coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: inc/device: Add extended capability ID for ATS
by David Hendricks (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Shuming Chu (Shuming), Tim Chu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71929 ) Change subject: inc/device: Add extended capability ID for ATS ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/71929/comment/2e72d128_cad1fb6e PS2, Line 471: #define PCIE_EXT_CAP_ID_ATS 0x000F > Got you. […] I think it's OK to merge this patch as-is. This one can simply update the generic PCIe capabilities list, CB:62883 adds some SOC-specific support. -- To view, visit https://review.coreboot.org/c/coreboot/+/71929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I777070ea223fc7e83c510c8eadbe4e028825eef6 Gerrit-Change-Number: 71929 Gerrit-PatchSet: 7 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 23:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: inc/device: Add extended capability ID for ATS
by David Hendricks (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Johnny Lin, Shuming Chu (Shuming), Tim Chu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71929 ) Change subject: inc/device: Add extended capability ID for ATS ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I777070ea223fc7e83c510c8eadbe4e028825eef6 Gerrit-Change-Number: 71929 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 23:40:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in libgfxinit[master]: common: Turn off VGA when not in use anymore
by Stefan Reinauer (Code Review) 04 Feb '23

04 Feb '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/72123 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: common: Turn off VGA when not in use anymore ...................................................................... common: Turn off VGA when not in use anymore When VGA mode is up on Alder Lake or Raptor Lake devices, `Update_Outputs' does successfully turn off graphics but it also leaves some undesirable configuration which can confuse following graphics drivers such as the PEIM graphics driver. Experimentally, we have identified that `libgfxinit' should turn off VGA when it disables the ouput which was using this mode. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen shows up on the recovery flow on skolas Change-Id: Id39c308a4d0408b996834439186645b33e692d02 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/72123 Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M common/hw-gfx-gma.adb 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: Stefan Reinauer: Verified Nick Vaccaro: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 1db493f..4a1050e 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -210,6 +210,10 @@ ("Disabling port " & Port_Names (Pipe_Cfg.Port))); pragma Debug (Debug.New_Line); + if Pipe_Cfg.Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET then + Display_Controller.Legacy_VGA_Off; + end if; + Connectors.Pre_Off (Port_Cfg); Display_Controller.Off (Pipe); Connectors.Post_Off (Port_Cfg); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/72123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id39c308a4d0408b996834439186645b33e692d02 Gerrit-Change-Number: 72123 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in libgfxinit[master]: common: Turn off VGA when not in use anymore
by Stefan Reinauer (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Nico Huber, Jérémy Compostella, Paul Menzel, Nick Vaccaro. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/72123 ) Change subject: common: Turn off VGA when not in use anymore ...................................................................... Patch Set 6: Verified+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/72123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id39c308a4d0408b996834439186645b33e692d02 Gerrit-Change-Number: 72123 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 23:36:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: update USB ports
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72773 ) Change subject: soc/amd/phoenix/chipset.cb: update USB ports ...................................................................... soc/amd/phoenix/chipset.cb: update USB ports Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 86 insertions(+), 37 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index d25ba37..9cebaab 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -172,23 +172,14 @@ device ref usb3_port0 on end end chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi device ref usb2_port0 on end end chip drivers/usb/acpi device ref usb2_port1 on end end - end - end - end - device ref xhci_1 on # USB 3.1 (USB1) - chip drivers/usb/acpi - device ref xhci_1_root_hub on - chip drivers/usb/acpi - device ref usb3_port2 on end - end - chip drivers/usb/acpi - device ref usb3_port3 on end - end chip drivers/usb/acpi device ref usb2_port2 on end end @@ -201,6 +192,18 @@ end end end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + end + end + end device ref acp on end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 10b7329..9d1a4b3 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -172,23 +172,14 @@ device ref usb3_port0 on end end chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi device ref usb2_port0 on end end chip drivers/usb/acpi device ref usb2_port1 on end end - end - end - end - device ref xhci_1 on # USB 3.1 (USB1) - chip drivers/usb/acpi - device ref xhci_1_root_hub on - chip drivers/usb/acpi - device ref usb3_port2 on end - end - chip drivers/usb/acpi - device ref usb3_port3 on end - end chip drivers/usb/acpi device ref usb2_port2 on end end @@ -201,6 +192,18 @@ end end end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + end + end + end device ref acp on end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 5763be8..2d92f14 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -45,11 +45,23 @@ device usb 3.0 alias usb3_port0 off end end chip drivers/usb/acpi + device usb 3.1 alias usb3_port1 off end + end + chip drivers/usb/acpi device usb 2.0 alias usb2_port0 off end end chip drivers/usb/acpi device usb 2.1 alias usb2_port1 off end end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port4 off end + end end end end @@ -58,19 +70,10 @@ register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off chip drivers/usb/acpi - device usb 3.0 alias usb3_port2 off end + device usb 3.0 alias usb3_port5 off end end chip drivers/usb/acpi - device usb 3.1 alias usb3_port3 off end - end - chip drivers/usb/acpi - device usb 2.0 alias usb2_port2 off end - end - chip drivers/usb/acpi - device usb 2.1 alias usb2_port3 off end - end - chip drivers/usb/acpi - device usb 2.2 alias usb2_port4 off end + device usb 2.0 alias usb2_port5 off end end end end @@ -89,8 +92,32 @@ ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.2 alias i2s_ac97 off end - device pci 0.3 alias usb4_xhci_0 off end - device pci 0.4 alias usb4_xhci_1 off end + device pci 0.3 alias usb4_xhci_0 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias usb4_xhci_0_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port6 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port6 off end + end + end + end + end + device pci 0.4 alias usb4_xhci_1 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias usb4_xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port7 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port7 off end + end + end + end + end device pci 0.5 alias usb4_router_0 off end device pci 0.6 alias usb4_router_1 off end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Gerrit-Change-Number: 72773 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72771 ) Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... soc/amd/phoenix/chipset.cb: add remaining PCI devices The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 37 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 787a6f3..d25ba37 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -204,16 +204,6 @@ device ref acp on end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - device ref xhci_2 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device usb 0.0 alias xhci_2_root_hub on - chip drivers/usb/acpi - device usb 2.0 alias usb2_port5 on end - end - end - end - end end end diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 8f33dd1..10b7329 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -204,16 +204,6 @@ device ref acp on end # Audio Processor (ACP) end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C - device ref xhci_2 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device usb 0.0 alias xhci_2_root_hub on - chip drivers/usb/acpi - device usb 2.0 alias usb2_port5 on end - end - end - end - end end end diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index f1c32fa..5763be8 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -25,6 +25,12 @@ device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 alias usb4_pcie_bridge_0 off end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 alias usb4_pcie_bridge_1 off end + device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops @@ -73,10 +79,20 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops + device pci 0.0 on end # dummy, do not disable + device pci 0.1 alias ipu off end + end + device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops - device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + device pci 0.0 on end # dummy, do not disable + device pci 0.2 alias i2s_ac97 off end + device pci 0.3 alias usb4_xhci_0 off end + device pci 0.4 alias usb4_xhci_1 off end + device pci 0.5 alias usb4_router_0 off end + device pci 0.6 alias usb4_router_1 off end end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
by Jonathan Zhang (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Angel Pons, Jian-Ming Wang, Arthur Heymans, Tim Chu, Shelly Chang. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71958 ) Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/71958/comment/78d57248_cc4f4674 PS2, Line 147: pds. > The pds is a global variable defined in numa.h which is not included in this patch. […] Right on, Thank you Jian-Ming! I agree that adding g_ prefix makes sense, but I did not see other coreboot code doing that, so I did not add so. I do think it makes sense though. -- To view, visit https://review.coreboot.org/c/coreboot/+/71958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Gerrit-Change-Number: 71958 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 19:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Jian-Ming Wang <jianmingW(a)supermicro.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72737 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 31 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index a4f18a3..787a6f3 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index ec88892..8f33dd1 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_1 on end # GBE + device ref gpp_bridge_2_2 on end # WIFI + device ref gpp_bridge_2_3 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 47b393d..f1c32fa 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -17,12 +17,13 @@ device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + # The PCIe GPP aliases in this SoC match the device and function numbers + device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72736 ) Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is due to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 38 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 5c341c8..47b393d 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -9,7 +9,12 @@ device pci 00.0 alias gnb on ops phoenix_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge + device pci 01.0 on end # Dummy Host Bridge, do not disable + # The PCIe GPP aliases in this SoC match the device and function numbers + device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Update ASPM settings for the NVMe device
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72391 ) Change subject: mb/google/skyrim: Update ASPM settings for the NVMe device ...................................................................... mb/google/skyrim: Update ASPM settings for the NVMe device This enables L1.2 for the SSD port. link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference. Enabling L1.2 on other devices currently causes problems. Debug is ongoing. BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 27 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index d745bd7..0046a33 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -16,7 +16,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .clk_req = CLK_REQ2, }, { /* SD */ @@ -29,7 +28,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .gpio_group_id = GPIO_27, .clk_req = CLK_REQ1, }, @@ -43,7 +41,7 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, + .link_aspm_L1_2 = true, .gpio_group_id = GPIO_6, .clk_req = CLK_REQ0, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/72391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Gerrit-Change-Number: 72391 Gerrit-PatchSet: 7 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2023