coreboot-gerrit February 2023

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by char (Code Review) 04 Feb '23

04 Feb '23

char has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca --- M src/mainboard/acer/swift3-SF314-52G-55WQ/Kconfig M src/mainboard/acer/swift3-SF314-52G-55WQ/Makefile.inc M src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ac.asl M src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl M src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ec.asl M src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/mainboard.asl A src/mainboard/acer/swift3-SF314-52G-55WQ/bootblock.c M src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb D src/mainboard/acer/swift3-SF314-52G-55WQ/gma-mainboard.ads M src/mainboard/acer/swift3-SF314-52G-55WQ/gpio.h A src/mainboard/acer/swift3-SF314-52G-55WQ/gpio_early.c A src/mainboard/acer/swift3-SF314-52G-55WQ/mainboard.c M src/mainboard/acer/swift3-SF314-52G-55WQ/ramstage.c M src/superio/ite/Makefile.inc A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/chip.h A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 19 files changed, 1,954 insertions(+), 275 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/72788/1 diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/Kconfig b/src/mainboard/acer/swift3-SF314-52G-55WQ/Kconfig index c835497..ea9b321 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/Kconfig +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/Kconfig @@ -5,53 +5,52 @@ select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8987E + select SUPERIO_ITE_ENV_CTRL select SOC_INTEL_KABYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 select DRIVERS_I2C_HID select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select DRIVERS_GENERIC_CBFS_SERIAL select HAVE_SPD_IN_CBFS - select S3_VGA_ROM_RUN - select PCI_OPTION_ROM_RUN_REALMODE - select SMMSTORE - select SPI_FLASH_SMM - select DISPLAY_HOBS - select DISPLAY_UPD_DATA - select DISPLAY_MTRRS - select DISPLAY_FSP_CALLS_AND_STATUS - select DISPLAY_FSP_HEADER - select VERIFY_HOBS - select CONFIG_DEBUG_GPIO - select CONFIG_DEBUG_CBFS - select DEBUG_SMBUS - select DEBUG_SMI - select DEBUG_MALLOC - select REALMODE_DEBUG - select DEBUG_SPI_FLASH - select DEBUG_BOOT_STATE - select HAVE_EM100_SUPPORT + select INTEL_GMA_HAS_VBT + select EC_ACPI + select HAVE_INTEL_PTT + select NO_UART_ON_SUPERIO + select CRB_TPM +config INTEL_GMA_VBT_FILE + default "3rdparty/fsp/KabylakeFspBinPkg/SampleCode/Vbt/Vbt.bin" + +config EC_USE_LGMR + bool "Use LPC generic memory range for EC" + help + Using MMIO accesses for EC range can improve performance. + +config SF314_USE_GPU + bool "Enable power on of GPU in SF314" + default n + help + This will enable powering on of the GPU so it is detected. Requires having the required option ROM loaded as well (too big for SeaBIOS). + +config ONBOARD_VGA_IS_PRIMARY + default y + +config VGA_BIOS_DGPU_ID + default "10de,1d10" + +config VGA_BIOS_ID + default "8086,5917" config SEABIOS_DEBUG_LEVEL int - default 6 - -config SMMSTORE_SIZE - string - default "0x40000" + default 3 config PRE_GRAPHICS_DELAY_MS int default 0 - -config VGA_BIOS_ID - string - default "8086,5917" - config MAINBOARD_FAMILY string default "SWIFT3" diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/Makefile.inc b/src/mainboard/acer/swift3-SF314-52G-55WQ/Makefile.inc index 921bb4f..7e39b09 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/Makefile.inc +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/Makefile.inc @@ -1,8 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + ramstage-y += ramstage.c ramstage-y += hda_verb.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads - SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 8GB diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ac.asl b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ac.asl index 0b3739f..3a1fa68 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ac.asl +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ac.asl @@ -7,11 +7,12 @@ Method (_PSR) { - Return (ACEX) + Return (EPWS & 0x1) } Method (_STA) { Return (0x0F) } + } diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl index 8f19555..e2d14b5 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl @@ -8,20 +8,37 @@ Name (BSTP, 0) +Name (NBIF, Package (0x0D) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + "", + "", + "", + "" + }) + Name (PBIF, Package () { 0x00000001, /* 0x00: Power Unit: mAh */ - 0xFFFFFFFF, /* 0x01: Design Capacity */ - 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00001770, /* 0x01: Design Capacity */ + 0x00001770, /* 0x02: Last Full Charge Capacity */ 0x00000001, /* 0x03: Battery Technology: Rechargeable */ - 0xFFFFFFFF, /* 0x04: Design Voltage */ - 0x00000003, /* 0x05: Design Capacity of Warning */ - 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ - 0x00000001, /* 0x07: Capacity Granularity 1 */ - 0x00000001, /* 0x08: Capacity Granularity 2 */ - "Razer Blade Stealth", - "SERIAL", - "LiIon", - "Razer" + 0x000039D0, /* 0x04: Design Voltage */ + 0x00000258, /* 0x05: Design Capacity of Warning */ + 0x0000012C, /* 0x06: Design Capacity of Low */ + 0x0000003C, /* 0x07: Capacity Granularity 1 */ + 0x0000003C, /* 0x08: Capacity Granularity 2 */ + "Model", + " ", + "LIon", + "OEM" }) @@ -32,35 +49,104 @@ 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ }) - Method (_STA, 0, Serialized) - { - Return (0x1F) - } - Method (_BIF, 0, Serialized) - { - /* Last Full Charge Capacity */ - PBIF [2] = BFCP + Name (BSLF, 0) + Name (LFCC, 0x1770) + Name (LOW2, 0x012C) + Name (DVOT, 0x0E) + Name (PUNT, One) + Name (LFC0, Zero) + Name (LFC1, Zero) - /* Design Voltage */ - PBIF [4] = BDVT + Mutex (MUBT, 0x00) - /* Design Capacity */ - PBIF [1] = BDCP +Method (_STA, 0, NotSerialized) // _STA: Status + { + If (DC_P (0)) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } - /* Design Capacity of Warning */ - PBIF [5] = BDCP / 50 - /* Design Capacity of Low */ - PBIF [6] = BDCP / 100 + Name (KBFF, One) + Method (_BIF, 0, Serialized) // _BIF: Battery Information + { + If ((KBFF == One)) + { + KBFF = Zero + Local0 = PKBC + If ((Local0 & One)) + { + Local0 = PKBD + } + } - PBIF [10] = ToString (BSER, Ones) +// Return (^^LPCB.EC0.BS_L (Zero)) +//Method (BS_L, 1, Serialized) +// { + If (!BT_P (0)) + { + Return (NBIF) /* \_SB_.PCI0.LPCB.EC0_.NBIF */ + } - Return (PBIF) - } + If ((EB1T == 0xFF)) + { + Return (NBIF) /* \_SB_.PCI0.LPCB.EC0_.NBIF */ + } + + If ((Acquire (MUBT, 0xFFFF) == Zero)) + { + BSLF = Zero + PBIF [0x09] = BD_N () + Local0 = BP_U () + Local1 = BD_C () + Local2 = BL_F () + LFC0 = Local2 + + Local3 = BT_C () + Local4 = BD_V () + If ((Local0 != Ones)) + { + If ((Local1 != Ones)) + { + If ((Local2 != Ones)) + { + If ((Local3 != Ones)) + { + If ((Local4 != Ones)) + { + BI_F (Local0, Local1, Local2, Local3, Local4) + } + } + } + } + } + +Release (MUBT) + } + + If ((PUNT == Zero)) + { + Local2 *= 0x0A + } + + LFCC = Local2 + Return (PBIF) /* \_SB_.PCI0.LPCB.EC0_.PBIF */ + } + + + + + Method (_BST, 0, Serialized) { +// BS_P(0) /* * 0: BATTERY STATE * @@ -69,38 +155,318 @@ * bit 2 = critical level */ - /* Check if AC is present */ - If (ACEX) { - /* Read battery status from EC */ - Local0 = BCST - } Else { - /* Always discharging when on battery power */ - Local0 = 0x01 + PBST [0] = Zero + PBST [1] = Ones + PBST [2] = Ones + PBST [3] = Ones + + If (!DC_P(0)) + { + Return (PBST) } - PBST [0] = Local0 - - /* Notify if battery state has changed since last time */ - If (Local0 != BSTP) { - BSTP = Local0 - Notify (BAT, 0x80) + If (EB0T == 0xFF) + { + Return (PBST) } - /* - * 1: BATTERY PRESENT RATE - */ - PBST [1] = BCRT + If ((Acquire (MUBT, 0xFFFF) == 0)) + { + BSLF = 0 + Local0 = BS_T () + Local1 = BC_R () + Local2 = BR_C () + Local3 = BV_T () - /* - * 2: BATTERY REMAINING CAPACITY - */ - PBST [2] = BRCP + If ((Local0 != Ones) && (Local1 != Ones) && (Local2 != Ones) && (Local3 != Ones)) + { + BS_C (Local0, Local1, Local2, Local3, 0) + } + - /* - * 3: BATTERY PRESENT VOLTAGE - */ - PBST [3] = BCVT + Release (MUBT) + } + + Local4 = LFCC + Divide (LFCC, 0x64, Local5, Local4) + Local5 = BL_F () + + If (PUNT == 0) + { + Local5 *= 0x0A + } + + If (LFCC >= Local5) + { + Local5 = (LFCC - Local5) + } + Else + { + Local5 -= LFCC + } + + If (Local5 > Local4) + { + Notify (BAT, 0x81) + } Return (PBST) } + + + Method (BS_T, 0, Serialized) + { + If (BSLF) + { + Local0 = B1ST /* \_SB_.PCI0.LPCB.EC0_.B1ST */ + } + Else + { + Local0 = B0ST /* \_SB_.PCI0.LPCB.EC0_.B0ST */ + } + + Return (Local0) + } + + Method (BC_R, 0, Serialized) + { + If (BSLF) + { + Local0 = B1CC /* \_SB_.PCI0.LPCB.EC0_.B1CC */ + } + Else + { + Local0 = B0CC /* \_SB_.PCI0.LPCB.EC0_.B0CC */ + } + + Return (Local0) + } + +Method (BR_C, 0, Serialized) + { + If (BSLF) + { + Local0 = B1RC /* \_SB_.PCI0.LPCB.EC0_.B1RC */ + } + Else + { + Local1 = RR_M (0x0382) + If ((Local1 & 0x10)) + { + Local0 = B0FC /* \_SB_.PCI0.LPCB.EC0_.B0FC */ + } + Else + { + Local0 = B0RC /* \_SB_.PCI0.LPCB.EC0_.B0RC */ + } + } + + If ((Local0 == 0xFFFF)) + { + Local0 = Ones + } + + Return (Local0) + } + + Method (BV_T, 0, Serialized) + { + If (BSLF) + { + Local0 = B1VL /* \_SB_.PCI0.LPCB.EC0_.B1VL */ + } + Else + { + Local0 = B0VL /* \_SB_.PCI0.LPCB.EC0_.B0VL */ + } + + Return (Local0) + } + + + +Method (BS_C, 5, NotSerialized) + { + Local1 = (Arg1 & 0xFFFF) + Local0 = Zero + If (AP_S ()) + { + Local0 = One + } + + If (Local0) + { + If (BC_H (Arg4)) + { + Local0 = 0x02 + } + Else + { + Local0 = Zero + } + } + Else + { + Local0 = One + } + + Local2 = (Arg0 & 0x0300) + If (Local2) + { + Local2 = 0x04 + Local0 |= Local2 + } + + If ((Local1 >= 0x8000)) + { + Local1 = (0xFFFF - Local1) + } + + Local2 = Arg2 + If ((PUNT == Zero)) + { + Local1 *= DVOT /* \_SB_.PCI0.LPCB.EC0_.DVOT */ + Local2 *= 0x0A + } +Local3 = (Local0 & 0x02) + If (!Local3) + { + Local3 = (LFCC - Local2) + Divide (LFCC, 0x64, Local4, Local5) + If ((Local3 <= Local5)) + { + Local2 = LFCC /* \_SB_.PCI0.LPCB.EC0_.LFCC */ + } + } + Else + { + Divide (LFCC, 0x64, Local4, Local5) + Local4 = (LFCC - Local5) + If ((Local2 > Local4)) + { + Local2 = Local4 + } + } + + If (!AP_S ()) + { + Divide (Local2, 0x0A, Local3, Local4) + If ((Local1 < Local4)) + { + Local1 = Local4 + } + } + + If ((AP_S () && BC_F (Arg4))) + { + Local0 &= 0x05 + Local2 = LFCC /* \_SB_.PCI0.LPCB.EC0_.LFCC */ + } + + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Arg3 + } + + + Method (BL_F, 0, Serialized) + { + If (BSLF) + { + Local0 = B1FC + } + Else + { + Local0 = B0FC + } + + Local0 &= 0xFFFF + Return (Local0) + } + + + +Method (BC_H, 1, Serialized) + { + If (Arg0) + { + Local0 = EB1S /* \_SB_.PCI0.LPCB.EC0_.EB1S */ + } + Else + { + Local0 = EB0S /* \_SB_.PCI0.LPCB.EC0_.EB0S */ + Local0 &= 0xFF + If ((Local0 != 0xFF)) + { + Local0 &= 0x02 + } + Else + { + Local0 = Zero + } + } + + Return (Local0) + } + +Method (BC_F, 1, Serialized) + { + If (Arg0) + { + Local0 = EB1S /* \_SB_.PCI0.LPCB.EC0_.EB1S */ + } + Else + { + Local0 = EB0S /* \_SB_.PCI0.LPCB.EC0_.EB0S */ + } + + Local0 &= 0xFF + If ((Local0 != 0xFF)) + { + Local0 &= 0x10 + Local0 >>= 0x04 + } + Else + { + Local0 = Zero + } + + Return (Local0) + } + +Method (BI_F, 5, NotSerialized) + { + PUNT = Arg0 + Local1 = Arg1 + Local2 = Arg2 + If ((PUNT == Zero)) + { + Local1 *= 0x0A + Local2 *= 0x0A + } + + PBIF [Zero] = PUNT /* \_SB_.PCI0.LPCB.EC0_.PUNT */ + PBIF [One] = Local1 + PBIF [0x02] = Local2 + LFCC = Local2 + PBIF [0x03] = Arg3 + PBIF [0x04] = Arg4 + Divide (Local2, 0x64, , Local5) + Local6 = (Local5 * 0x0A) + PBIF [0x05] = Local6 + Local6 = (Local5 * 0x05) + PBIF [0x06] = Local6 + Divide (Local1, 0x64, , Local7) + PBIF [0x07] = Local7 + PBIF [0x08] = Local7 + If (PUNT) + { + If ((DerefOf (PBIF [One]) == Zero)) + { + PBIF [Zero] = Zero + } + } + } + } diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ec.asl b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ec.asl index 7325562..63ea906 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ec.asl +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/ec.asl @@ -11,8 +11,44 @@ IO (Decode16, 0x66, 0x66, 0, 1) }) + +Name (WRQK, 0x02) + Name (RDQK, 0x03) + Name (SDBT, 0x04) + Name (RCBT, 0x05) + Name (WRBT, 0x06) + Name (RDBT, 0x07) + Name (WRWD, 0x08) + Name (RDWD, 0x09) + Name (WRBL, 0x0A) + Name (RDBL, 0x0B) + Name (WBLP, 0x8A) + Name (RBLP, 0x8B) + Name (PCLL, 0x0C) + Name (GOOD, Zero) + Name (UKER, 0x07) + Name (DAER, 0x10) + Name (DERR, 0x11) + Name (CMDN, 0x12) + Name (UKE2, 0x13) + Name (DADN, 0x17) + Name (SBTO, 0x18) + Name (USPT, 0x19) + Name (SBBY, 0x1A) + +Name (BADR, 0x0B) + Name (CADR, 0x09) + Name (SADR, 0x0A) + Name (ISHE, Zero) + +Name (KBCM, Zero) + + Name (ACEX, 0) +Mutex (MUEC, 0x00) + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { @@ -53,6 +89,122 @@ LIDS, 8 // Lid state } + // this is set inside the ITE/EC and memory mapped in mainboard.c + OperationRegion (ECW1, SystemMemory, 0xFEFF0380, 0x80) + Field (ECW1, ByteAcc, Lock, Preserve) + { + Offset (0x01), + EPWS, 8, + EB0S, 8, + EB1S, 8, + EB0R, 8, + EB1R, 8, + EB0T, 8, + EB1T, 8, + OCOT, 8, + Offset (0x10), + B0PN, 16, + B0VL, 16, + B0RC, 16, + B0FC, 16, + B0ST, 16, + B0CC, 16, + B0TM, 16, + B0C1, 16, + B0CV, 16, + Offset (0x30), + B1PN, 16, + B1VL, 16, + B1RC, 16, + B1FC, 16, + B1ST, 16, + B1CC, 16, + B1TM, 16, + B1C1, 16, + B1CV, 16, + Offset (0x50), + B0DC, 16, + B0DV, 16, + B0SN, 16, + B0MD, 16, + B1DC, 16, + B1DV, 16, + B1SN, 16, + B1MD, 16, + TH1R, 8, + TH1L, 8, + TH0R, 8, + TH0L, 8, + ECRT, 8, + EPSV, 8, + EACT, 8, + TERR, 8, + F0TS, 16, + F1TS, 16, + F0CS, 8, + F1CS, 8, + PCPT, 16, + ALSC, 8, + Offset (0x72), + ALSU, 16, + ALSL, 16, + ALSX, 16, + BRTC, 8, + BCDV, 8, + AINP, 16 + } + +OperationRegion (ECW2, SystemMemory, 0xFEFF0700, 0x80) + Field (ECW2, ByteAcc, Lock, Preserve) + { + ESEM, 8, + CMD1, 8, + CDT1, 8, + CDT2, 8, + CDT3, 8, + CDT4, 8, + CDT5, 8, + CDT6, 8, + CDT7, 8, + CDT8, 8, + CDT9, 8, + CD10, 8, + CD11, 8, + CD12, 8, + Offset (0x40), + EDA1, 8, + EDA2, 8, + EDA3, 8, + EDA4, 8, + EDA5, 8, + EDA6, 8, + EDA7, 8, + EDA8, 8, + EDA9, 8, + ED10, 8, + ED11, 8, + ED12, 8 + } + + OperationRegion (PKBS, SystemIO, 0x60, 0x05) + Field (PKBS, ByteAcc, Lock, Preserve) + { + PKBD, 8, + Offset (0x02), + Offset (0x03), + Offset (0x04), + PKBC, 8 + } + +OperationRegion (ECBD, SystemMemory, 0xFEFF0700, 0x80) + Field (ECBD, ByteAcc, Lock, Preserve) + { + Offset (0x40), + Offset (0x41), + BCNT, 8, + BDAT, 240 + } + Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ @@ -63,29 +215,518 @@ } - // Close ? - Method (_Q14, 0, NotSerialized) - { - \LIDS = LIDS - Notify (LID0, 0x80) - } + Method (_Q81, 0, NotSerialized) + { + Notify (LID0, 0x80) // Status Change + } - //Open - Method (_Q15, 0, NotSerialized) - { - \LIDS = LIDS - Notify (LID0, 0x80) - } + Method (AC_P, 0, Serialized) + { + Return (EPWS & 0x1) + } + + Method (DC_P, 1, Serialized) + { + Local0 = EPWS + If (Arg0) + { + Local0 &= 0x04 + } + Else + { + Local0 &= 0x02 + } + + If (Local0) + { + Local0 = One + } + Else + { + Local0 = Zero + } + + Return (Local0) + } + + Method (AP_S, 0, Serialized) + { + Local0 = (EPWS & One) + Return (Local0) + } // AC plugged - Method (_Q13, 0, NotSerialized) - { - ACEX = PWRS - 0x82 - Notify (BAT, 0x80) // Status Change - Notify (BAT, 0x81) // Information Change - Notify (AC, 0x80) // Status Change - } +// Method (_Q13, 0, NotSerialized) +// { +// ACEX = PWRS - 0x82 +// Notify (BAT, 0x80) // Status Change +// Notify (BAT, 0x81) // Information Change +// Notify (AC, 0x80) // Status Change +// } + +Method (_Q13, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + KBCM = One + EX_T (0xC8, Zero, One, Zero, Zero, Zero) + Local0 = KBLS /* \KBLS */ + Local0 &= 0x03 + If ((Local0 < 0x02)) + { + Local0++ + } + + KBLS = Local0 + KBST = One +// If (^^^WMID.LMST) +// { +// ^^^WMID.FEBC [Zero] = One +// ^^^WMID.FEBC [One] = 0x84 +// Notify (WMID, 0xBC) // Device-Specific +// } + } + + +Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (AC_P ()) + { + AC_F = One +// Local0 = 0x58 +// If ((GGOV (0x02030006) == Zero)) {} +// Else +// { +// Notify (^^^RP01.PXSX, 0xD1) // Hardware-Specific +// } + } + Else + { + AC_F = Zero +// Local0 = 0x57 +// If ((GGOV (0x02030006) == Zero)) {} +// Else +// { +// Notify (^^^RP01.PXSX, 0xD2) // Hardware-Specific +// } + } + + PWRS = AC_F /* \AC_F */ +// If (^^^WMID.LMST) +// { +// ^^^WMID.FEBC [Zero] = 0x08 +// Notify (WMID, 0xBC) // Device-Specific +// } + + + Notify (AC, 0x80) // Status Change + Sleep (0x14) + PNOT () + Sleep (0x0A) + NB_T (0x80) + } + + + + // Battery + Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (DC_P(0)) + { + Sleep (0x07D0) + } + + Notify (BAT, 0x80) // Status Change + Notify (BAT, 0x81) // Information Change + } + + Method (_QA3, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT, 0x80) // Status Change + } + + Method (_QA5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT, 0x80) // Status Change + } + + + + Method (BT_P, 1, Serialized) + { + Return ( DC_P(Arg0) ) + } + + Method (NB_T, 1, NotSerialized) + { + If ( BT_P(0) ) + { + Notify (BAT, Arg0) + } + } + +Method (BD_N, 0, Serialized) + { + Name (BSTR, Buffer (0x20) {}) + Local0 = SR_T (RDBL, BADR, 0x21) + If ((DerefOf (Local0 [Zero]) != Zero)) + { + BSTR [0x04] = Zero + } + Else + { + BSTR = DerefOf (Local0 [0x02]) + BSTR [DerefOf (Local0 [One])] = Zero + } + + Return (BSTR) /* \_SB_.PCI0.LPCB.EC0_.BD_N.BSTR */ + } + + +Method (SR_T, 3, Serialized) + { + Local0 = Package (0x03) + { + 0x07, + Zero, + Zero + } + + If ((Arg0 != RDBL)) + { + If ((Arg0 != RDWD)) + { + If ((Arg0 != RDBT)) + { + If ((Arg0 != RCBT)) + { + If ((Arg0 != RDQK)) + { + If ((Arg0 != RBLP)) + { + Return (Local0) + } + } + } + } + } + } +If ((Acquire (MUEC, 0xFFFF) == Zero)) + { + CDT1 = Zero + CDT2 = Arg0 + Local1 = (Arg1 << One) + CDT3 = Local1 + CDT4 = Arg2 + CDT5 = Zero + CMD1 = 0x9A + ESEM = 0x0F + Local2 = 0xFA + While ((Local2 && CMD1)) + { + Sleep (0x02) + Local2-- + } + + If ((CMD1 == Zero)) + { + If ((EDA1 == 0x80)) + { + Local0 [Zero] = GOOD /* \_SB_.PCI0.LPCB.EC0_.GOOD */ + If ((Arg0 == RDBL)) + { + Local0 [One] = BCNT /* \_SB_.PCI0.LPCB.EC0_.SR_T.BCNT */ + Local0 [0x02] = BDAT /* \_SB_.PCI0.LPCB.EC0_.SR_T.BDAT */ + } + + If ((Arg0 == RBLP)) + { + Local0 [One] = BCNT /* \_SB_.PCI0.LPCB.EC0_.SR_T.BCNT */ + Local0 [0x02] = BDAT /* \_SB_.PCI0.LPCB.EC0_.SR_T.BDAT */ + } + + If ((Arg0 == RDWD)) + { + Local0 [One] = 0x02 + Local1 = EDA3 /* \_SB_.PCI0.LPCB.EC0_.EDA3 */ + Local1 <<= 0x08 + Local1 |= EDA2 /* \_SB_.PCI0.LPCB.EC0_.EDA2 */ + Local0 [0x02] = Local1 + } +If ((Arg0 == RDBT)) + { + Local0 [One] = One + Local0 [0x02] = EDA2 /* \_SB_.PCI0.LPCB.EC0_.EDA2 */ + } + + If ((Arg0 == RCBT)) + { + Local0 [One] = One + Local0 [0x02] = EDA2 /* \_SB_.PCI0.LPCB.EC0_.EDA2 */ + } + } + } + Else + { + Local0 [Zero] = UKER /* \_SB_.PCI0.LPCB.EC0_.UKER */ + Local0 [One] = Zero + Local0 [0x02] = 0xFF + } + + Release (MUEC) + } + + Return (Local0) + } + +Method (RR_M, 1, Serialized) + { + If ((Acquire (MUEC, 0xFFFF) == Zero)) + { + Local0 = Arg0 + Local1 = (Local0 & 0xFF) + Local0 >>= 0x08 + Local0 &= 0xFF + CDT2 = Local1 + CDT1 = Local0 + CMD1 = 0x80 + ESEM = 0x0F + Local0 = 0x7F + While ((Local0 && CMD1)) + { + Sleep (One) + Local0-- + } + + If ((CMD1 == Zero)) + { + Local0 = EDA1 /* \_SB_.PCI0.LPCB.EC0_.EDA1 */ + } + Else + { + Local0 = Ones + } + + Release (MUEC) + Return (Local0) + } + + Return (Ones) + } + +Method (BP_U, 0, Serialized) + { + If (BSLF) + { + Local0 = B1MD /* \_SB_.PCI0.LPCB.EC0_.B1MD */ + } + Else + { + Local0 = B0MD /* \_SB_.PCI0.LPCB.EC0_.B0MD */ + } + + If ((Local0 != 0xFFFF)) + { + Local1 = (Local0 >> 0x0F) + Local1 &= One + Local0 = (Local1 ^ One) + } + + Return (Local0) + } + + +Method (BD_C, 0, Serialized) + { + If (BSLF) + { + Local0 = B1DC /* \_SB_.PCI0.LPCB.EC0_.B1DC */ + } + Else + { + Local0 = B0DC /* \_SB_.PCI0.LPCB.EC0_.B0DC */ + Local1 = 0x03 + While ((Local1 != Zero)) + { + Local0 = B0DC /* \_SB_.PCI0.LPCB.EC0_.B0DC */ + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Local1-- + WR_M (0x06B0, Zero) + Sleep (0x64) + Local0 = RR_M (0x06B0) + If ((Local0 & 0x10)) + { + Local0 = B0DC /* \_SB_.PCI0.LPCB.EC0_.B0DC */ + } + } + Else + { + Local1 = Zero + } + } + } + + Local0 &= 0xFFFF + Return (Local0) + } + +Method (BT_C, 0, Serialized) + { + If (BSLF) + { + Local0 = B1MD /* \_SB_.PCI0.LPCB.EC0_.B1MD */ + } + Else + { + Local0 = B0MD /* \_SB_.PCI0.LPCB.EC0_.B0MD */ + } + + If ((Local0 != 0xFFFF)) + { + Local0 >>= 0x09 + Local0 &= One + Local0 ^= One + } + Else + { + Local0 = Zero + } + + Return (Local0) + } + + +Method (BD_V, 0, Serialized) + { + If (BSLF) + { + Local0 = B1DV /* \_SB_.PCI0.LPCB.EC0_.B1DV */ + } + Else + { + Local1 = 0x03 + While ((Local1 != Zero)) + { + Local0 = B0DV /* \_SB_.PCI0.LPCB.EC0_.B0DV */ + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Local1-- + WR_M (0x06B0, Zero) + Sleep (0x64) + Local0 = RR_M (0x06B0) + If ((Local0 & 0x10)) + { + Local0 = B0DV /* \_SB_.PCI0.LPCB.EC0_.B0DV */ + } + } + Else + { + Local1 = Zero + } + } + } + + Return (Local0) + } + +Name (BSLF, Zero) + Method (BS_F, 1, Serialized) + { + If (Arg0) + { + BSLF = One + } + Else + { + BSLF = Zero + } + } + + +Method (WR_M, 2, Serialized) + { + If ((Acquire (MUEC, 0xFFFF) == Zero)) + { + Local0 = Arg0 + Local1 = (Local0 & 0xFF) + Local0 >>= 0x08 + Local0 &= 0xFF + CDT2 = Local1 + CDT1 = Local0 + CDT3 = Arg1 + CMD1 = 0x81 + ESEM = 0x0F + Local0 = 0x7F + While ((Local0 && CMD1)) + { + Sleep (One) + Local0-- + } + + If ((CMD1 == Zero)) + { + Local0 = One + } + Else + { + Local0 = Ones + } + + Release (MUEC) + Return (Local0) + } + + Return (Ones) + } + + +Method (EX_T, 6, NotSerialized) + { + Local1 = Package (0x06) + { + 0x10, + Zero, + Zero, + Zero, + Zero, + Zero + } + If ((Acquire (MUEC, 0xFFFF) == Zero)) + { + CDT1 = Arg1 + CDT2 = Arg2 + CDT3 = Arg3 + CDT4 = Arg4 + CDT5 = Arg5 + CMD1 = Arg0 + ESEM = 0x0F + Local0 = 0x7F + While ((Local0 && CMD1)) + { + Sleep (One) + Local0-- + } + + If ((CMD1 == Zero)) + { + Local1 [Zero] = Zero + Local1 [One] = EDA1 /* \_SB_.PCI0.LPCB.EC0_.EDA1 */ + Local1 [0x02] = EDA2 /* \_SB_.PCI0.LPCB.EC0_.EDA2 */ + Local1 [0x03] = EDA3 /* \_SB_.PCI0.LPCB.EC0_.EDA3 */ + Local1 [0x04] = EDA4 /* \_SB_.PCI0.LPCB.EC0_.EDA4 */ + Local1 [0x05] = EDA5 /* \_SB_.PCI0.LPCB.EC0_.EDA5 */ + } + Else + { + Local1 [Zero] = 0x10 + } + + Release (MUEC) + } + + Return (Local1) + } + #include "ac.asl" #include "battery.asl" diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/mainboard.asl b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/mainboard.asl index be4aa5d..5b5fff0 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/mainboard.asl +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/mainboard.asl @@ -25,3 +25,105 @@ } } + + OperationRegion (PECM, SystemIO, 0x72, 0x02) + Field (PECM, ByteAcc, Lock, Preserve) + { + EIND, 8, + EDAT, 8 + } + + IndexField (EIND, EDAT, ByteAcc, NoLock, Preserve) + { + Offset (0xE0), + RAMB, 32, + OTPE, 8, + RESV, 24, + CTPF, 8, + WLDP, 1, + BTDP, 1, + RES1, 2, + WRST, 1, + BRST, 1, + RES2, 2, + FSCU, 8, + RSDF, 8, + ABTY, 8, + FANS, 1, + WWKS, 1, + PFNS, 2, + FGPU, 1, + RES4, 1, + CLS1, 2, + CLS2, 2, + CLS3, 2, + CLS4, 2, + CLS5, 2, + QFKF, 2, + LBAR, 2, + KBLD, 4, + S3TL, 8, + S3TH, 8, + ES3M, 1, + SS3F, 1, + ADAP, 2, + LOCS, 2, + RES3, 2, + I2CT, 1, + TCTP, 2, + KBLS, 2, + KBST, 1, + RES5, 2, + RES6, 8, + LDDF, 8, + S3FA, 8, + POS0, 8, + POS1, 8, + POS2, 8, + POS3, 8, + POS4, 8, + POS5, 8, + MANN, 8, + ISXX, 8, + RES7, 8 + } + +OperationRegion (RAMW, SystemMemory, RAMB, 0x0100) + Field (RAMW, AnyAcc, NoLock, Preserve) + { + TT_P, 8, + FS_F, 8, + FS_T, 16, + FA_D, 32, + FS_Z, 16, + ST_P, 8, + MN_A, 64, + BT_P, 8, + AL_D, 32, + DB_1, 8, + DB_2, 32, + DB_3, 32, + DB_4, 32, + RT_W, 16, + PM_B, 32, + PM_S, 8, + AC_F, 8, + DC_F, 8, + DC_2, 8, + VG_F, 16, + PD_L, 16, + CD_L, 16, + CD_S, 16, + ND_S, 16, + SD_S, 16, + CN_R, 8, + TJ_M, 16, + TR_T, 8, + CR_T, 8, + PC_P, 8, + S3_E, 16, + S3_B, 16, + S3_O, 16 + } + + diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/bootblock.c b/src/mainboard/acer/swift3-SF314-52G-55WQ/bootblock.c new file mode 100644 index 0000000..463af0f --- /dev/null +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/bootblock.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> +#include "gpio.h" + +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> + +// out +#define DGPU_HOLD_RSTN GPP_D12 /* Active low */ +#define VGA_AON_PWR_EN GPP_D9 /* Active high */ +// in +#define GPU_ID GPP_D8 /* 1 N17S, 0 N16S */ +#define DGPU_PWROK GPP_D5 /* Active high */ +#define CPU_ID GPP_D7 +#define BID_GPU GPP_D14 +#define PCB_ID0 GPP_C13 +#define PCB_ID1 GPP_C14 +#define PCB_ID2 GPP_C23 + +/* Tested for SF314 only */ +static void board_detect(void) +{ + uint8_t id_cpu, id_pcb[3], id_gpu, bid_gpu, dgpu_power_ok, combined; + printk(BIOS_DEBUG, "Mainboard: Detecting board, CPU, GPU IDs\n"); + + id_cpu = gpio_get(CPU_ID); + id_pcb[0] = gpio_get(PCB_ID0); + id_pcb[1] = gpio_get(PCB_ID1); + id_pcb[2] = gpio_get(PCB_ID2); + id_gpu = gpio_get(GPU_ID); + bid_gpu = gpio_get(BID_GPU); + dgpu_power_ok = gpio_get(DGPU_PWROK); + + printk(BIOS_DEBUG, "CPU ID 0x%x\n", id_cpu); + printk(BIOS_DEBUG, "GPU ID 0x%x BID 0x%x POWER_OK 0x%x\n", id_gpu, bid_gpu, dgpu_power_ok); + printk(BIOS_DEBUG, "PCB ID0 0x%x ID1 0x%x ID2 0x%x\n", id_pcb[0], id_pcb[1], id_pcb[2]); + + combined = (id_cpu << 5) | (id_pcb[0] << 4) | (id_pcb[1] << 3) | (id_pcb[2] << 2) | (bid_gpu << 1) | id_gpu; + + switch(combined) + { + // SF314-52G-55WQ 0b0011_1010 + case 0x3A: + printk(BIOS_INFO, "GPIOs indicate Acer Swift SF314-52G-55WQ\n"); + break; + default: + printk(BIOS_WARNING, "Warning! Unknown mainboard configuration! Proceed at own risk!\n"); + } +} + +static void dgpu_power_on(void) +{ +#if CONFIG_SF314_USE_GPU == 1 + if (gpio_get(DGPU_PWROK) && gpio_get(BID_GPU)) { + printk(BIOS_DEBUG, "dGPU present, enable power...\n"); + gpio_set(DGPU_HOLD_RSTN, 0); // Assert gpu reset + mdelay(2); + gpio_set(VGA_AON_PWR_EN, 1); // Assert power + mdelay(7); + gpio_set(DGPU_HOLD_RSTN, 1); // Deassert gpu reset + mdelay(30); + } else { + printk(BIOS_DEBUG, "dGPU not present, disable power...\n"); + gpio_set(DGPU_HOLD_RSTN, 0); // Assert gpu reset + gpio_set(VGA_AON_PWR_EN, 0); // Deassert GPU power + } +#else + printk(BIOS_INFO, "Disabling GPU: power off and hold in reset.\n"); + gpio_set(DGPU_HOLD_RSTN, 0); + gpio_set(VGA_AON_PWR_EN, 0); +#endif +} + + +void bootblock_mainboard_init(void) +{ + board_detect(); + dgpu_power_on(); +} + +void bootblock_mainboard_early_init(void) +{ + mainboard_config_stage_gpios(); +} diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb b/src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb index b42da49..cc87a65 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/skylake - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" + register "deep_s3_enable_ac" = "1" + register "deep_s3_enable_dc" = "1" register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" @@ -15,11 +15,15 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0681" - register "gen2_dec" = "0x000c1641" - - # Disable DPTF - register "dptf_enable" = "0" + # This assigns IO for the LPC see pch_lpc_add_io_resources in ./soc/intel/common/block/lpc/lpc.c + # bit 0 'enable' should be set to '1' + # first 16bits is base, bitwise AND with 0xfffc (ignore the enable bit) + # size is calcualted: size = (0x3 | ((gen_io_dec >> 16) & 0xfc)) + 1; + # examples + # register "gen3_dec" = "0x00040069" # 8Ch-8Fh; EC (sideband): Port 68h/6Ch + # register "gen4_dec" = "0x000c1201" # 90h-93h; EC (index): Port 1200h + # our ITE is at 0x25c, EC has a port at 1200h -- for some reason PMIC2 maps to 25c? + register "gen1_dec" = "0x0004025d" # FSP Configuration register "SataSalpSupport" = "0" @@ -30,15 +34,18 @@ register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + + # Enable S0ix + register "s0ix_enable" = "1" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Have not verified these thresholds # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -113,34 +120,71 @@ .dc_loadline = 310, }" - # Enable Root Ports 3, 5 and 9 - register "PcieRpEnable[2]" = "1" + # Enable Root Ports 1, 5, 9, and 11 + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[2]" = "1" + register "PcieRpMaxPayload[0]" = "RpMaxPayload_128" + register "PcieRpMaxPayload[4]" = "RpMaxPayload_128" + register "PcieRpMaxPayload[8]" = "RpMaxPayload_128" + register "PcieRpMaxPayload[10]" = "RpMaxPayload_128" + + register "PcieRpLtrEnable[0]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpLtrEnable[8]" = "1" + register "PcieRpLtrEnable[10]" = "0" - register "PcieRpHotPlug[4]" = "1" + register "PcieRpHotPlug[0]" = "0" + register "PcieRpHotPlug[4]" = "0" + register "PcieRpHotPlug[8]" = "0" + register "PcieRpHotPlug[10]" = "0" + + register "PcieRpAdvancedErrorReporting[0]" = "0" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpAdvancedErrorReporting[10]" = "1" + + register "PcieRpClkReqSupport[0]" = "0" + register "PcieRpClkReqSupport[4]" = "0" + register "PcieRpClkReqSupport[8]" = "0" + register "PcieRpClkReqSupport[10]" = "0" + + register "PcieRpClkReqNumber[0]" = "0" # Nvidia GPU + register "PcieRpClkReqNumber[4]" = "0" # NVME drive + register "PcieRpClkReqNumber[8]" = "0" # Wifi + register "PcieRpClkReqNumber[10]" = "0" # LPC + + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[4]" = "0" + register "PcieRpClkSrcNumber[8]" = "0" + register "PcieRpClkSrcNumber[10]" = "0" + + # ASPM L0s is broken/unsupported on Nvidia GPU bridge? (AER: corrected errors) + register "pcie_rp_aspm[0]" = "AspmL1" # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB3.0 S&C + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB3.0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3.0 Type C + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB3.0 Type C + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # USB20 (IO BD) + register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Bluetooth register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard - register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen + register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Card reader + register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Finger + register "usb2_ports[9]" = "USB2_PORT_FLEX(OC2)" # Touch + register "usb2_ports[10]" = "USB2_PORT_FLEX(OC2)" # ? + register "usb2_ports[11]" = "USB2_PORT_FLEX(OC2)" # ? - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3.0 S/C + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3.0 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3.0 Type C + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # USB3.0 Type C + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # ? + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # ? # PL1 override 25W # PL2 override 44W @@ -166,13 +210,14 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" + device cpu_cluster 0 on device lapic 0 on end end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # Thermal Subsystem + device pci 04.0 off end # Thermal Subsystem device pci 08.0 off end # Gaussian Mixture Model device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) @@ -181,9 +226,9 @@ device pci 15.0 on end # I2C Controller #0 device pci 15.1 on chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA7DB5"" register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D13_IRQ)" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end @@ -197,7 +242,7 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA - device pci 19.0 on end # I2C Controller #4 + device pci 19.0 off end # I2C Controller #4 device pci 19.1 off end # I2C Controller #5 device pci 19.2 off end # UART #2 device pci 1c.0 on end # PCI Express Port 1 @@ -210,38 +255,107 @@ device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 off end # Serial IO UART0 device pci 1e.6 off end # SDXC device pci 1f.0 on # LPC - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8987e - device pnp 6e.1 off end - device pnp 6e.2 off end - device pnp 6e.3 off end - device pnp 6e.4 off end - device pnp 6e.5 off end - device pnp 6e.6 off end - device pnp 6e.a off end - device pnp 6e.f off end - device pnp 6e.10 off end - device pnp 6e.11 off end - device pnp 6e.12 off end - device pnp 6e.13 off end - device pnp 6e.14 off end - device pnp 6e.17 off end - device pnp 6e.18 off end - device pnp 6e.19 off end - end #superio/ite/it8528e + chip superio/ite/it8987e # 'on' for everything returned from superiotool /w vendor ROM + # this is just copied from acer g43t + register "ec.smbus_en" = "1" + register "ec.smbus_24mhz" = "1" + register "TMPIN1.mode" = "THERMAL_RESISTOR" #memory + register "TMPIN2.mode" = "THERMAL_RESISTOR" #GPU + register "TMPIN3.mode" = "THERMAL_RESISTOR" #CPU + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "0" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "90" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "1" + register "FAN1.smart.smoothing" = "0" + register "FAN1.smart.pwm_start" = "30" + register "FAN1.smart.slope" = "0x0d" + register "FAN2.mode" = "FAN_MODE_OFF" + register "FAN3.mode" = "FAN_MODE_OFF" # Not connected + + register "ec.vin_mask" = "VIN_ALL" + + device pnp 25e.1 off end # UART 1 + device pnp 25e.2 off end # UART 2 + device pnp 25e.4 off end # System Wake Up Controller SWUC + device pnp 25e.5 on # Mouse + io 0x60 = 0x00 + io 0x61 = 0x00 + io 0x62 = 0x00 + io 0x63 = 0x00 + irq 0x70 = 0x0c + irq 0x71 = 0x01 + end + device pnp 25e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + irq 0x71 = 0x01 + end + device pnp 25e.a off end # IR + device pnp 25e.f on # Shared Memory / Flash Interface SMFI + io 0x60 = 0x00 + io 0x61 = 0x00 + io 0x62 = 0x00 + io 0x63 = 0x00 + irq 0x70 = 0x00 + irq 0x71 = 0x02 + irq 0xf0 = 0x00 + irq 0xf1 = 0x00 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + irq 0xf9 = 0x02 + irq 0xfa = 0x00 + irq 0xfb = 0x00 + irq 0xfc = 0x00 + end + device pnp 25e.10 off end # RTC like timer + device pnp 25e.11 on # Power Management Channel 1 PMC1 + io 0x60 = 0x0062 + io 0x62 = 0x0066 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + end + device pnp 25e.12 on # PMIC2 + io 0x60 = 0x025c + io 0x62 = 0x025d + io 0x64 = 0x00 + io 0x65 = 0x00 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + irq 0xf0 = 0x00 + end + device pnp 25e.13 off end # Slave SPI SSPI + device pnp 25e.14 off end # Platform EC Interface PECI + device pnp 25e.17 on # PMIC3 + io 0x60 = 0x0068 + io 0x62 = 0x006c + irq 0x70 = 0x01 + irq 0x71 = 0x01 + end + device pnp 25e.18 off end # PMIC4 + device pnp 25e.19 off end # PMIC5 + end end # LPC Bridge device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI + device pci 1f.5 off end # PCH SPI device pci 1f.6 off end # GbE end + chip drivers/crb + device mmio 0xfed40000 on end # this is the Intel PTT iTPM + end end diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/gma-mainboard.ads b/src/mainboard/acer/swift3-SF314-52G-55WQ/gma-mainboard.ads deleted file mode 100644 index a19ff06..0000000 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/gma-mainboard.ads +++ /dev/null @@ -1,18 +0,0 @@ --- SPDX-License-Identifier: GPL-2.0-or-later - -with HW.GFX.GMA; -with HW.GFX.GMA.Display_Probing; - -use HW.GFX.GMA; -use HW.GFX.GMA.Display_Probing; - -private package GMA.Mainboard is - - ports : constant Port_List := - (eDP, - DP1, - DP2, - HDMI1, - others => Disabled); - -end GMA.Mainboard; diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio.h b/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio.h index f0f93ce..f980a45 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio.h +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio.h @@ -5,6 +5,8 @@ #include <gpio.h> +void mainboard_config_stage_gpios(void); // gpio_early.c + /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { @@ -60,24 +62,6 @@ /* PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), */ _PAD_CFG_STRUCT(GPP_A7, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - /* GPP_A8 - CLKRUN# */ - /* DW0: 0x84000402, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) | (1 << 1) - IGNORED */ - /* PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), */ - _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), - - /* GPP_A9 - CLKOUT_LPC0 */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), */ - _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), - - /* GPP_A10 - CLKOUT_LPC1 */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), */ - _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), - /* GPP_A11 - GPIO */ /* DW0: 0x84000102, DW1: 0x00000000 */ /* DW0: (1 << 1) - IGNORED */ @@ -220,12 +204,6 @@ /* PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1), */ _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), - /* GPP_B13 - PLTRST# */ - /* DW0: 0x84000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), */ - _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), - /* GPP_B14 - SPKR */ /* DW0: 0x84000400, DW1: 0x00000000 */ /* DW0: PAD_TRIG(OFF) - IGNORED */ @@ -326,14 +304,6 @@ /* PAD_CFG_NF(GPP_C7, NONE, PLTRST, NF1), */ _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), - /* GPP_C8 - GPIO */ - /* DW0: 0x84000100, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), - - /* GPP_C9 - GPIO */ - /* DW0: 0x84000100, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), - /* GPP_C10 - GPIO */ /* DW0: 0x84000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), @@ -346,18 +316,6 @@ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C12, 1, PLTRST), - /* GPP_C13 - GPIO */ - /* DW0: 0x84000102, DW1: 0x00000000 */ - /* DW0: (1 << 1) - IGNORED */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_C13, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - - /* GPP_C14 - GPIO */ - /* DW0: 0x84000102, DW1: 0x00000000 */ - /* DW0: (1 << 1) - IGNORED */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_C14, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - /* GPP_C15 - GPIO */ /* DW0: 0x84000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI), @@ -400,10 +358,6 @@ /* PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, EDGE_SINGLE, NONE), */ _PAD_CFG_STRUCT(GPP_C22, PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - /* GPP_C23 - GPIO */ - /* DW0: 0x84000100, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), - /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -426,28 +380,10 @@ /* DW0: 0x84000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, PLTRST, OFF, ACPI), - /* GPP_D5 - GPIO */ - /* DW0: 0x84000100, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), - /* GPP_D6 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D6, 1, PLTRST), - /* GPP_D7 - GPIO */ - /* DW0: 0x84000102, DW1: 0x00000000 */ - /* DW0: (1 << 1) - IGNORED */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_D7, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - - /* GPP_D8 - GPIO */ - /* DW0: 0x84000100, DW1: 0x00000000 */ - PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), - - /* GPP_D9 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D9, 0, PLTRST), - /* GPP_D10 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D10, 1, PLTRST), @@ -456,22 +392,12 @@ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D11, 1, PLTRST), - /* GPP_D12 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D12, 0, PLTRST), - /* GPP_D13 - GPIO */ /* DW0: 0x80100102, DW1: 0x00000000 */ /* DW0: (1 << 1) - IGNORED */ /* PAD_CFG_GPI_APIC_HIGH(GPP_D13, NONE, PLTRST), */ _PAD_CFG_STRUCT(GPP_D13, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - /* GPP_D14 - GPIO */ - /* DW0: 0x84000102, DW1: 0x00000000 */ - /* DW0: (1 << 1) - IGNORED */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_D14, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), - /* GPP_D15 - GPIO */ /* DW0: 0x84000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI), @@ -664,18 +590,6 @@ /* PAD_CFG_NF(GPD3, UP_1K, DEEP, NF1), */ _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_1K)), - /* GPD4 - SLP_S3# */ - /* DW0: 0x44000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPD4, NONE, DEEP, NF1), */ - _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), - - /* GPD5 - SLP_S4# */ - /* DW0: 0x44000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPD5, NONE, DEEP, NF1), */ - _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), - /* GPD6 - GPIO */ /* DW0: 0x44000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, DEEP, OFF, ACPI), @@ -686,12 +600,6 @@ /* PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, DEEP, OFF, ACPI), */ _PAD_CFG_STRUCT(GPD7, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0), - /* GPD8 - SUSCLK */ - /* DW0: 0x44000400, DW1: 0x00000000 */ - /* DW0: PAD_TRIG(OFF) - IGNORED */ - /* PAD_CFG_NF(GPD8, NONE, DEEP, NF1), */ - _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), - /* GPD9 - GPIO */ /* DW0: 0x44000100, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, DEEP, OFF, ACPI), diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio_early.c b/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio_early.c new file mode 100644 index 0000000..6298030 --- /dev/null +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/gpio_early.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include "gpio.h" + +/* Early pad configuration + * Labeling from SF315 + */ +static const struct pad_config early_gpio_table[] = { + // GPIO = GPU_ID + // GPU_ID D8 (1 N17S, 0 N16S) + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI), + // GPIO <= DGPU_PWROK + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, PLTRST, OFF, ACPI), + // GPIO => DGPU_HOLD_RST# + PAD_CFG_GPO(GPP_D12, 0, PLTRST), + // GPIO => VGA_AON_PWR_EN + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + // No easy way to connect? + // PCH UART 0 DEBUG RX + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), + // PCH UART 0 DEBUG TX + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), + // CPU_ID D7 (0 U22, 1 U42) + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI), + // BID_GPU D14 + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI), + // PCB ID0 C13 + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI), + // PCB ID1 C14 + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI), + // PCB ID2 C23 + PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI), + // SUSMS#_EN B19 (also goes to SLP_S0# with optional resistor? + // SLP_S0# B12 + + // S3 sleep on PCH PM_SUSB# D4 to ITE + // S4 sleep on PCH PM_SUSC# D5 to ITE + + // HDCP ID A20 (0 Disable, 1 Enable) + // SOC ID A21 (1 BASE, 0 Premium) + + // DMIC ID (memory) E8 (1 4DMIC, 0 2DMIC) + + // GPU_OVERT# D4 + // SM_INTRUDER# (INTRUDER# on PCH) + +// Make sure SIO/EC is not in reset... + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x44000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPD4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x44000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPD5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), + + /* GPD8 - SUSCLK */ + /* DW0: 0x44000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPD8, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) - IGNORED */ + /* PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), + + +}; + +void mainboard_config_stage_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/mainboard.c b/src/mainboard/acer/swift3-SF314-52G-55WQ/mainboard.c new file mode 100644 index 0000000..70e383a --- /dev/null +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/mainboard.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/io.h> +#include <arch/cpuid.h> +#include <console/console.h> +#include <cpu/x86/msr_access.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <halt.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pmclib.h> +#include <intelblocks/pcr.h> +#include <rtc.h> +#include <soc/nhlt.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include "gpio.h" + +static void test_tpm(void) +{ + uint32_t tpm_resp=0; + uint8_t tpm_b=0; + uint32_t count=0x2EE; + + printk(BIOS_DEBUG, "Testing if TPM is working\n"); + do + { + tpm_resp = *(uint32_t*)(0xFED40000); + tpm_b=tpm_resp & 0x000000FF; + + if (tpm_b == 0xFF) + { + printk(BIOS_DEBUG, " 0xFED40000 got 0xFF, fail!\n"); + return; + } + if ( (tpm_b & 0x80) == 0x80) + { + printk(BIOS_DEBUG, " 0xFED40000 got bit 7 set, succeed, = %02X (expect 0x83)\n", tpm_b); + return; + } + count--; + } while (count != 0); + printk(BIOS_DEBUG, " timeout... fail\n"); +} + +/* + +// From volume top file entry8 (deep in function calls) +// Set up MTRR and some undocumented MSRs +static void vtf_entry8(void) +{ + uint32_t tmp8=0; + + printk(BIOS_DEBUG, "VTF Memory space Configuration\n"); + + // possibly memory mapping something? + printk(BIOS_DEBUG, "... set memory areas\n"); + *(uint32_t *)(0xFEE00300) = 0x000c4500; + + // 'setGlobals' + *(uint32_t *)(0xE00F9010) = 0xfd000000; + *(uint32_t *)(0xE00F9004) |= 2; + *(uint32_t *)(0xE00FC064) = 0x0a0a0000; + *(uint32_t *)(0xE00FC020) = 0x0000efa0; + *(uint32_t *)(0xE00FC004) |= 1; + tmp8 = 0x000000FF & *(uint32_t *)(0xE00FC040); + tmp8 |= 0xE00FC001; + *(uint32_t *)(0xE00FC040) = tmp8; +} +*/ + +static void vendor_config(void) +{ + uint32_t tmp=0; +// uint8_t tmpb=0; + uint8_t tmpb2=0; + uint16_t tmps=0; + +// struct cpuid_result cpuidResult; // has eax,ebx,ecx,edx +// msr_t msrValue; // either lo,hi or raw (64 bit) +// uint8_t eaxByte=0; +// uint32_t tmp3=0; +// uint32_t tmp4=0; + uint32_t tmp5=0; + +/* + // starting from Volume Top File initialization + // removing things found to be unnecessary + outl(0x80000060, 0x0cf8); + outl(0xE0000001, 0x0cfc); + *(uint32_t*)(0xE0000048) = 0xFED10001; + *(uint32_t*)(0xE000004c) = 0x0; + *(uint32_t*)(0xE00F9060) = 0x80; + *(uint32_t*)(0xFED00108) = 0x0; + *(uint32_t*)(0xFED0010c) = 0x0; + + outl(0x800000dc, 0x0cf8); + tmp = inl(0x0cfc); + printk(BIOS_DEBUG, "Read from 0x800000dc = 0x%08X\n", tmp); + if ((uint8_t)(tmp >> 0x18) == 0xFF) { + printk(BIOS_DEBUG, " ... would have set 0xcf9 to 6 (reset)\n"); + } + + // from VTF - probably setting EC clock + outb(0xFB, 0x0072); + tmpb = inb(0x0073); + outb(tmpb, 0x00ED); // one byte below ITE - setting time? + outb(0xFC, 0x0072); + outb(tmpb, 0x0073); + outb(tmpb, 0x00ED); + + outb(0xFA, 0x0072); + tmpb = inb(0x0073); + outb(tmpb, 0x00ED); + outb(0xFB, 0x0072); + outb(tmpb, 0x0073); + outb(tmpb, 0x00ED); + + outb(0xF9, 0x0072); + tmpb = inb(0x0073); + outb(tmpb, 0x00ED); + outb(0xFA, 0x0072); + outb(tmpb, 0x0073); + outb(tmpb, 0x00ED); + + outb(0xF8, 0x0072); + tmpb = inb(0x0073); + outb(tmpb, 0x00ED); + outb(0xF9, 0x0072); + outb(tmpb, 0x0073); + outb(tmpb, 0x00ED); + + outb(0xF7, 0x0072); + tmpb = inb(0x0073); + outb(tmpb, 0x00ED); + outb(0xF8, 0x0072); + outb(tmpb, 0x0073); + outb(tmpb, 0x00ED); + + outb(0xF7, 0x0072); + outb(0x00, 0x0073); + outb(0x2D, 0x0072); + tmpb = inb(0x0073); + printk(BIOS_DEBUG, "Read from RTC 0x%02X\n", tmpb); + if (tmpb == 0xF1) + { + printk(BIOS_DEBUG, " ... would have written to reset and 0x8000faac then waited for reset\n"); + } + + outl(0x8000FAAC, 0x0CF8); + tmp = inl(0x0CFC); + printk(BIOS_DEBUG, "Read from 0x8000FAAC = 0x%08X\n", tmp); + outl(tmp & 0xffefffff, 0x0CFC); + printk(BIOS_DEBUG, "Write to 0x8000FAAC = 0x%08X\n", tmp & 0xffefffff); + outl(0x800000DC, 0x0CF8); + tmp = inl(0x0CFC); + printk(BIOS_DEBUG, "Read from 0x800000dc = 0x%08X\n", tmp); + if ((uint8_t)(tmp >> 0x18) == 0xFF) { + printk(BIOS_DEBUG, " ... would have set 0xcf9 to 6 (reset)\n"); + } +*/ + + // SMBus stuff from VTF + // Appears this is how the Intel Platform Trust Technology TPM is enabled + printk(BIOS_DEBUG, "Begin SMBus transactions - enable iTPM\n"); + tmp = inl(0xcf8); + + outl(0x8000fa44, 0xcf8); + tmpb2 = inb(0xcfc); + printk(BIOS_DEBUG, " 0x8000fa44 = 0x%02X\n", tmpb2); + // test if MSB is 1 + if (tmpb2 & 0x80) + { + printk(BIOS_DEBUG, " MSB set, set 0x8000fa40 = 0x1800\n"); + outl(0x8000fa40,0xcf8); + outw(0x1800,0xcfc); + + outl(0x8000fa44, 0xcf8); + tmpb2 = inb(0xcfc); + printk(BIOS_DEBUG, " read 0x8000fa44 = 0x%02X (expect 0x80)\n", tmpb2); + tmpb2 |= 0x80; + outb(tmpb2,0xcfc); + printk(BIOS_DEBUG, " wrote 0x8000fa44 = 0x%02X (expect 0x80)\n", tmpb2); + } + + outl(0x8000fa40,0xcf8); + tmps = inw(0xcfc); + printk(BIOS_DEBUG, " read 0x8000fa40 = 0x%04X\n", tmps); + + tmps=(tmps & 0xFFFC) + 8; + tmp5 = inl(tmps); + printk(BIOS_DEBUG, " read in, then check in loop 0x%04X = 0x%08X\n", tmps, tmp5); + + for (uint32_t i=0; i<0x2EE; i++) + { + uint32_t t=inl(tmps); + if ( ((tmp5 + 0xdfb - t) & 0x00800000) == 0 ) + { + printk(BIOS_DEBUG, " 0x%04X = 0x%08X at index %d - iTPM probably enabled\n", tmps, t, i); + break; + } + } + printk(BIOS_DEBUG, "Done trying to enable iTPM...\n"); + + outl(0xcf8,tmp); + tmp5=0; + +// vtf_entry8(); + + test_tpm(); +} + +static void mainboard_init(void *chip_info) +{ + /* Program the same 64K range of EC memory as vendor FW */ + lpc_open_mmio_window(0xFEFF0000, 0x10000); + vendor_config(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + diff --git a/src/mainboard/acer/swift3-SF314-52G-55WQ/ramstage.c b/src/mainboard/acer/swift3-SF314-52G-55WQ/ramstage.c index 7c05c6b..e769f54 100644 --- a/src/mainboard/acer/swift3-SF314-52G-55WQ/ramstage.c +++ b/src/mainboard/acer/swift3-SF314-52G-55WQ/ramstage.c @@ -3,6 +3,7 @@ #include <soc/ramstage.h> #include "gpio.h" + void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 8ff122b..3cb3b71 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -18,3 +18,4 @@ subdirs-y += it8772f subdirs-y += it8783ef subdirs-y += it8786e +subdirs-y += it8987e diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..dba9879 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..90bdfb5 --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/chip.h b/src/superio/ite/it8987e/chip.h new file mode 100644 index 0000000..98884e3 --- /dev/null +++ b/src/superio/ite/it8987e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8987E_CHIP_H +#define SUPERIO_ITE_IT8987E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8987e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8987E_CHIP_H */ diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..7e9f7eb --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SP1 0x01 /* Com1 */ +#define IT8987E_SP2 0x02 /* Com2 */ +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..6a047e0 --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> +#include <pc80/keyboard.h> +#include <console/console.h> + +#include "it8987e.h" +#include "chip.h" + + +static void it8987e_init(struct device *dev) +{ + + printk(BIOS_INFO, "IT8987E: init\n"); + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8987E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + printk(BIOS_INFO, "IT8987E: unknown default %d\n", dev->path.pnp.device); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + const struct superio_ite_it8987e_config *conf; + + printk(BIOS_INFO, "IT8987E: enable\n"); + + conf = dev->chip_info; + if (!conf) + { + printk(BIOS_ERR, "IT8987E: unable to init, bad conf/res\n"); + } else { + printk(BIOS_INFO, "IT8987E: init ITE EC\n"); + ite_ec_init(0x25e, &conf->ec); + } + + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Update opensbi submodule to upstream master
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72793 ) Change subject: Update opensbi submodule to upstream master ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169888): https://review.coreboot.org/c/coreboot/+/72793/comment/37a98952_d82bb848 PS1, Line 12: to commit id c8ea836: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65cdd60a39665ec490474f400eddf318aa139a72 Gerrit-Change-Number: 72793 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update opensbi submodule to upstream master
by Elyes Haouas (Code Review) 04 Feb '23

04 Feb '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72793 ) Change subject: Update opensbi submodule to upstream master ...................................................................... Update opensbi submodule to upstream master Updating from commit id 5019fd1: 2022-09-01 16:53:28 +0530 - (include: sbi: Reduce includes in sbi_pmu.h) to commit id c8ea836: 2023-01-27 08:39:49 +0530 - (firmware: Fix fw_rw_offset computation in fw_base.S) This brings in 116 new commits. Change-Id: I65cdd60a39665ec490474f400eddf318aa139a72 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/opensbi 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/72793/1 diff --git a/3rdparty/opensbi b/3rdparty/opensbi index 5019fd1..c8ea836 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit 5019fd124b4c46e1581129c5154fc2cdd3b777ed +Subproject commit c8ea836ee33eb778f48f780412e147386dac5301 -- To view, visit https://review.coreboot.org/c/coreboot/+/72793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65cdd60a39665ec490474f400eddf318aa139a72 Gerrit-Change-Number: 72793 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72792 ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169887): https://review.coreboot.org/c/coreboot/+/72792/comment/f4311159_a2fdfdba PS1, Line 9: Updating from commit id 9881bb93a: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169887): https://review.coreboot.org/c/coreboot/+/72792/comment/65be89f4_0c92f0db PS1, Line 12: to commit id 6264643a0: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4d8d5f5144f50a097c6118467e141c5fe78e812 Gerrit-Change-Number: 72792 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Elyes Haouas (Code Review) 04 Feb '23

04 Feb '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72792 ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 9881bb93a: 2022-11-21 19:12:00 +0100 - (Merge "docs(spm): update threat model" into integration) to commit id 6264643a0: 2023-02-03 17:04:42 +0100 - (Merge "refactor(tc): update total compute gpu device node" into integration) This brings in 335 new commits. Change-Id: If4d8d5f5144f50a097c6118467e141c5fe78e812 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/arm-trusted-firmware 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/72792/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 9881bb9..6264643 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 9881bb93a3bc0a3ea37e9f093e09ab4b360a9e48 +Subproject commit 6264643a0711faef346cbbb6e3d928a198aeaf31 -- To view, visit https://review.coreboot.org/c/coreboot/+/72792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4d8d5f5144f50a097c6118467e141c5fe78e812 Gerrit-Change-Number: 72792 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Update cmocka submodule to upstream master
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72791 ) Change subject: Update cmocka submodule to upstream master ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169886): https://review.coreboot.org/c/coreboot/+/72791/comment/281a8dc0_10f4a3bd PS1, Line 9: Updating from commit id 8931845: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169886): https://review.coreboot.org/c/coreboot/+/72791/comment/dc447d12_8efb34b8 PS1, Line 12: to commit id a79b97c: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a53ac7685a8b7e2f57613a9909dfc0a8c057c55 Gerrit-Change-Number: 72791 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:49:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update cmocka submodule to upstream master
by Elyes Haouas (Code Review) 04 Feb '23

04 Feb '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72791 ) Change subject: Update cmocka submodule to upstream master ...................................................................... Update cmocka submodule to upstream master Updating from commit id 8931845: 2020-10-12 08:24:45 +0200 - (cmocka: Fix cm_print_error() in check_for_leftover_values(_list)) to commit id a79b97c: 2023-02-03 12:47:42 +0100 - (coverity: Add missing functions to model file) This brings in 156 new commits. Change-Id: I6a53ac7685a8b7e2f57613a9909dfc0a8c057c55 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/cmocka 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/72791/1 diff --git a/3rdparty/cmocka b/3rdparty/cmocka index 8931845..a79b97c 160000 --- a/3rdparty/cmocka +++ b/3rdparty/cmocka @@ -1 +1 @@ -Subproject commit 8931845c35e78b5123d73430b071affd537d5935 +Subproject commit a79b97cb9235175b27a82d48702b083f54c7400e -- To view, visit https://review.coreboot.org/c/coreboot/+/72791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a53ac7685a8b7e2f57613a9909dfc0a8c057c55 Gerrit-Change-Number: 72791 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Update intel-sec-tools submodule to upstream master
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72790 ) Change subject: Update intel-sec-tools submodule to upstream master ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169885): https://review.coreboot.org/c/coreboot/+/72790/comment/79646067_073b94cf PS1, Line 9: Updating from commit id 0031ac7: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169885): https://review.coreboot.org/c/coreboot/+/72790/comment/8270b6b5_d8b64949 PS1, Line 12: to commit id b58fd49: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8817e18ee943db0d4be4d6de3c0142faee9dd201 Gerrit-Change-Number: 72790 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Update intel-sec-tools submodule to upstream master
by Elyes Haouas (Code Review) 04 Feb '23

04 Feb '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72790 ) Change subject: Update intel-sec-tools submodule to upstream master ...................................................................... Update intel-sec-tools submodule to upstream master Updating from commit id 0031ac7: 2021-06-22 14:22:03 +0200 - (Merge pull request #245 from 9elements/meparser) to commit id b58fd49: 2023-02-01 12:19:53 +0100 - (Merge pull request #346 from 9elements/bootguard-1.0) This brings in 216 new commits. Change-Id: I8817e18ee943db0d4be4d6de3c0142faee9dd201 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/intel-sec-tools 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/72790/1 diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools index 0031ac7..b58fd49 160000 --- a/3rdparty/intel-sec-tools +++ b/3rdparty/intel-sec-tools @@ -1 +1 @@ -Subproject commit 0031ac73447baeb197fb2d80e5fba2470716e76d +Subproject commit b58fd497cabf496ecfc4ec61e5e54144da258c09 -- To view, visit https://review.coreboot.org/c/coreboot/+/72790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8817e18ee943db0d4be4d6de3c0142faee9dd201 Gerrit-Change-Number: 72790 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/kano: Update ELAN TS delay time to 150ms
by Paz Zcharya (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Ren Kuo, Nick Vaccaro. Paz Zcharya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72784 ) Change subject: mb/google/brya/var/kano: Update ELAN TS delay time to 150ms ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Please also update the datasheet in AVL and then mark this as resolved -- To view, visit https://review.coreboot.org/c/coreboot/+/72784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a Gerrit-Change-Number: 72784 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023