coreboot-gerrit February 2023

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[M] Change in coreboot[master]: tree: drop repeated words
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Erik van den Bogaert, Martin L Roth, Frans Hendriks, Patrick Rudolph, Jakub Czapiga, Christian Walter, Angel Pons, Julius Werner, Lean Sheng Tan, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72795 ) Change subject: tree: drop repeated words ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169906): https://review.coreboot.org/c/coreboot/+/72795/comment/e79916fc_5cbad8ec PS1, Line 8: Non-standard signature: Found-by: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169906): https://review.coreboot.org/c/coreboot/+/72795/comment/9c87fe2a_20f5d2a8 PS1, Line 8: Unrecognized email address: 'linter' -- To view, visit https://review.coreboot.org/c/coreboot/+/72795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Gerrit-Change-Number: 72795 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Sat, 04 Feb 2023 19:02:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: tree: drop repeated words
by Alexander Goncharov (Code Review) 04 Feb '23

04 Feb '23

Alexander Goncharov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72795 ) Change subject: tree: drop repeated words ...................................................................... tree: drop repeated words Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> --- M src/Kconfig M src/arch/arm/include/armv7/arch/cache.h M src/cpu/x86/Kconfig M src/include/device_tree.h M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/google/dedede/smihandler.c M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/prodrive/hermes/eeprom.c M src/soc/intel/common/block/cse/cse_lite.c M src/southbridge/amd/pi/hudson/lpc.c M src/vendorcode/eltan/security/mboot/mboot.c M tests/lib/rtc-test.c M util/sconfig/main.c 32 files changed, 65 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/72795/1 diff --git a/src/Kconfig b/src/Kconfig index 8246a17..16f7881 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -562,7 +562,7 @@ # Default value set at the end of the file help This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start + end of the ROM (passed through cbfstool -o) on x86 and at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index e332c31..f10b8a0 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -192,7 +192,7 @@ return val; } -/* read cache size ID register register (CCSIDR) */ +/* read cache size ID register (CCSIDR) */ static inline uint32_t read_ccsidr(void) { uint32_t val = 0; diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 7e58175..1a7d8c6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -179,7 +179,7 @@ bool default n help - This option limits the number of SIPI signals sent during during the + This option limits the number of SIPI signals sent during the common AP setup. Intel documentation specifies an INIT SIPI SIPI sequence, however this doesn't work on some AMD and Intel platforms. These newer AMD and Intel platforms don't need the 10ms wait between @@ -197,7 +197,7 @@ default n help This option allows a platform to reserve 2 MTRRs for the OS usage. - The Intel SDM documents that the the first 6 MTRRs are intended for + The Intel SDM documents that the first 6 MTRRs are intended for the system BIOS and the last 2 are to be reserved for OS usage. However, modern OSes use PAT to control cacheability instead of using MTRRs. diff --git a/src/include/device_tree.h b/src/include/device_tree.h index ae30c59..02fcaa7 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -91,10 +91,10 @@ * which were consumed reading the requested value. */ -/* Read the property, if any, at offset offset. */ +/* Read the property at offset, if any exists. */ int fdt_next_property(const void *blob, uint32_t offset, struct fdt_property *prop); -/* Read the name of the node, if any, at offset offset. */ +/* Read the name of the node at offset, if any exists. */ int fdt_node_name(const void *blob, uint32_t offset, const char **name); void fdt_print_node(const void *blob, uint32_t offset); diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 4b1b9af..c408d5a 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -40,7 +40,7 @@ device ref ehci2 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c subsystemid 0x8086 0x7270 end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x8086 0x7270 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 163cdb3..b9f3f4d 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -57,7 +57,7 @@ device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device ref hda on # High Definition Audio Audio controller + device ref hda on # High Definition Audio controller subsystemid 0x1849 0x8892 end device ref pcie_rp1 on # PCIe Port #1 diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb index 89ef419..cb30fc3 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/overridetree.cb @@ -5,7 +5,7 @@ subsystemid 0x1043 0x844d inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" - device pci 1b.0 on # High Definition Audio Audio controller + device pci 1b.0 on # High Definition Audio controller subsystemid 0x1043 0x8445 end device pci 1c.0 off end # PCIe Port #1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 98fcb62..bacdae8 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -11,7 +11,7 @@ { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to + * setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 33c6b2e..7fc4c13 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -80,7 +80,7 @@ } /* - * Note that we are assuming that the Status Register protect bits are + * Note that we are assuming that the Status Register protect bits * are located at this index and that 1 means hardware protected. This * should be the case for these boards. */ diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 95d5368..74c601a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -168,7 +168,7 @@ register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 + # RP 3 uses CLK SRC 0 register "PcieRpClkSrcNumber[2]" = "0" # Enable Root port 4(x1) for WLAN. @@ -181,7 +181,7 @@ register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 + # RP 4 uses CLK SRC 5 register "PcieRpClkSrcNumber[3]" = "5" # Enable Root port 5(x4) for NVMe. @@ -207,7 +207,7 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # Enable Root port 11 for BtoB. @@ -220,7 +220,7 @@ register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 + # RP 11 uses CLK SRC 2 register "PcieRpClkSrcNumber[10]" = "2" # Enable Root port 12 for BtoB. @@ -233,7 +233,7 @@ register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 + # RP 12 uses CLK SRC 2 register "PcieRpClkSrcNumber[11]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 3ca1648..07ed7bc 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -10,7 +10,7 @@ register "PcieRpAdvancedErrorReporting[6]" = "1" # RP 7, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" - # RP 7 uses uses CLK SRC 4 + # RP 7 uses CLK SRC 4 register "PcieRpClkSrcNumber[6]" = "4" # Enable Root port 8(x1) for TPU0 @@ -23,7 +23,7 @@ register "PcieRpAdvancedErrorReporting[7]" = "1" # RP 8, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[7]" = "1" - # RP 8 uses uses CLK SRC 2 + # RP 8 uses CLK SRC 2 register "PcieRpClkSrcNumber[7]" = "2" # Enable Root port 9(x4) for i350 LAN @@ -34,7 +34,7 @@ register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 + # RP 9 uses CLK SRC 2 register "PcieRpClkSrcNumber[8]" = "2" # These are part of Root port 9(x4) diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d963d9d..2e3953a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -130,7 +130,7 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 25f75b8f..07363fd 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -135,7 +135,7 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 66c07db..8be97c8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -133,7 +133,7 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7cc3eb3..a20c197 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -130,7 +130,7 @@ register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" - # RP 1 uses uses CLK SRC 1 + # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 13398d0..a18ec3c 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -30,7 +30,7 @@ device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 265b0ef..71b1865 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -34,7 +34,7 @@ device ref me_kt on end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 off end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index df35e8a..d512814 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -10,37 +10,37 @@ register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 - # RP7, uses uses CLK SRC 2 + # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - # RP8, uses uses CLK SRC 3 + # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - # RP9, uses uses CLK SRC 4 + # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 - # RP14, uses uses CLK SRC 5 + # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 - # RP17, uses uses CLK SRC 7 + # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" # USB related diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b1d2917..2c93a38 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -41,21 +41,21 @@ register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" - # RP1, uses uses CLK SRC 2 + # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" - # RP5, uses uses CLK SRC 3 + # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" - # RP6, uses uses CLK SRC 1 + # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" # PCIE Port 7 Disabled @@ -64,14 +64,14 @@ register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" - # RP9, uses uses CLK SRC 5 + # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" - # RP10, uses uses CLK SRC 4 + # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" # USB 2.0 Enable all ports diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 5c5382f..23cbf96 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -101,15 +101,15 @@ register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkReqNumber[8]" = "1" - # RP 3 uses uses CLK SRC 5# + # RP 3 uses CLK SRC 5# register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses uses CLK SRC 2# + # RP 4 uses CLK SRC 2# register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses uses CLK SRC 3# + # RP 5 uses CLK SRC 3# register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses uses CLK SRC 4# + # RP 6 uses CLK SRC 4# register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses uses CLK SRC 1# + # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" # USB 2.0 Enable all ports diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index fc00734..fb05027 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -41,7 +41,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # High Definition Audio controller device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader device pci 1c.1 on # PCIe Port #2, WLAN smbios_slot_desc "0x14" "1" "M.2 2230" "8" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ca16094..a012741 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -41,7 +41,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 on end # PCIe Port #3 diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f105424..eae9696 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -45,7 +45,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 device ref pcie_rp3 off end # PCIe Port #3 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index bcffdaa..7e54383 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -43,7 +43,7 @@ device ref me_kt off end # Management Engine KT device ref gbe on end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 0acf98bb..beb2609 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -55,7 +55,7 @@ device ref me_kt off end # Management Engine KT device ref gbe off end # Intel Gigabit Ethernet device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio Audio controller + device ref hda on end # High Definition Audio controller device ref pcie_rp1 on end # PCIe Port #1 device ref pcie_rp2 on end # PCIe Port #2 (WLAN card) device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index c90c69c..86e86f5 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -96,7 +96,7 @@ }" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" - # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) + # Enable CPU PCIE RP 1, 2, 3 using free running CLK (0x80) # Clock source is shared hence marked as free running. register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index c4a2695..c0e9cb6 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -16,7 +16,7 @@ /* * Check Signature in EEPROM (M24C32-FMN6TP) - * If signature is there we assume that that the content is valid + * If signature is there we assume that the content is valid */ int check_signature(const size_t offset, const uint64_t signature) { diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9866d55..4a624e6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1111,7 +1111,7 @@ /* * If system is in recovery mode, CSE Lite update has to be skipped but CSE - * sub-partitions like NPHY and IOM have to to be updated. If CSE sub-parition update + * sub-partitions like NPHY and IOM have to be updated. If CSE sub-parition update * fails during recovery, just continue to boot. */ if (CONFIG(SOC_INTEL_CSE_SUB_PART_UPDATE) && vboot_recovery_mode_enabled()) { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 7abb5bf..0a4e038 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -47,8 +47,8 @@ /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can + byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is running + on LPC, it holds PCI grant, so no LPC slave cycle can interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index d7817bd..e8a2f80 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -342,7 +342,7 @@ * * mb_measure_log_start * - * performs the measurements defined by the the board routines. + * performs the measurements defined by the board routines. * * The logging is defined by the mb_log_list structure * diff --git a/tests/lib/rtc-test.c b/tests/lib/rtc-test.c index c3c7403..a205692 100644 --- a/tests/lib/rtc-test.c +++ b/tests/lib/rtc-test.c @@ -109,7 +109,7 @@ tm.mon = 2; tm.mday = 29; assert_int_equal(1078062333, rtc_mktime(&tm)); - /* Ensure that February 29 and March 1 have different different and correct values + /* Ensure that February 29 and March 1 have different and correct values in leap year */ tm = (struct rtc_time){ .year = 2004, .mon = 3, .mday = 1, .hour = 7, .min = 7, .sec = 17, diff --git a/util/sconfig/main.c b/util/sconfig/main.c index a532dd4..6618a45 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -317,7 +317,7 @@ sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { /* root_complex gets away without a separate directory, but - * exists on on pretty much all AMD chipsets. + * exists on pretty much all AMD chipsets. */ if (!strstr(path, "/root_complex")) { fprintf(stderr, "ERROR: Chip component %s does not exist.\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/72795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Gerrit-Change-Number: 72795 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by Nicholas Chin (Code Review) 04 Feb '23

04 Feb '23

1 0

[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by Nicholas Chin (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: char, Felix Held. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Patch Set 1: (9 comments) Commit Message: PS1: Missing Signed-off-by line Patchset: PS1: I would split the ITE8987e stuff to a separate commit File src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb: https://review.coreboot.org/c/coreboot/+/72788/comment/832ca50e_4c866318 PS1, Line 39: # Enable S0ix : register "s0ix_enable" = "1" : register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h : register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h : register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h : register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h Please change to tabs to be consistent with the rest of the file (seems like tabs are preferred anyway) https://review.coreboot.org/c/coreboot/+/72788/comment/657d4d63_7850e3e5 PS1, Line 129: register "PcieRpMaxPayload[0]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[4]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[8]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[10]" = "RpMaxPayload_128" Tabs https://review.coreboot.org/c/coreboot/+/72788/comment/9812742e_ace6b9e8 PS1, Line 149: register "PcieRpClkReqSupport[0]" = "0" : register "PcieRpClkReqSupport[4]" = "0" : register "PcieRpClkReqSupport[8]" = "0" : register "PcieRpClkReqSupport[10]" = "0" : : register "PcieRpClkReqNumber[0]" = "0" # Nvidia GPU : register "PcieRpClkReqNumber[4]" = "0" # NVME drive : register "PcieRpClkReqNumber[8]" = "0" # Wifi : register "PcieRpClkReqNumber[10]" = "0" # LPC Tabs https://review.coreboot.org/c/coreboot/+/72788/comment/cc8dfe48_ec8b0d73 PS1, Line 215: device lapic 0 on end As of commit 69cd729c0c (mb/*: Remove lapic from devicetree) this line should be removed https://review.coreboot.org/c/coreboot/+/72788/comment/7ce8aadf_3b882399 PS1, Line 263: chip superio/ite/it8987e # 'on' for everything returned from superiotool /w vendor ROM Many lines in this chip instance have tab/space issues https://review.coreboot.org/c/coreboot/+/72788/comment/5fbbfa4c_7372b17e PS1, Line 358: chip drivers/crb : device mmio 0xfed40000 on end # this is the Intel PTT iTPM : end Tabs https://review.coreboot.org/c/coreboot/+/72788/comment/9eb3393f_20ac9c6c PS1, Line 360: end nit: Fix alignment with corresponding chip line in line 358 -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: char Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Feb 2023 18:39:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES
by Harsha B R (Code Review) 04 Feb '23

04 Feb '23

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72813 ) Change subject: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES ...................................................................... mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for mtlrvp_p which helps in mode switch using dut-control power_state:rec chroot command. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode (mode switch) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/72813/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 945aa2e..70285d6 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -89,6 +89,7 @@ config VBOOT select VBOOT_LID_SWITCH + select EC_GOOGLE_CHROMEEC_SWITCHES config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/72813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Gerrit-Change-Number: 72813 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: Update libgfxinit submodule to upstream master
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72794 ) Change subject: Update libgfxinit submodule to upstream master ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169891): https://review.coreboot.org/c/coreboot/+/72794/comment/e8bdb69f_6c905d2a PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ea3e7cc7fbf0d848e47e52685355b1c3fabf Gerrit-Change-Number: 72794 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Feb 2023 15:18:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Update libgfxinit submodule to upstream master
by Elyes Haouas (Code Review) 04 Feb '23

04 Feb '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72794 ) Change subject: Update libgfxinit submodule to upstream master ...................................................................... Update libgfxinit submodule to upstream master Updating from commit 066e52ee (Fix "unnecessary with of ancestor [-gnatwr]") to commit 793f4f8 (gma: Correct Global annotation for Initialize()) This brings in 7 new commits. Change-Id: I0713ea3e7cc7fbf0d848e47e52685355b1c3fabf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/libgfxinit 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/72794/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 066e52e..793f4f8 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 066e52eeaa329d782ccee96265a6a351fc395bf1 +Subproject commit 793f4f83f128b5ed2afe9bbcc1299c625bad9a8c -- To view, visit https://review.coreboot.org/c/coreboot/+/72794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0713ea3e7cc7fbf0d848e47e52685355b1c3fabf Gerrit-Change-Number: 72794 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI support for Type-C ports
by Harsha B R (Code Review) 04 Feb '23

04 Feb '23

Harsha B R has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72789 ) Change subject: mb/intel/mtlrvp: Enable ACPI support for Type-C ports ...................................................................... mb/intel/mtlrvp: Enable ACPI support for Type-C ports This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the correspodning entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/dsdt.asl M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/72789/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Gerrit-Change-Number: 72789 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI support for Type-C ports
by Harsha B R (Code Review) 04 Feb '23

04 Feb '23

Harsha B R has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72789 ) Change subject: mb/intel/mtlrvp: Enable ACPI support for Type-C ports ...................................................................... mb/intel/mtlrvp: Enable ACPI support for Type-C ports This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the correspodning entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/dsdt.asl M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/72789/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 945aa2e..3468ac9 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -13,6 +13,7 @@ config BOARD_INTEL_MTLRVP_P_EXT_EC select BOARD_INTEL_MTLRVP_COMMON + select DRIVERS_INTEL_PMC if BOARD_INTEL_MTLRVP_COMMON diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl index d253617..a367bbb 100644 --- a/src/mainboard/intel/mtlrvp/dsdt.asl +++ b/src/mainboard/intel/mtlrvp/dsdt.asl @@ -22,6 +22,7 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> } } diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb index b08d7ca..26b833f 100644 --- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -3,8 +3,36 @@ device domain 0 on device ref soc_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port4 as usb2_port + use tcss_usb3_port4 as usb3_port + device generic 3 alias conn3 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Gerrit-Change-Number: 72789 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Patch Set 1: (347 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/b3ffb421_6583506a PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) File src/mainboard/acer/swift3-SF314-52G-55WQ/acpi/battery.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/361073d3_08ac1101 PS1, Line 13: Zero, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2e5a0dd3_a9303996 PS1, Line 14: 0xFFFFFFFF, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/58e302c0_6e5e71e8 PS1, Line 15: 0xFFFFFFFF, trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): 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jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d9d09a8d_19661fe4 PS1, Line 49: switch(combined) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/477e973a_0c543963 PS1, Line 49: switch(combined) space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/fba265d9_4df22ae6 PS1, Line 79: gpio_set(VGA_AON_PWR_EN, 0); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/70a7910d_098556fb PS1, Line 79: gpio_set(VGA_AON_PWR_EN, 0); please, no spaces at the start of a line File src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/9cd1ed77_c4e605fd PS1, Line 21: # size is calcualted: size = (0x3 | ((gen_io_dec >> 16) & 0xfc)) + 1; 'calcualted' may be misspelled - perhaps 'calculated'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ac626025_2f5e804b PS1, Line 349: end trailing whitespace File src/mainboard/acer/swift3-SF314-52G-55WQ/gpio_early.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/6b585dec_eff74ae7 PS1, Line 52: /* DW0: 0x84000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/064b402f_78bb5a0c PS1, Line 53: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/687cfc78_bdedce2a PS1, Line 54: /* PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7d59f9dc_1dd9500c PS1, Line 55: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/5a2dc808_09f4c5d9 PS1, Line 55: _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d86d6643_37e76083 PS1, Line 57: /* GPD4 - SLP_S3# */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4e0df6dc_c63fd975 PS1, Line 58: /* DW0: 0x44000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/aaa00b26_a5fb4085 PS1, Line 59: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/3629b081_feaaff00 PS1, Line 60: /* PAD_CFG_NF(GPD4, NONE, DEEP, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/36eb686b_0a6f530e PS1, Line 61: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/0ad62c33_b5bea28c PS1, Line 61: _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7bde1db4_32f8c8ce PS1, Line 63: /* GPD5 - SLP_S4# */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/c2dc802c_c990ddfc PS1, Line 64: /* DW0: 0x44000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f18143db_9d44e862 PS1, Line 65: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ef5b9b13_5e53a8c8 PS1, Line 66: /* PAD_CFG_NF(GPD5, NONE, DEEP, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/cf2e08c4_1a469392 PS1, Line 67: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7cf02067_a2087aac PS1, Line 67: _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ae27dd48_af47741e PS1, Line 69: /* GPD8 - SUSCLK */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/b345c40b_9cec9888 PS1, Line 70: /* DW0: 0x44000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/e1e5845e_532a3f2a PS1, Line 71: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/36eeed97_25d76d4f PS1, Line 72: /* PAD_CFG_NF(GPD8, NONE, DEEP, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/67562fae_2d276cd3 PS1, Line 73: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/beee27d9_a6ac0fd1 PS1, Line 73: _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/dcee1e6e_4fa16c47 PS1, Line 75: /* GPP_A8 - CLKRUN# */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/137f4224_88ac6187 PS1, Line 76: /* DW0: 0x84000402, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/6948ecb9_97123bde PS1, Line 77: /* DW0: PAD_TRIG(OFF) | (1 << 1) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/0dc6fed2_d0ed5589 PS1, Line 78: /* PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/439cca9e_4d0e5375 PS1, Line 79: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/00e6c737_37752d5b PS1, Line 79: _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/e3644c58_066a8379 PS1, Line 81: /* GPP_A9 - CLKOUT_LPC0 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/8bc92c30_10369c5c PS1, Line 82: /* DW0: 0x84000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ea68444e_fadcaa2c PS1, Line 83: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/858fd629_a76d6053 PS1, Line 84: /* PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/a607ef5d_e3d8598b PS1, Line 85: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ba68eafa_e87bbe84 PS1, Line 85: _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/e2afdd7a_bd1ea5b0 PS1, Line 87: /* GPP_A10 - CLKOUT_LPC1 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/9f6327fb_7218c92f PS1, Line 88: /* DW0: 0x84000400, DW1: 0x00000000 */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4a6c11ed_94dff1c6 PS1, Line 89: /* DW0: PAD_TRIG(OFF) - IGNORED */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/63fbef8a_09dab89c PS1, Line 90: /* PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/65431855_24c45c64 PS1, Line 91: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/803a1095_799082c2 PS1, Line 91: _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0), please, no spaces at the start of a line File src/mainboard/acer/swift3-SF314-52G-55WQ/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/b077ecc2_eb0badb2 PS1, Line 28: uint32_t tpm_resp=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/633bb673_b670d728 PS1, Line 29: uint8_t tpm_b=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/6688d08d_47a9d4ff PS1, Line 30: uint32_t count=0x2EE; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/c1afbb49_ed16b00c PS1, Line 33: do that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2656dc40_e59f2990 PS1, Line 35: tpm_resp = *(uint32_t*)(0xFED40000); "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/137e948d_825a80d8 PS1, Line 36: tpm_b=tpm_resp & 0x000000FF; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/841fd9ac_4301d249 PS1, Line 38: if (tpm_b == 0xFF) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/473feefd_156a2cd7 PS1, Line 43: if ( (tpm_b & 0x80) == 0x80) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/91f18f83_14db62c3 PS1, Line 43: if ( (tpm_b & 0x80) == 0x80) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4a018dc8_a4ba6f61 PS1, Line 81: uint32_t tmp=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2a710daf_b9ff15fa PS1, Line 83: uint8_t tmpb2=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/6f4b597a_eda016bd PS1, Line 84: uint16_t tmps=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/52da62a5_389618b4 PS1, Line 91: uint32_t tmp5=0; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d15af0e5_13e064ca PS1, Line 107: if ((uint8_t)(tmp >> 0x18) == 0xFF) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/49c691a3_c292f16d PS1, Line 107: if ((uint8_t)(tmp >> 0x18) == 0xFF) { please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/5516e424_f6a2c049 PS1, Line 109: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/bd190a3a_da4d0fe4 PS1, Line 109: } please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/fa57dbb7_e597916e PS1, Line 120: tmpb = inb(0x0073); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/58fd53cc_b6deace8 PS1, Line 120: tmpb = inb(0x0073); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/da5d1ac9_95ee3dbe PS1, Line 121: outb(tmpb, 0x00ED); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/cbea933e_3c2784bc PS1, Line 121: outb(tmpb, 0x00ED); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f58a9b5d_cb7f5ab0 PS1, Line 123: outb(tmpb, 0x0073); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/e21085ad_db59e266 PS1, Line 123: outb(tmpb, 0x0073); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ddc5d545_76943db9 PS1, Line 124: outb(tmpb, 0x00ED); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/851806cd_8aabdf85 PS1, Line 124: outb(tmpb, 0x00ED); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/18f1f96e_4df31727 PS1, Line 127: tmpb = inb(0x0073); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/70eba54e_50d569d1 PS1, Line 127: tmpb = inb(0x0073); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/02a62e60_38d8f7c8 PS1, Line 135: outb(tmpb, 0x00ED); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4c231d38_0e951872 PS1, Line 135: outb(tmpb, 0x00ED); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/087a939a_d87bd77a PS1, Line 165: if ((uint8_t)(tmp >> 0x18) == 0xFF) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/24dedbae_3c660664 PS1, Line 165: if ((uint8_t)(tmp >> 0x18) == 0xFF) { please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d71e9ba4_3533f45c PS1, Line 167: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/71e9d0a0_36a58340 PS1, Line 167: } please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/775339c9_059b0d61 PS1, Line 173: tmp = inl(0xcf8); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/1bde3e7f_dd112748 PS1, Line 173: tmp = inl(0xcf8); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/22ff0526_b8c90b0d PS1, Line 173: tmp = inl(0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/1a491cda_d3bc0b81 PS1, Line 175: outl(0x8000fa44, 0xcf8); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/dc6a49ae_fa36d4d2 PS1, Line 175: outl(0x8000fa44, 0xcf8); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ee8f68dd_3049ab9f PS1, Line 175: outl(0x8000fa44, 0xcf8); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/202abbc1_030f8288 PS1, Line 176: tmpb2 = inb(0xcfc); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/a584291b_4becf802 PS1, Line 176: tmpb2 = inb(0xcfc); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/922bb005_ba8e129d PS1, Line 176: tmpb2 = inb(0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/59ea8193_7d0cbf3a PS1, Line 179: if (tmpb2 & 0x80) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/da7fb83d_fc16cdb4 PS1, Line 182: outl(0x8000fa40,0xcf8); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2ac2d2de_06bfe0fd PS1, Line 183: outw(0x1800,0xcfc); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/32e1fed5_259dc0be PS1, Line 185: outl(0x8000fa44, 0xcf8); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/3da8e376_737872c9 PS1, Line 186: tmpb2 = inb(0xcfc); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ba12cd80_39228a09 PS1, Line 186: tmpb2 = inb(0xcfc); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/eda56e33_152cb1df PS1, Line 186: tmpb2 = inb(0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/da7e64d3_65ad1d7e PS1, Line 189: outb(tmpb2,0xcfc); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7c31a078_0604ddb6 PS1, Line 189: outb(tmpb2,0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/6b7c055b_7ac7f28c PS1, Line 189: outb(tmpb2,0xcfc); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/9cd8f55a_e4463676 PS1, Line 193: outl(0x8000fa40,0xcf8); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/5e156e5c_7785d14b PS1, Line 194: tmps = inw(0xcfc); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f8bc9d46_8f687c65 PS1, Line 194: tmps = inw(0xcfc); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/c777016c_fbedf3e8 PS1, Line 194: tmps = inw(0xcfc); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/0bce7752_5efdcb13 PS1, Line 197: tmps=(tmps & 0xFFFC) + 8; spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/8016acfb_4aed205b PS1, Line 201: for (uint32_t i=0; i<0x2EE; i++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/49fd2a72_85cc34ff PS1, Line 201: for (uint32_t i=0; i<0x2EE; i++) spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4f667157_2b1042c6 PS1, Line 201: for (uint32_t i=0; i<0x2EE; i++) spaces required around that '<' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/410c5f5e_5ab4774c PS1, Line 203: uint32_t t=inl(tmps); spaces required around that '=' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/bf85f1c2_9359f53c PS1, Line 204: if ( ((tmp5 + 0xdfb - t) & 0x00800000) == 0 ) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/b247754b_da7ade9f PS1, Line 204: if ( ((tmp5 + 0xdfb - t) & 0x00800000) == 0 ) space prohibited after that open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/70db58dd_baa9a589 PS1, Line 204: if ( ((tmp5 + 0xdfb - t) & 0x00800000) == 0 ) space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/16b450c1_100ef3a8 PS1, Line 212: outl(0xcf8,tmp); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/36908a08_37e38089 PS1, Line 212: outl(0xcf8,tmp); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/97b61c37_9565d2bd PS1, Line 212: outl(0xcf8,tmp); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/e9bedf17_1629e1eb PS1, Line 212: outl(0xcf8,tmp); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d63c98f0_b201ada3 PS1, Line 213: tmp5=0; spaces required around that '=' (ctx:VxV) File src/superio/ite/it8987e/superio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/af9d0977_346a0c3b PS1, Line 18: if (!dev->enabled) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/88f7b97f_ef9cf0a3 PS1, Line 18: if (!dev->enabled) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/76958e14_f340e84e PS1, Line 19: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/4c5a1c05_ef14d546 PS1, Line 19: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/77da5279_dbd906dc PS1, Line 21: switch (dev->path.pnp.device) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f936c5f1_9efa2311 PS1, Line 21: switch (dev->path.pnp.device) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f054a21d_bdb621c3 PS1, Line 22: case IT8987E_KBCK: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/38766dcb_1e7f6c56 PS1, Line 22: case IT8987E_KBCK: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/8ee2424c_cc91a43e PS1, Line 23: pc_keyboard_init(NO_AUX_DEVICE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/921fded1_92c7b219 PS1, Line 23: pc_keyboard_init(NO_AUX_DEVICE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/3993c3e0_f4c7dbfe PS1, Line 24: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2dc4f34e_f10aee12 PS1, Line 24: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/2ed1b4f4_02ee2e15 PS1, Line 25: default: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/bc0f6aae_96549736 PS1, Line 27: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/dcda6c13_d4ab71f1 PS1, Line 27: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/c89e4eb1_cb7acf68 PS1, Line 28: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/43e39b2a_b03e540d PS1, Line 28: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/3f20f10e_230ed66a PS1, Line 41: { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7be63171_360300b3 PS1, Line 41: { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/d161c5ae_455ccdd9 PS1, Line 42: { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/30fe4aac_3adc2ba9 PS1, Line 42: { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/bb49130d_d8ccef20 PS1, Line 65: const struct superio_ite_it8987e_config *conf; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/29c70382_ee29fd76 PS1, Line 65: const struct superio_ite_it8987e_config *conf; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/57728111_8e6ef3b0 PS1, Line 69: conf = dev->chip_info; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/ca3fbc84_746f1ec3 PS1, Line 69: conf = dev->chip_info; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7b1b5487_cfafb37c PS1, Line 70: if (!conf) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/212701d8_6251bd09 PS1, Line 70: if (!conf) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/f19420f5_3848d54d PS1, Line 70: if (!conf) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/07b11391_5f0cb9cf PS1, Line 74: printk(BIOS_INFO, "IT8987E: init ITE EC\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/7015be06_d57c5398 PS1, Line 75: ite_ec_init(0x25e, &conf->ec); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/cd138d6d_8f3b304e PS1, Line 75: ite_ec_init(0x25e, &conf->ec); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169889): https://review.coreboot.org/c/coreboot/+/72788/comment/faff9471_ec237c64 PS1, Line 75: ite_ec_init(0x25e, &conf->ec); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Feb 2023 14:55:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2023