coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[M] Change in coreboot[master]: drivers/ocp, mb/ocp/deltalake: move get_loglevel_from_vpd function
by David Hendricks (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Arthur Heymans, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Tim Chu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71936 ) Change subject: drivers/ocp, mb/ocp/deltalake: move get_loglevel_from_vpd function ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20 Gerrit-Change-Number: 71936 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:44:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Paul Menzel, Angel Pons, Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64779 ) Change subject: clang-format: Update 'clang-format' file ...................................................................... Patch Set 16: (1 comment) Patchset: PS16: I think this should go back to a clang-format-13 or clang-format-14 file. clang-format-15 hasn't made its way into the package management systems of many popular distros, and the older versions of clang-format choke on the newer version of the file. I mean, by default, debian buster still give you clang-format-11. :-/ -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:43:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Paul Menzel, Angel Pons, Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64779 ) Change subject: clang-format: Update 'clang-format' file ...................................................................... Patch Set 16: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:36:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
by 9elements QA (Code Review) 05 Feb '23

05 Feb '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72694 ) Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149417 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149415 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/149414 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/149413 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/149412 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149411 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/149410 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/149409 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/149408 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/149407 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/149406 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/149405 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149404 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/149403 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/149402 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/149401 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/72694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Gerrit-Change-Number: 72694 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Chao Gui <chaogui(a)google.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:36:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Paul Menzel, Angel Pons, Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64779 ) Change subject: clang-format: Update 'clang-format' file ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:24:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: security/vboot: Don't build with flashrom support
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72716 ) Change subject: security/vboot: Don't build with flashrom support ...................................................................... security/vboot: Don't build with flashrom support We don't need flashrom support just for vboot payloads. The current default (USE_FLASHROM=1) is mostly harmless, especially if libflashrom is not present (the autodetection in vboot_reference just spits out a pkg-config error but doesn't actually fail the build), but it's better to be clear we don't need it. BUG=b:172225709 TEST=build Change-Id: I53bcc2d1e7666646ddad58ba3717cfdd321014e8 Signed-off-by: Brian Norris <briannorris(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72716 Reviewed-by: Jack Rosenthal <jrosenth(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/security/vboot/Makefile.inc 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jack Rosenthal: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 8747e02..f6103bb 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -33,6 +33,7 @@ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ V=$(V) \ + USE_FLASHROM=0 \ fwlib \ $(if $(CONFIG_SBOM_VBOOT),$$(abspath $$(dir $$(VBOOT_LIB_$(1))))/vboot_host.pc) -- To view, visit https://review.coreboot.org/c/coreboot/+/72716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53bcc2d1e7666646ddad58ba3717cfdd321014e8 Gerrit-Change-Number: 72716 Gerrit-PatchSet: 5 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: amdfwtool: Remove useless printing out
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72724 ) Change subject: amdfwtool: Remove useless printing out ...................................................................... amdfwtool: Remove useless printing out Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72724 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/amdfwtool/data_parse.c 1 file changed, 13 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index dde1f97..f30196a5 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -374,7 +374,6 @@ fw_type = AMD_FW_MPIO; subprog = 0; } else if (strcmp(fw_name, "TPMLITE_FILE") == 0) { - printf("TPMLITE\n"); fw_type = AMD_FW_TPMLITE; subprog = 0; } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/72724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4 Gerrit-Change-Number: 72724 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: amdfwtool: Add a function to make the calling stack less deep
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51881 ) Change subject: amdfwtool: Add a function to make the calling stack less deep ...................................................................... amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M util/amdfwtool/data_parse.c 1 file changed, 52 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 8c22dc5..dde1f97 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -611,6 +611,39 @@ return lvl; } +static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir, + uint8_t print_deps, amd_cb_config *cb_config) +{ + char *path_filename, *fn = &(oneline[match[2].rm_so]); + char *fw_type_str = &(oneline[match[1].rm_so]); + char ch_lvl = 'x'; + regoff_t ch_lvl_index = match[3].rm_so; + + /* If the optional level field is present, + extract the level char. */ + ch_lvl = get_level_from_config(oneline, ch_lvl_index, cb_config); + + path_filename = malloc(MAX_LINE_SIZE * 2 + 2); + snprintf(path_filename, MAX_LINE_SIZE * 2 + 2, "%.*s/%.*s", + MAX_LINE_SIZE, dir, MAX_LINE_SIZE, fn); + + if (find_register_fw_filename_psp_dir( + fw_type_str, path_filename, ch_lvl, cb_config) == 0) { + if (find_register_fw_filename_bios_dir( + fw_type_str, path_filename, ch_lvl, cb_config) == 0) { + fprintf(stderr, "Module's name \"%s\" is not valid\n", fw_type_str); + return 0; /* Stop parsing. */ + } else { + if (print_deps) + printf(" %s ", path_filename); + } + } else { + if (print_deps) + printf(" %s ", path_filename); + } + return 1; +} + /* return value: 0: The config file can not be parsed correctly. @@ -618,7 +651,7 @@ */ uint8_t process_config(FILE *config, amd_cb_config *cb_config, uint8_t print_deps) { - char oneline[MAX_LINE_SIZE], *path_filename; + char oneline[MAX_LINE_SIZE]; regmatch_t match[N_MATCHES]; char dir[MAX_LINE_SIZE] = {'\0'}; uint32_t dir_len; @@ -668,34 +701,9 @@ if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATION") == 0) { continue; } else { - char ch_lvl = 'x'; - path_filename = malloc(MAX_LINE_SIZE * 2 + 2); - snprintf(path_filename, MAX_LINE_SIZE * 2 + 2, "%.*s/%.*s", - MAX_LINE_SIZE, dir, MAX_LINE_SIZE, - &(oneline[match[2].rm_so])); - - /* If the optional level field is present, - extract the level char. */ - ch_lvl = get_level_from_config(oneline, - match[3].rm_so, cb_config); - - if (find_register_fw_filename_psp_dir( - &(oneline[match[1].rm_so]), - path_filename, ch_lvl, cb_config) == 0) { - if (find_register_fw_filename_bios_dir( - &(oneline[match[1].rm_so]), - path_filename, ch_lvl, cb_config) - == 0) { - fprintf(stderr, "Module's name \"%s\" is not valid\n", oneline); - return 0; /* Stop parsing. */ - } else { - if (print_deps) - printf(" %s ", path_filename); - } - } else { - if (print_deps) - printf(" %s ", path_filename); - } + if (process_one_line(oneline, match, dir, print_deps, + cb_config) == 0) + return 0; } } else { fprintf(stderr, "AMDFWTOOL config file line can't be parsed \"%s\"\n", oneline); -- To view, visit https://review.coreboot.org/c/coreboot/+/51881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Gerrit-Change-Number: 51881 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload feature
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72035 ) Change subject: mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload feature ...................................................................... mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload feature 1. Enable Cnvi BT Audio Offload feature and also configure the virtual GPIO for CNVi Bluetooth I2S pads. 2. According to the SOC_GPIO_Table_20230116, Change GPIO GPP_D15, GPP_D16 to NC. BUG=b:264834572 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423 Signed-off-by: Jamie chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/gpio.c M src/mainboard/google/brya/variants/omnigul/overridetree.cb 2 files changed, 45 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/omnigul/gpio.c b/src/mainboard/google/brya/variants/omnigul/gpio.c index f65f8ab..704ef8f 100644 --- a/src/mainboard/google/brya/variants/omnigul/gpio.c +++ b/src/mainboard/google/brya/variants/omnigul/gpio.c @@ -105,9 +105,9 @@ /* D14 : ISH_UART0_TXD ==> NC */ PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> GPP_D15 */ - PAD_CFG_GPI_LOCK(GPP_D15, NONE, LOCK_CONFIG), + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> GPP_D16 */ - PAD_CFG_GPI_LOCK(GPP_D16, NONE, LOCK_CONFIG), + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : UART1_RXD ==> GPP_D17 */ PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> NC */ @@ -255,6 +255,24 @@ /* GPD10: SLP_S5# ==> SLP_S5_L */ /* GPD11: LANPHYC ==> GPD11 */ PAD_NC(GPD11, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 53f3fea..79e948d 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -44,6 +44,9 @@ .configure_ext_fivr = 1, }" + # Enable the Cnvi BT Audio Offload + register "cnvi_bt_audio_offload" = "1" + device domain 0 on device ref i2c0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/72035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423 Gerrit-Change-Number: 72035 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/brya/var/omnigul: Add variant specific devicetree
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71883 ) Change subject: mb/google/brya/var/omnigul: Add variant specific devicetree ...................................................................... mb/google/brya/var/omnigul: Add variant specific devicetree This variant was added without a devicetree, so add the board specific devicetree according to schematic_20230110. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/omnigul/overridetree.cb 2 files changed, 228 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Ian Feng: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7b980e7..087837f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -331,3 +331,4 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS + select DRIVERS_INTEL_ISH diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 4f2c04a..53f3fea 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -1,6 +1,212 @@ chip soc/intel/alderlake - device domain 0 on - end + register "sagv" = "SaGv_Enabled" + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3 Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3 Port 2 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3 Port 3 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" # Type C port C0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1 + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" # Type C port C1 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable Port3 + + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 1 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C1 + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end #I2C3 + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end #I2C5 + device ref pcie_rp8 off end + device ref pcie_rp9 off end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[2] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/71883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Gerrit-Change-Number: 71883 Gerrit-PatchSet: 17 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023