coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
by Cliff Huang (Code Review) 05 Feb '23

05 Feb '23

Cliff Huang has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72826 ) Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic ...................................................................... src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic _ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. Before exiting, it needs to check if it was scheduled to be skipped first. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will aslo increments ONSK. Similarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72826/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Gerrit-Change-Number: 72826 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Elyes Haouas (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Paul Menzel, Angel Pons, Elyes Haouas. Hello build bot (Jenkins), Martin L Roth, Jonathan Zhang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64779 to look at the new patch set (#18). Change subject: clang-format: Update 'clang-format' file ...................................................................... clang-format: Update 'clang-format' file Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .clang-format 1 file changed, 163 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/64779/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 18 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Elyes Haouas (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Paul Menzel, Angel Pons, Elyes Haouas. Hello build bot (Jenkins), Martin L Roth, Jonathan Zhang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64779 to look at the new patch set (#17). Change subject: clang-format: Update 'clang-format' file ...................................................................... clang-format: Update 'clang-format' file Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .clang-format 1 file changed, 164 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/64779/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 17 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Makefile.inc: Use 'Wmissing-include-dirs' command option
by Elyes Haouas (Code Review) 05 Feb '23

05 Feb '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70251 ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Makefile.inc: Use 'Wmissing-include-dirs' command option ...................................................................... Makefile.inc: Use 'Wmissing-include-dirs' command option This is to warn if a user add to Makefile a path to nonexistent directory. Change-Id: I5a30c3830f30509deaaadc6eaeab0e17bc08565c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70251 Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, but someone else must approve diff --git a/Makefile.inc b/Makefile.inc index f1f4646..96121d4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -423,7 +423,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition -CFLAGS_common += -Wdangling-else +CFLAGS_common += -Wdangling-else -Wmissing-include-dirs CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/70251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a30c3830f30509deaaadc6eaeab0e17bc08565c Gerrit-Change-Number: 70251 Gerrit-PatchSet: 34 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
by build bot (Jenkins) (Code Review) 05 Feb '23

05 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72826 ) Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169921): https://review.coreboot.org/c/coreboot/+/72826/comment/6dd04a57_8ae3bd5c PS1, Line 15: _RST(), it increments OFSK. When the following _OFF() is called, it 'Similiarly' may be misspelled - perhaps 'Similarly'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169921): https://review.coreboot.org/c/coreboot/+/72826/comment/11e225fc_7c78ca87 PS1, Line 22: BUG=b:241850118 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Gerrit-Change-Number: 72826 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 05 Feb 2023 05:32:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic
by Cliff Huang (Code Review) 05 Feb '23

05 Feb '23

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72826 ) Change subject: src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic ...................................................................... src/soc/intel/common/block/pcie/rtd3: Fix root port _ON logic _ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. Before exiting, it needs to check if it was scheduled to be skipped first. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will aslo increments ONSK. Similiarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/72826/1 diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 8a67367..726d489 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -144,6 +144,12 @@ acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA")); acpigen_emit_byte(LOCAL0_OP); acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP); + if (config->skip_on_off_support) { + acpigen_write_if_lgreater_namestr_int("ONSK", 0); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_namestring("ONSK"); + acpigen_write_if_end(); + } acpigen_write_return_op(ONE_OP); acpigen_write_if_end(); -- To view, visit https://review.coreboot.org/c/coreboot/+/72826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Gerrit-Change-Number: 72826 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/acpi: add function gen: if_lgreater_ and namestr assignment
by Cliff Huang (Code Review) 05 Feb '23

05 Feb '23

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72825 ) Change subject: src/acpi: add function gen: if_lgreater_ and namestr assignment ...................................................................... src/acpi: add function gen: if_lgreater_ and namestr assignment 1. add functions to generate if greater than conditions: acpigen_write_if_lgreater_op_op: if (op1 > op2) acpigen_write_if_lgreater_op_int: if (op > val) acpigen_write_if_lgreater_namestr_int: if (namestr > val) 2. add function to assignal value to a namestr acpigen_write_store_namestr_to_op: namestr = val TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/72825/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 305cddb..725a2d8 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1368,6 +1368,14 @@ acpigen_emit_namestring(dst); } +/* Store ("namestr", dst) */ +void acpigen_write_store_namestr_to_op(const char *src, uint8_t dst) +{ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(dst); +} + /* Store (src, dst) */ void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst) { @@ -1527,6 +1535,20 @@ } /* + * Generates ACPI code for checking if operand1 is greater than operand2. + * Both operand1 and operand2 are ACPI ops. + * + * If (Lgreater (op1 op2)) + */ +void acpigen_write_if_lgreater_op_op(uint8_t op1, uint8_t op2) +{ + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(op1); + acpigen_emit_byte(op2); +} + +/* * Generates ACPI code for checking if operand1 and operand2 are equal, where, * operand1 is ACPI op and operand2 is an integer. * @@ -1541,6 +1563,20 @@ } /* + * Generates ACPI code for checking if operand is greater than the value, where, + * operand is ACPI op and val is an integer. + * + * If (Lgreater (op, val)) + */ +void acpigen_write_if_lgreater_op_int(uint8_t op, uint64_t val) +{ + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(op); + acpigen_write_integer(val); +} + +/* * Generates ACPI code for checking if operand1 and operand2 are equal, where, * operand1 is namestring and operand2 is an integer. * @@ -1555,6 +1591,20 @@ } /* + * Generates ACPI code for checking if operand1 and operand2 are equal, where, + * operand1 is namestring and operand2 is an integer. + * + * If (Lgreater ("namestr", val)) + */ +void acpigen_write_if_lgreater_namestr_int(const char *namestr, uint64_t val) +{ + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_namestring(namestr); + acpigen_write_integer(val); +} + +/* * Generates ACPI code to check at runtime if an object named `namestring` * exists, and leaves the If scope open to continue execute code when this * is true. NOTE: Requires matching acpigen_write_if_end(). diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index c506021..cf88100 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -487,6 +487,7 @@ void acpigen_write_store_int_to_op(uint64_t src, uint8_t dst); void acpigen_write_store_ops(uint8_t src, uint8_t dst); void acpigen_write_store_op_to_namestr(uint8_t src, const char *dst); +void acpigen_write_store_namestr_to_op(const char *src, uint8_t dst); void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_xor(uint8_t arg1, uint8_t arg2, uint8_t res); void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); @@ -506,8 +507,11 @@ void acpigen_write_if(void); void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); void acpigen_write_if_lequal_op_op(uint8_t op, uint8_t val); +void acpigen_write_if_lgreater_op_op(uint8_t op1, uint8_t op2); void acpigen_write_if_lequal_op_int(uint8_t op, uint64_t val); +void acpigen_write_if_lgreater_op_int(uint8_t op, uint64_t val); void acpigen_write_if_lequal_namestr_int(const char *namestr, uint64_t val); +void acpigen_write_if_lgreater_namestr_int(const char *namestr, uint64_t val); __always_inline void acpigen_write_if_end(void) { acpigen_pop_len(); -- To view, visit https://review.coreboot.org/c/coreboot/+/72825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818 Gerrit-Change-Number: 72825 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
by 9elements QA (Code Review) 05 Feb '23

05 Feb '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72051 ) Change subject: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping ...................................................................... Patch Set 10: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149570 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/149568 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/149567 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/149566 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/149565 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149564 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/149563 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/149562 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/149561 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/149560 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/149559 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/149558 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/149557 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/149556 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/149555 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/149554 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/72051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Gerrit-Change-Number: 72051 Gerrit-PatchSet: 10 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 05:08:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: add MSR definition for SPR-SP
by Jonathan Zhang (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: TimLiu-SMCI, Johnny Lin, David Hendricks, Christian Walter, Jian-Ming Wang, Arthur Heymans, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72611 ) Change subject: soc/intel/xeon_sp: add MSR definition for SPR-SP ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/include/soc/msr.h: https://review.coreboot.org/c/coreboot/+/72611/comment/320c0e99_a9ca2ecf PS1, Line 44: #if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)) > Agreed. […] skx/cpx/spr have different include path for <skx|cpx|spr>/include/soc.Therefore, we could have files with same file name (soc_msr.h) in those directories. And then mer.h just need to have one line: #include <soc/soc_msr.h> and the rest of the definitions are common for all xeon_sp socs. -- To view, visit https://review.coreboot.org/c/coreboot/+/72611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f2d8ac85d9fb1e75d51ad7b5fe5d9152900fc3b Gerrit-Change-Number: 72611 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 05:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Add IIO resources via SSDT
by Jonathan Zhang (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Christian Walter, Arthur Heymans, Jian-Ming Wang, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70501 ) Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: Tim, could you give this a try on DeltaLake? Thanks! File src/soc/intel/xeon_sp/skx/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/70501/comment/605064d7_6a729f21 PS1, Line 92: acpigen_write_name("ICRS"); > Naming it _CRS directly is actually even better. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I188090819023ca83f14c4610266d215ba34379b8 Gerrit-Change-Number: 70501 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 05:01:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit February 2023