coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code
by Jonathan Zhang (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Arthur Heymans, Jian-Ming Wang, Shuming Chu (Shuming). Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 ) Change subject: soc/intel/xeon_sp/spr: add ACPI code ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/xeon_sp/spr/romstage.c: https://review.coreboot.org/c/coreboot/+/71967/comment/5e7a48fd_b043d389 PS2, Line 177: 0x3F8; > SerialIoUartDebugIoBase in FSPM_UPD is used to control the debug message from Intel FSP. […] I think: * Instead of hardcoding, it should be taken from CONFIG_TTYS0_BASE. * It should be set in mainboard code, instead of SoC code. -- To view, visit https://review.coreboot.org/c/coreboot/+/71967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Gerrit-Change-Number: 71967 Gerrit-PatchSet: 13 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 04:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jian-Ming Wang <jianmingW(a)supermicro.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Paul Menzel, Sridhar Siricilla, Usha P. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72706 to look at the new patch set (#5). Change subject: mb/intel/mtlrvp: Enable GSPI interface ...................................................................... mb/intel/mtlrvp: Enable GSPI interface This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223) SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72706/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/72706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Gerrit-Change-Number: 72706 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add chip configuration for I2C devices
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72647 to look at the new patch set (#7). Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices ...................................................................... mb/intel/mtlrvp: Add chip configuration for I2C devices This patch adds below chip configuration for I2C devices for mtlrvp. +-----------+--------------------+-------------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | +-----------+--------------------+-------------+ | I2C0 | 0:0x15:0 | CAM1 | +-----------+--------------------+-------------+ | I2C1 | 0:0x15:1 | CAM0 | +-----------+--------------------+-------------+ | I2C2 | 0:0x15:2 | NC | +-----------+--------------------+-------------+ | I2C3 | 0:0x15:3 | HID | +-----------+--------------------+-------------+ | I2C4 | 0:0x15:4 | NC | +-----------+--------------------+-------------+ | I2C5 | 0:0x15:5 | NC | +-----------+--------------------+-------------+ BUG=b:224325352 BRANCH=None TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus enumeration through lspci. 00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01) 00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01) 00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Ia5964472be902041f961187c0072a89055badd4f Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/72647/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/72647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5964472be902041f961187c0072a89055badd4f Gerrit-Change-Number: 72647 Gerrit-PatchSet: 7 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Override display configuration
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Usha P. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72645 to look at the new patch set (#6). Change subject: mb/intel/mtlrvp: Override display configuration ...................................................................... mb/intel/mtlrvp: Override display configuration This patch enables display configuration for mtlrvp. The change follows mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump. Also verify display over eDP and HDMI. DdiPortAConfig : 0x1 DdiPortBConfig : 0x0 DdiPortAHpd : 0x0 DdiPortBHpd : 0x1 DdiPortCHpd : 0x0 DdiPort1Hpd : 0x0 DdiPort2Hpd : 0x0 DdiPort3Hpd : 0x0 DdiPort4Hpd : 0x0 DdiPortADdc : 0x0 DdiPortBDdc : 0x1 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/72645/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/72645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Gerrit-Change-Number: 72645 Gerrit-PatchSet: 6 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add chip configuration for I2C devices
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72647 to look at the new patch set (#5). Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices ...................................................................... mb/intel/mtlrvp: Add chip configuration for I2C devices This patch adds below chip configuration for I2C devices for mtlrvp. +-----------+--------------------+-------------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | +-----------+--------------------+-------------+ | I2C0 | 0:0x15:0 | CAM1 | +-----------+--------------------+-------------+ | I2C1 | 0:0x15:1 | CAM0 | +-----------+--------------------+-------------+ | I2C2 | 0:0x15:2 | NC | +-----------+--------------------+-------------+ | I2C3 | 0:0x15:3 | HID | +-----------+--------------------+-------------+ | I2C4 | 0:0x15:4 | NC | +-----------+--------------------+-------------+ | I2C5 | 0:0x15:5 | NC | +-----------+--------------------+-------------+ BUG=b:224325352 BRANCH=None TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus enumeration through lspci. 00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01) 00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01) 00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01) Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Ia5964472be902041f961187c0072a89055badd4f Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/72647/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/72647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5964472be902041f961187c0072a89055badd4f Gerrit-Change-Number: 72647 Gerrit-PatchSet: 5 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Override display configuration
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jamie Ryu, Sridhar Siricilla, Usha P. Hello build bot (Jenkins), Jamie Ryu, Sridhar Siricilla, Eric Lai, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72645 to look at the new patch set (#4). Change subject: mb/intel/mtlrvp: Override display configuration ...................................................................... mb/intel/mtlrvp: Override display configuration This patch enables display configuration for mtlrvp. The change follows mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump. Also verify display over eDP and HDMI. DdiPortAConfig : 0x1 DdiPortBConfig : 0x0 DdiPortAHpd : 0x0 DdiPortBHpd : 0x1 DdiPortCHpd : 0x0 DdiPort1Hpd : 0x0 DdiPort2Hpd : 0x0 DdiPort3Hpd : 0x0 DdiPort4Hpd : 0x0 DdiPortADdc : 0x0 DdiPortBDdc : 0x1 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/72645/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Gerrit-Change-Number: 72645 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform
by Usha P (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Harsha B R, Ravishankar Sarawadi, Sridhar Siricilla. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72742 ) Change subject: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 Gerrit-Change-Number: 72742 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 02:22:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES
by Harsha B R (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Ravishankar Sarawadi, Usha P, Eric Lai. Hello Ravishankar Sarawadi, Usha P, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72813 to look at the new patch set (#2). Change subject: mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES ...................................................................... mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHES This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which helps in mode switch using dut-control power_state:rec. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode. Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/72813/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Gerrit-Change-Number: 72813 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/ocp/vpd: Override mainboard_set_smm_log_level
by David Hendricks (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Johnny Lin, Angel Pons, Shuming Chu (Shuming), Arthur Heymans. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71992 ) Change subject: drivers/ocp/vpd: Override mainboard_set_smm_log_level ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574 Gerrit-Change-Number: 71992 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:45:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/smm: Enable setting SMM console log level from mainboard
by David Hendricks (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Marc Jones, Martin L Roth, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Paul Menzel, Rocky Phagura, Jingle Hsu, Angel Pons, Arthur Heymans, Morgan Jang, Kyösti Mälkki. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard ...................................................................... Patch Set 34: Code-Review+2 (1 comment) File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/49460/comment/c1315fd6_e5ae17a4 PS28, Line 58: return smm_runtime.smm_log_level; > Do you mean removing the preprocessor at line 55 '#if CONFIG(RUNTIME_CONFIGURABLE_SMM_LOGLEVEL)' and […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 34 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 01:45:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2023