coreboot-gerrit February 2023

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[M] Change in coreboot[master]: security/vboot: Add store/validate methods for VBIOS FMAP cache
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Andrey Pronin, Raul Rangel, Matt DeVillier, Julius Werner, Martin Roth, Yu-Ping Wu, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72401 ) Change subject: security/vboot: Add store/validate methods for VBIOS FMAP cache ...................................................................... Patch Set 4: (2 comments) File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/c/coreboot/+/72401/comment/71a3b59f_9766c7b7 PS4, Line 520: setup_space > > this "create on 1st write" is useful to deploy the feature on the devices already in the field, wh […] Karthik, are you saying we should have a Kconfig option for switching between setup_space and disabling it? The advantage of leaving this in is that it will work on existing boards that weren't initialized in the factory. What's the disadvantage of leaving it? https://review.coreboot.org/c/coreboot/+/72401/comment/971d3d23_ac1ec7a7 PS4, Line 520: return Why would we choose to always return instead of continuing to write the buffer out after setting up the TPM (so long as setup_space works)? Also, because the code calling this will get the return code from setup_space instead of safe_write, if setup_space works, i think the code will believes that it was correctly written out, even though it wasn't. So whatever we do, I think returning this way is wrong. It's not a huge deal - just printing the warning message vs not, but still wrong, (I think). -- To view, visit https://review.coreboot.org/c/coreboot/+/72401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I030017d3bf956b8593bc09073ad6545b80a5b52b Gerrit-Change-Number: 72401 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:29:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Andrey Pronin <apronin(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Adding new ITE IT8987e
by build bot (Jenkins) (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72827 ) Change subject: Adding new ITE IT8987e ...................................................................... Patch Set 1: (32 comments) File src/superio/ite/it8987e/superio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/e4f48a5b_d3a97edc PS1, Line 18: if (!dev->enabled) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/973b18f7_e5eedb82 PS1, Line 18: if (!dev->enabled) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/5d7ee3a2_523495d9 PS1, Line 19: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/575319c0_2f7ac79b PS1, Line 19: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/b98e465c_2a29b956 PS1, Line 21: switch (dev->path.pnp.device) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/1850e995_730afdd4 PS1, Line 21: switch (dev->path.pnp.device) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/408a1f32_6562f98d PS1, Line 22: case IT8987E_KBCK: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/8ca950e9_bd52c4c5 PS1, Line 22: case IT8987E_KBCK: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/cf91b8a1_8154e961 PS1, Line 23: pc_keyboard_init(NO_AUX_DEVICE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/8408dbc5_1c8e9168 PS1, Line 23: pc_keyboard_init(NO_AUX_DEVICE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/4d01137d_1476a91b PS1, Line 24: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/39539a94_6b6fdd94 PS1, Line 24: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/10b85c11_283b1608 PS1, Line 25: default: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/01b45fe1_9ae04e54 PS1, Line 27: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/19166a5c_1219e2d7 PS1, Line 27: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/9658ccb1_e51d780d PS1, Line 28: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/19981cfe_c9ee4e6e PS1, Line 28: } please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/68e55a46_86d60174 PS1, Line 41: { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/5cbe22a8_2495188b PS1, Line 41: { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/af9482ae_9493e876 PS1, Line 42: { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/90428ac2_be150b76 PS1, Line 42: { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/28cdd618_834db09a PS1, Line 65: const struct superio_ite_it8987e_config *conf; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/8cf9e530_b004b6ca PS1, Line 65: const struct superio_ite_it8987e_config *conf; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/7e992ba4_16be3e55 PS1, Line 69: conf = dev->chip_info; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/de720446_a2f7ca2b PS1, Line 69: conf = dev->chip_info; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/efd56675_b0511ad2 PS1, Line 70: if (!conf) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/d9ccf847_e544292e PS1, Line 70: if (!conf) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/07f89e41_8fd21c34 PS1, Line 70: if (!conf) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/c5c72b4a_cb788c0a PS1, Line 74: printk(BIOS_INFO, "IT8987E: init ITE EC\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/7110d470_f0adb278 PS1, Line 75: ite_ec_init(0x25e, &conf->ec); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/a72ab840_3e683578 PS1, Line 75: ite_ec_init(0x25e, &conf->ec); please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169931): https://review.coreboot.org/c/coreboot/+/72827/comment/1b2f21cd_9b9f460e PS1, Line 75: ite_ec_init(0x25e, &conf->ec); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/72827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide92e41ccadcea665544a07895614fa9514619e2 Gerrit-Change-Number: 72827 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:22:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Adding new ITE IT8987e
by char (Code Review) 05 Feb '23

05 Feb '23

char has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72827 ) Change subject: Adding new ITE IT8987e ...................................................................... Adding new ITE IT8987e This is specifically to support the Acer Swift 3 mainboard addition. See changeset 70623. Signed-off-by: hack-char <char(a)dmail.site> Change-Id: Ide92e41ccadcea665544a07895614fa9514619e2 --- M src/superio/ite/Makefile.inc A src/superio/ite/it8987e/Kconfig A src/superio/ite/it8987e/Makefile.inc A src/superio/ite/it8987e/chip.h A src/superio/ite/it8987e/it8987e.h A src/superio/ite/it8987e/superio.c 6 files changed, 145 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/72827/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 8ff122b..3cb3b71 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -18,3 +18,4 @@ subdirs-y += it8772f subdirs-y += it8783ef subdirs-y += it8786e +subdirs-y += it8987e diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig new file mode 100644 index 0000000..dba9879 --- /dev/null +++ b/src/superio/ite/it8987e/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_ITE_IT8987E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc new file mode 100644 index 0000000..90bdfb5 --- /dev/null +++ b/src/superio/ite/it8987e/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c diff --git a/src/superio/ite/it8987e/chip.h b/src/superio/ite/it8987e/chip.h new file mode 100644 index 0000000..98884e3 --- /dev/null +++ b/src/superio/ite/it8987e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8987E_CHIP_H +#define SUPERIO_ITE_IT8987E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8987e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8987E_CHIP_H */ diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h new file mode 100644 index 0000000..7e9f7eb --- /dev/null +++ b/src/superio/ite/it8987e/it8987e.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8987E_H +#define SUPERIO_ITE_IT8987E_H + +#define IT8987E_SP1 0x01 /* Com1 */ +#define IT8987E_SP2 0x02 /* Com2 */ +#define IT8987E_SWUC 0x04 /* System Wake-Up */ +#define IT8987E_KBCM 0x05 /* PS/2 mouse */ +#define IT8987E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8987E_IR 0x0a /* Consumer IR */ +#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8987E_RTCT 0x10 /* RTC-like Timer */ +#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */ +#define IT8987E_PECI 0x14 /* Platform EC Interface */ +#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */ + +#endif /* SUPERIO_ITE_IT8987E_H */ diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c new file mode 100644 index 0000000..6a047e0 --- /dev/null +++ b/src/superio/ite/it8987e/superio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> +#include <pc80/keyboard.h> +#include <console/console.h> + +#include "it8987e.h" +#include "chip.h" + + +static void it8987e_init(struct device *dev) +{ + + printk(BIOS_INFO, "IT8987E: init\n"); + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8987E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + printk(BIOS_INFO, "IT8987E: unknown default %d\n", dev->path.pnp.device); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8987e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8987E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8987E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8987E_KBCM, PNP_IRQ0, }, + { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, }, + { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0 + | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0, + 0x07fc, 0x07fc, 0xfff0 }, + { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 }, + { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, + { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x07ff, 0x07ff }, +}; + +static void enable_dev(struct device *dev) +{ + const struct superio_ite_it8987e_config *conf; + + printk(BIOS_INFO, "IT8987E: enable\n"); + + conf = dev->chip_info; + if (!conf) + { + printk(BIOS_ERR, "IT8987E: unable to init, bad conf/res\n"); + } else { + printk(BIOS_INFO, "IT8987E: init ITE EC\n"); + ite_ec_init(0x25e, &conf->ec); + } + + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8987e_ops = { + CHIP_NAME("ITE IT8987E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/72827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide92e41ccadcea665544a07895614fa9514619e2 Gerrit-Change-Number: 72827 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: ec/google/chromeec: clang-format ec_commands.h
by Elyes Haouas (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Subrata Banik, Caveh Jalali, Nick Vaccaro, Boris Mittelberg. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72639 ) Change subject: ec/google/chromeec: clang-format ec_commands.h ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Are you using this one https://review.coreboot.org/c/coreboot/+/64779 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/72639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06 Gerrit-Change-Number: 72639 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:15:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/gfx: add support for caching VBIOS in FMAP
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Jon Murphy, Martin Roth, Fred Reitberger, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70858 ) Change subject: soc/amd/common/block/gfx: add support for caching VBIOS in FMAP ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9cfd192500d411655a3c8fa436098897428109e Gerrit-Change-Number: 70858 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:14:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: char, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: You need to use a real name, and add a signed-off-by line to the commit message. This is saying that you're the original author of this code or have the rights to push it to the project. -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: char Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:05:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by Nicholas Chin (Code Review) 05 Feb '23

05 Feb '23

1 0

[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by Nicholas Chin (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: char, Felix Held. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Patch Set 1: (8 comments) Patchset: PS1: > Sorry, this should have been amended to 70623 (adding Acer Swift 3 mainboard). […] Done. I'll leave the other 2 unresolved comments here up, and I'll mark them as resolved or move them depending on what you want to do with this patchset. File src/mainboard/acer/swift3-SF314-52G-55WQ/devicetree.cb: https://review.coreboot.org/c/coreboot/+/72788/comment/d61ab0e9_ff22b1f5 PS1, Line 39: # Enable S0ix : register "s0ix_enable" = "1" : register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h : register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h : register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" # 19:18 in pmbase+0018h : register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" # 17:16 in pmbase+0018h > Please change to tabs to be consistent with the rest of the file (seems like tabs are preferred anyw […] Moving comments to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/ae6dc898_77171ebf PS1, Line 129: register "PcieRpMaxPayload[0]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[4]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[8]" = "RpMaxPayload_128" : register "PcieRpMaxPayload[10]" = "RpMaxPayload_128" > Tabs Moving comments to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/dd23c805_c48cbff3 PS1, Line 149: register "PcieRpClkReqSupport[0]" = "0" : register "PcieRpClkReqSupport[4]" = "0" : register "PcieRpClkReqSupport[8]" = "0" : register "PcieRpClkReqSupport[10]" = "0" : : register "PcieRpClkReqNumber[0]" = "0" # Nvidia GPU : register "PcieRpClkReqNumber[4]" = "0" # NVME drive : register "PcieRpClkReqNumber[8]" = "0" # Wifi : register "PcieRpClkReqNumber[10]" = "0" # LPC > Tabs Moving comments to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/10273aae_1295046d PS1, Line 215: device lapic 0 on end > As of commit 69cd729c0c (mb/*: Remove lapic from devicetree) this line should be removed Moved comment to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/f47279be_14d0f831 PS1, Line 263: chip superio/ite/it8987e # 'on' for everything returned from superiotool /w vendor ROM > Many lines in this chip instance have tab/space issues Moving comments to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/27bdb750_1b9c3bc2 PS1, Line 360: end > nit: Fix alignment with corresponding chip line in line 358 Moving comments to CB:70623 https://review.coreboot.org/c/coreboot/+/72788/comment/18393505_147ef3a4 PS1, Line 358: chip drivers/crb : device mmio 0xfed40000 on end # this is the Intel PTT iTPM : end > Tabs Moving comments to CB:70623 -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: char Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 20:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: char Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Intel TPM works, troubleshooting potential battery charge not being s...
by char (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Felix Held. char has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72788 ) Change subject: Intel TPM works, troubleshooting potential battery charge not being shown Added ITE8987e superio/EC ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Sorry, this should have been amended to 70623 (adding Acer Swift 3 mainboard). Is it possible to move your review comments to that one? -- To view, visit https://review.coreboot.org/c/coreboot/+/72788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5af5bdc9799647959e02e5fef05ccc2f0ae36ca Gerrit-Change-Number: 72788 Gerrit-PatchSet: 1 Gerrit-Owner: char Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 19:53:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: clang-format: Update 'clang-format' file
by Elyes Haouas (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Martin L Roth, Paul Menzel, Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64779 ) Change subject: clang-format: Update 'clang-format' file ...................................................................... Patch Set 19: (1 comment) Patchset: PS18: > Thank yoy Thank you* :) -- To view, visit https://review.coreboot.org/c/coreboot/+/64779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec6b6d47c58c393dc28f91cbf109f3e87f935bf Gerrit-Change-Number: 64779 Gerrit-PatchSet: 19 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 18:12:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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