coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3037 discussions

[XS] Change in coreboot[master]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Deepti Deshatty has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78398?usp=email ) Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... Abandoned https://review.coreboot.org/c/coreboot/+/79209 created on Main branch -- To view, visit https://review.coreboot.org/c/coreboot/+/78398?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 78398 Gerrit-PatchSet: 5 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Deepti Deshatty. Deepti Deshatty has uploaded a new patch set (#3) to the change originally created by Deepti Deshatty. ( https://review.coreboot.org/c/coreboot/+/79209?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... mtlrvp: add SI_EC region in flash map MTLRVP booted with microchip EC1723 which do not have an internal flash memory similar to the windows RVP designs. Using MEC1723 for chrome helps in RVP BOM convergence. EC, AP shares the same external SPI flash. EC ROM will download the EC firmware from external SPI to internal SRAM for execution. This patch adds SI_EC region similar to windows. Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 3 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Deepti Deshatty, Deepti Deshatty, Krishna P Bhat D, V Sowmya. Hello Balaji Manigandan, Deepti Deshatty, Krishna P Bhat D, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78398?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... mtlrvp: add SI_EC region in flash map MTLRVP booted with microchip EC1723 which do not have an internal flash memory similar to the windows RVP designs. Using MEC1723 for chrome helps in RVP BOM convergence. EC, AP shares the same external SPI flash. EC ROM will download the EC firmware from external SPI to internal SRAM for execution. This patch adds SI_EC region similar to windows. Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/78398/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78398?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 78398 Gerrit-PatchSet: 5 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/rex/var/karis: Update fw_config settings
by Subrata Banik (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79176?usp=email ) Change subject: mb/google/rex/var/karis: Update fw_config settings ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/variants/karis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79176/comment/805aa219_5d676025 : PS1, Line 32: THERMAL_SETTING_1 > How about ```THERMAL_SOLUTION_1```? I mean to ask what the thermal solution refers to ? like socketed board or soldered down SoC ? -- To view, visit https://review.coreboot.org/c/coreboot/+/79176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a8a68b2a6c42045d541690ddb111fbf617b45d6 Gerrit-Change-Number: 79176 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 08:26:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/rex/var/karis: Enable audio BT offload
by Tyler Wang (Code Review) 21 Nov '23

21 Nov '23

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79210?usp=email ) Change subject: mb/google/rex/var/karis: Enable audio BT offload ...................................................................... mb/google/rex/var/karis: Enable audio BT offload BUG=b:312099281 TEST=none Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/fw_config.c M src/mainboard/google/rex/variants/karis/variant.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/79210/1 diff --git a/src/mainboard/google/rex/variants/karis/fw_config.c b/src/mainboard/google/rex/variants/karis/fw_config.c index 7211d8a..4209407 100644 --- a/src/mainboard/google/rex/variants/karis/fw_config.c +++ b/src/mainboard/google/rex/variants/karis/fw_config.c @@ -8,6 +8,25 @@ #define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) +static const struct pad_config bt_i2s_enable_pads[] = { + /* GPP_V30 : [] ==> BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF2), + /* GPP_V31 : [] ==> BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF2), + /* GPP_V32 : [] ==> BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF2), + /* GPP_V33 : [] ==> BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF2), + /* GPP_V34 : [] ==> SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + /* GPP_V35 : [] ==> SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + /* GPP_V36 : [] ==> SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + /* GPP_V37 : [] ==> SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), +}; + static const struct pad_config fp_disable_pads[] = { /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_NC(GPP_B11, NONE), @@ -42,4 +61,8 @@ printk(BIOS_INFO, "Configure GPIOs for no FP module.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads); } + if (fw_config_probe(FW_CONFIG(AUDIO, ALC5650_NO_AMP_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads); + } } diff --git a/src/mainboard/google/rex/variants/karis/variant.c b/src/mainboard/google/rex/variants/karis/variant.c index 308eea6..ecfd4f8 100644 --- a/src/mainboard/google/rex/variants/karis/variant.c +++ b/src/mainboard/google/rex/variants/karis/variant.c @@ -9,3 +9,9 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_TYPE)); } + +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(AUDIO, ALC5650_NO_AMP_I2S))) + config->cnvi_bt_audio_offload = true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79210?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4 Gerrit-Change-Number: 79210 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Deepti Deshatty. Hello Deepti Deshatty, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79209?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... mtlrvp: add SI_EC region in flash map MTLRVP booted with microchip EC1723 which do not have an internal flash memory similar to the windows RVP designs. Using MEC1723 for chrome helps in RVP BOM convergence. EC, AP shares the same external SPI flash. EC ROM will download the EC firmware from external SPI to internal SRAM for execution. This patch adds SI_EC region similar to windows. Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/chromeos.fmd 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part
by Leo Chou (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held, YH Lin. Leo Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79184?usp=email ) Change subject: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Gerrit-Change-Number: 79184 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 07:06:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Deepti Deshatty. Hello Deepti Deshatty, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/79209?usp=email to review the following change. Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... mtlrvp: add SI_EC region in flash map MTLRVP booted with microchip EC1723 which do not have an internal flash memory similar to the windows RVP designs. Using MEC1723 for chrome helps in RVP BOM convergence. EC, AP shares the same external SPI flash. EC ROM will download the EC firmware from external SPI to internal SRAM for execution. This patch adds SI_EC region similar to windows. Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/chromeos.fmd 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index f225aa5..a4e5e1a 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -99,7 +99,8 @@ choice prompt "ON BOARD EC" default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P - default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP + default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC + default MTL_CHROME_EC_SHARED_SPI if BOARD_INTEL_MTLRVP_P_MCHP help This option allows you to select the on board EC to use. Select whether the board has Intel EC or/and Chrome EC @@ -111,6 +112,14 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_BOARDID +config MTL_CHROME_EC_SHARED_SPI + bool "Chrome EC with external Shared SPI flash" + select EC_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select MAINBOARD_USES_IFD_EC_REGION + config MTL_INTEL_EC bool "Intel EC" select EC_ACPI @@ -118,7 +127,7 @@ config VBOOT select VBOOT_LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC + select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC || MTL_CHROME_EC_SHARED_SPI config UART_FOR_CONSOLE int diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index a5bc538..d49ac0c7 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -1,6 +1,7 @@ FLASH 32M { SI_ALL 9M { SI_DESC 16K + SI_EC 512K SI_ME } SI_BIOS 23M { -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part
by Leo Chou (Code Review) 21 Nov '23

21 Nov '23

Leo Chou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79208?usp=email ) Change subject: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/79208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644da24607d34852c1054cb18768bad021dcc45a Gerrit-Change-Number: 79208 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part
by Leo Chou (Code Review) 21 Nov '23

21 Nov '23

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79208?usp=email ) Change subject: mb/google/brya/var/taeko: Generate SPD ID for new supported memory part ...................................................................... mb/google/brya/var/taeko: Generate SPD ID for new supported memory part Add taeko new supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4UBE3D4AB-MGCL 2. Micron MT53E1G32D2NP-046 WT:B BUG=b:312363368 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: I644da24607d34852c1054cb18768bad021dcc45a --- M src/mainboard/google/brya/variants/taeko/memory/Makefile.inc M src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt 3 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/79208/1 diff --git a/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc b/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc index 2ac3e32..458f555 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/taeko/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory/ src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt index fda303c..4787674 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/taeko/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/taeko/memory/ src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) @@ -10,3 +10,5 @@ MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AB-MGCL 0 (0000) H54G46CYRBX267 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) +MT53E1G32D2NP-046 WT:B 1 (0001) diff --git a/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt index dd80fc8..6f7967f 100644 --- a/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/taeko/memory/mem_parts_used.txt @@ -4,3 +4,5 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AB-MGCL H54G46CYRBX267 +K4UBE3D4AB-MGCL +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/79208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644da24607d34852c1054cb18768bad021dcc45a Gerrit-Change-Number: 79208 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023