coreboot-gerrit November 2023

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79167?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Gerrit-Change-Number: 79167 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:48:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79116?usp=email ) Change subject: nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guards ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Gerrit-Change-Number: 79116 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:48:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79115?usp=email ) Change subject: nb/intel/sandybridge: assign PCIe root port ops in chipset devicetree ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I357aa0b27fcc73814f60d0aa5b5141add8917825 Gerrit-Change-Number: 79115 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:47:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x/pch: Add method to identify PCH
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79145?usp=email ) Change subject: sb/intel/bd82x6x/pch: Add method to identify PCH ...................................................................... Patch Set 2: (4 comments) File src/southbridge/intel/bd82x6x/pch.c: https://review.coreboot.org/c/coreboot/+/79145/comment/ff4f1363_04f3f3f8 : PS2, Line 47: {0x1C43, 0x1C47, 0x1C49, 0x1C4B, 0x1C4F, 0x1C41, : 0x1C4D, 0x1E42, 0x1E55, 0x1E5D, 0x1E57, 0x1E58, : 0x1E59, 0x1E43, 0x1E56}; nit: Format these values in 2 lines for CPT/PPT? I also sorted the IDs numerically. ``` const u16 devids[] = { 0x1C41, 0x1C43, 0x1C47, 0x1C49, 0x1C4B, 0x1C4D, 0x1C4F, 0x1E42, 0x1E43, 0x1E55, 0x1E56, 0x1E57, 0x1E58, 0x1E59, 0x1E5D, }; ``` https://review.coreboot.org/c/coreboot/+/79145/comment/a62fadd3_28070fb5 : PS2, Line 52: 1 true https://review.coreboot.org/c/coreboot/+/79145/comment/d41f3aee_c2b1e88e : PS2, Line 53: 0 false https://review.coreboot.org/c/coreboot/+/79145/comment/177be8e6_1c8937c4 : PS2, Line 14: int pch_silicon_revision(void) : { : static int pch_revision_id = -1; : : #ifdef __SIMPLE_DEVICE__ : pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); : #else : struct device *dev = pcidev_on_root(0x1f, 0); : #endif : : if (pch_revision_id < 0) : pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); : return pch_revision_id; : } : : int pch_silicon_type(void) : { : static int pch_type = -1; : : #ifdef __SIMPLE_DEVICE__ : pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); : #else : struct device *dev = pcidev_on_root(0x1f, 0); : #endif : : if (pch_type < 0) : pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); : return pch_type; : } : : bool pch_is_mobile(void) : { : const u16 devid = pci_s_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); : const u16 devids[] = {0x1C43, 0x1C47, 0x1C49, 0x1C4B, 0x1C4F, 0x1C41, : 0x1C4D, 0x1E42, 0x1E55, 0x1E5D, 0x1E57, 0x1E58, : 0x1E59, 0x1E43, 0x1E56}; : for (size_t i = 0; i < ARRAY_SIZE(devids); i++) : if (devid == devids[i]) : return 1; : return 0; : } Maybe these functions should be in a separate file, so that `__SIMPLE_DEVICE__` is not a problem? -- To view, visit https://review.coreboot.org/c/coreboot/+/79145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Gerrit-Change-Number: 79145 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:46:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Patrick Rudolph, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78827?usp=email ) Change subject: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting ...................................................................... Patch Set 8: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78827/comment/08cecbe3_e16a89c6 : PS8, Line 15: Tested: Lenovo X220 still boots. Isn't this a laptop? This change should be a no-op for mobile PCHs. File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/c/coreboot/+/78827/comment/d0419463_625608b7 : PS8, Line 28: if (!pch_is_mobile() && portmap[i].current == 0) { We may want to skip complaining about disabled ports. If we still want to make sure the current index is not reserved, we need to fall back to any other value that is supported. https://review.coreboot.org/c/coreboot/+/78827/comment/9cc36c53_dd25ac08 : PS8, Line 29: Consult the OEM for correct settings As most Sandy/Ivy Bridge ports are retrofits (people add coreboot support without OEM involvement), I think the following would be much more helpful: ``` /* * Note for developers: You can fix this by re-running autoport on * vendor firmware and then updating portmap currents accordingly. * If that is not possible, another option is to choose a non-zero * current setting. In either case, please test all the USB ports. */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Gerrit-Change-Number: 78827 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:40:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/hp/280_g2: Restore comments documenting root port devices
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79153?usp=email ) Change subject: mb/hp/280_g2: Restore comments documenting root port devices ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79153/comment/7402e967_90cd0cbc : PS2, Line 9: to make it using the chipset nit: Did you mean: > to make use of the chipset devicetree Patchset: PS2: Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/79153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I178cb472a8f40baaccc30514689bda2730dfa9dc Gerrit-Change-Number: 79153 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mtlrvp: define new config for chrome ec
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Deepti Deshatty, Deepti Deshatty. Hello Deepti Deshatty, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79211?usp=email to look at the new patch set (#2). Change subject: mtlrvp: define new config for chrome ec ...................................................................... mtlrvp: define new config for chrome ec Add new config MTL_CHROME_EC_SHARED_SPI for chrome EC's using external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/79211/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mtlrvp: define new config for chrome ec
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79211?usp=email ) Change subject: mtlrvp: define new config for chrome ec ...................................................................... mtlrvp: define new config for chrome ec Add new config MTL_CHROME_EC_SHARED_SPI for chrome EC's using external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/79211/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 26faf91..5080e86 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -102,7 +102,8 @@ choice prompt "ON BOARD EC" default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P - default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default MTL_CHROME_EC_SHARED_SPI if BOARD_INTEL_MTLRVP_P_MCHP help This option allows you to select the on board EC to use. Select whether the board has Intel EC or/and Chrome EC @@ -114,6 +115,14 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_BOARDID +config MTL_CHROME_EC_SHARED_SPI + bool "Chrome EC with external Shared SPI flash" + select EC_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select MAINBOARD_USES_IFD_EC_REGION + config MTL_INTEL_EC bool "Intel EC" select EC_ACPI @@ -121,7 +130,7 @@ config VBOOT select VBOOT_LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC + select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC || MTL_CHROME_EC_SHARED_SPI config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map
by Deepti Deshatty (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Krishna P Bhat D. Hello Balaji Manigandan, Deepti Deshatty, Krishna P Bhat D, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79209?usp=email to look at the new patch set (#4). Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... mtlrvp: add SI_EC region in flash map MTLRVP booted with microchip EC1723 which do not have an internal flash memory similar to the windows RVP designs. Using MEC1723 for chrome helps in RVP BOM convergence. EC, AP shares the same external SPI flash. EC ROM will download the EC firmware from external SPI to internal SRAM for execution. This patch adds SI_EC region similar to windows. BUG=b:289783489 TEST=build "emerge-rex coreboot chromeos-bootimage" is successful Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/chromeos.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 4 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex: Enable FSP logo rendering for all Rex variants
by Eric Lai (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79175?usp=email ) Change subject: mb/google/rex: Enable FSP logo rendering for all Rex variants ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73d82e16f70ffdc8cb168506c86d9c4e9a92c38d Gerrit-Change-Number: 79175 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 08:50:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2023