coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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3037 discussions

[XS] Change in coreboot[main]: Update fsp submodule to upstream master
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Lean Sheng Tan, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79004?usp=email ) Change subject: Update fsp submodule to upstream master ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fe65d830061c93ceac549dc7f41e7a98646a0a3 Gerrit-Change-Number: 79004 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 11:20:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mtlrvp: define new config for chrome ec
by Paul Menzel (Code Review) 21 Nov '23

21 Nov '23

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[XS] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map
by Paul Menzel (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Krishna P Bhat D. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79209?usp=email ) Change subject: mtlrvp: add SI_EC region in flash map ...................................................................... Patch Set 4: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79209/comment/a2f4aacf_cbc6496a : PS4, Line 7: mtlrvp Please extend the prefix: mb/intel/mtlrvp. https://review.coreboot.org/c/coreboot/+/79209/comment/7a841b0b_5d50f4a8 : PS4, Line 7: add SI_EC region in flash map Add 512 kB SI_EC FMAP region fo MEC1723 https://review.coreboot.org/c/coreboot/+/79209/comment/633fdf77_78f66864 : PS4, Line 9: MTLRVP Use “MTLRVP for Chrome OS”? https://review.coreboot.org/c/coreboot/+/79209/comment/c8b20d44_0c670c41 : PS4, Line 9: do does https://review.coreboot.org/c/coreboot/+/79209/comment/7fb6f649_b1981ba7 : PS4, Line 9: microchip Microship https://review.coreboot.org/c/coreboot/+/79209/comment/5155ae22_c3247976 : PS4, Line 9: booted with “booted with”? What do you mean? https://review.coreboot.org/c/coreboot/+/79209/comment/e6c38cc5_2fd2000f : PS4, Line 11: Using MEC1723 for chrome helps in RVP BOM convergence. Sorry, I do not understand what you mean. https://review.coreboot.org/c/coreboot/+/79209/comment/a6adc9c4_1a5218b4 : PS4, Line 16: This patch adds SI_EC region similar to windows. “This patch adds” is redundant in a commit message. Maybe use imperative mood: > So, add a 512 kB SI_EC region to the flash map similar to RVPs for Microsoft Windows. Do the boards for Microsoft Windows also use coreboot based firmware? https://review.coreboot.org/c/coreboot/+/79209/comment/8ca58ebd_1078c81d : PS4, Line 16: This patch adds SI_EC region similar to windows. Please add a blank line above to separate paragraphs. https://review.coreboot.org/c/coreboot/+/79209/comment/a1937276_181c1167 : PS4, Line 9: MTLRVP booted with microchip EC1723 which do not have an : internal flash memory similar to the windows RVP designs. : Using MEC1723 for chrome helps in RVP BOM convergence. : : EC, AP shares the same external SPI flash. EC ROM will : download the EC firmware from external SPI to internal SRAM : for execution. : This patch adds SI_EC region similar to windows. Please reflow to use all of the allowed text width of 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/79209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Gerrit-Change-Number: 79209 Gerrit-PatchSet: 4 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 11:18:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x/pch: Add method to identify PCH
by Paul Menzel (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79145?usp=email ) Change subject: sb/intel/bd82x6x/pch: Add method to identify PCH ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Gerrit-Change-Number: 79145 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 11:12:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Keith Hui, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email ) Change subject: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Following this line of thought, have I gone too far with sandybridge? […] Hmmm, do you have a link to these sandybridge changes? I'd like to see these review comments -- To view, visit https://review.coreboot.org/c/coreboot/+/79025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Gerrit-Change-Number: 79025 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:55:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Write MSRs in scope package only once
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78607?usp=email ) Change subject: cpu/intel/model_206ax: Write MSRs in scope package only once ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78607/comment/3a8b720c_9125c9b8 : PS6, Line 14: TEST: Lenovo X220 still boots. Would've been nice to check if the affected MSRs, when read from different cores/threads, still return the same values. -- To view, visit https://review.coreboot.org/c/coreboot/+/78607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5d62d782466d2796c1df6015d43c0fbf9d031 Gerrit-Change-Number: 78607 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:53:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79171?usp=email ) Change subject: sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Gerrit-Change-Number: 79171 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:49:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79170?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Gerrit-Change-Number: 79170 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:49:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79169?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Gerrit-Change-Number: 79169 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:48:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree
by Angel Pons (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79168?usp=email ) Change subject: sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Gerrit-Change-Number: 79168 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 21 Nov 2023 10:48:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2023