coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[S] Change in libgfxinit[main]: [EXPERIMENTAL] Begin Meteor Lake integration
by Jérémy Compostella (Code Review) 21 Nov '23

21 Nov '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/libgfxinit/+/72714?usp=email ) Change subject: [EXPERIMENTAL] Begin Meteor Lake integration ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/libgfxinit/+/72714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: main Gerrit-Change-Id: I890b32497af8edc82dd533e5c556e30ec50d0d04 Gerrit-Change-Number: 72714 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life
by Jérémy Compostella (Code Review) 21 Nov '23

21 Nov '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/72715?usp=email ) Change subject: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/72715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4c37077b3b3032c861f96231435fcebc7ef36ff Gerrit-Change-Number: 72715 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: [EXPERIMENTAL] soc/intel/meteorlake: Enable ramstage libgfxinit
by Jérémy Compostella (Code Review) 21 Nov '23

21 Nov '23

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/72731?usp=email ) Change subject: [EXPERIMENTAL] soc/intel/meteorlake: Enable ramstage libgfxinit ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/72731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib366eb85f13b53d4768eace32c0486e6cd476fec Gerrit-Change-Number: 72731 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
by Karthik Ramasubramanian (Code Review) 21 Nov '23

21 Nov '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79155?usp=email ) Change subject: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable ...................................................................... soc/amd/common/psp_verstage: Make SPI ROM mapping configurable Earlier entire SPI ROM was mapped to memory. With limited TLB resources in PSP, this approach hit the limit on systems using 32 MiB SPI ROM. Therefore regions in SPI ROM were mapped on need basis. This works well on Mendocino and Phoenix SoCs. But unfortunately this causes boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM and enable it in Cezanne SoC. For other SoCs, keep the configuration disabled so that only the required SPI ROM region is mapped. BUG=b:309690716 TEST=Build and boot to OS in both Dewatt and Skyrim. Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/boot_dev.c M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/psp_verstage.c 4 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79155/1 diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index dc6ea1c..118ef61 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -43,3 +43,11 @@ help This configuration indicates whether the PSP Verstage stack is mapped to a virtual address space. This has been the case so far only in Picasso SoC. + +config PSP_VERSTAGE_MAP_ENTIRE_SPIROM + bool + default y if SOC_AMD_CEZANNE + default n + help + This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. + This is required only in Cezanne SoC at the moment. diff --git a/src/soc/amd/common/psp_verstage/boot_dev.c b/src/soc/amd/common/psp_verstage/boot_dev.c index c129479..e3cd512 100644 --- a/src/soc/amd/common/psp_verstage/boot_dev.c +++ b/src/soc/amd/common/psp_verstage/boot_dev.c @@ -20,6 +20,8 @@ uint32_t ret; mdev = container_of(rd, __typeof__(*mdev), rdev); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return &(mdev->base[offset]); if (mdev->base) { if ((ret = svc_map_spi_rom(&mdev->base[offset], size, (void **)&mapping)) @@ -37,9 +39,12 @@ { uint32_t ret; - active_map_count--; - if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) - printk(BIOS_ERR, "Failed(%d) to unmap SPI ROM mapping %p\n", ret, mapping); + if (!CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) { + active_map_count--; + if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) + printk(BIOS_ERR, "Failed(%d) to unmap SPI ROM mapping %p\n", + ret, mapping); + } return 0; } diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index 0517545..0d5ee7c 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -92,12 +92,20 @@ void *map_spi_rom(void) { + uintptr_t *addr = NULL; struct spirom_info spi = {0}; if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); - return spi.SpiBiosSmnBase; + if (!CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return spi.SpiBiosSmnBase; + + if (spi.SpiBiosSmnBase != 0) + if (svc_map_spi_rom(spi.SpiBiosSmnBase, CONFIG_ROM_SIZE, (void **)&addr)) + printk(BIOS_DEBUG, "Error mapping SPI ROM to address.\n"); + + return addr; } static uint32_t map_fch_devices(void) diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 87d126f2..fd546ce 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -235,6 +235,7 @@ uint32_t retval; struct vb2_context *ctx = NULL; uint32_t bootmode; + void *boot_dev_base; /* * Do not use printk() before console_init() @@ -350,7 +351,15 @@ if (retval) reboot_into_recovery(ctx, retval); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) { + boot_dev_base = rdev_mmap_full(boot_device_ro()); + if (boot_dev_base) { + if (svc_unmap_spi_rom((void *)boot_dev_base)) + printk(BIOS_ERR, "Error unmapping SPI rom\n"); + } + } assert(!boot_dev_get_active_map_count()); + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); -- To view, visit https://review.coreboot.org/c/coreboot/+/79155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Gerrit-Change-Number: 79155 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
by Karthik Ramasubramanian (Code Review) 21 Nov '23

21 Nov '23

Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79154?usp=email ) Change subject: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/79154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090928d35516efe8264c7f1b4ac474dca3c53588 Gerrit-Change-Number: 79154 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable
by Karthik Ramasubramanian (Code Review) 21 Nov '23

21 Nov '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79154?usp=email ) Change subject: soc/amd/common/psp_verstage: Make SPI ROM mapping configurable ...................................................................... soc/amd/common/psp_verstage: Make SPI ROM mapping configurable Earlier entire SPI ROM was mapped to memory. With limited TLB resources in PSP, this approach hit the limit on systems using 32 MiB SPI ROM. Therefore regions in SPI ROM were mapped on need basis. This works well on Mendocino and Phoenix SoCs. But unfortunately this causes boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM and enable it in Cezanne SoC. For other SoCs, keep the configuration disabled so that only the required SPI ROM region is mapped. BUG=b:309690716 TEST=Build and boot to OS in both Dewatt and Skyrim. Change-Id: I090928d35516efe8264c7f1b4ac474dca3c53588 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/boot_dev.c M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/common/psp_verstage/psp_verstage.c 4 files changed, 34 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79154/1 diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index dc6ea1c..118ef61 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -43,3 +43,11 @@ help This configuration indicates whether the PSP Verstage stack is mapped to a virtual address space. This has been the case so far only in Picasso SoC. + +config PSP_VERSTAGE_MAP_ENTIRE_SPIROM + bool + default y if SOC_AMD_CEZANNE + default n + help + This configuration indicates whether PSP Verstage needs to map the entire SPI ROM. + This is required only in Cezanne SoC at the moment. diff --git a/src/soc/amd/common/psp_verstage/boot_dev.c b/src/soc/amd/common/psp_verstage/boot_dev.c index c129479..e3cd512 100644 --- a/src/soc/amd/common/psp_verstage/boot_dev.c +++ b/src/soc/amd/common/psp_verstage/boot_dev.c @@ -20,6 +20,8 @@ uint32_t ret; mdev = container_of(rd, __typeof__(*mdev), rdev); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return &(mdev->base[offset]); if (mdev->base) { if ((ret = svc_map_spi_rom(&mdev->base[offset], size, (void **)&mapping)) @@ -37,9 +39,12 @@ { uint32_t ret; - active_map_count--; - if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) - printk(BIOS_ERR, "Failed(%d) to unmap SPI ROM mapping %p\n", ret, mapping); + if (!CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) { + active_map_count--; + if ((ret = svc_unmap_spi_rom(mapping)) != BL_OK) + printk(BIOS_ERR, "Failed(%d) to unmap SPI ROM mapping %p\n", + ret, mapping); + } return 0; } diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index 0517545..0d5ee7c 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -92,12 +92,20 @@ void *map_spi_rom(void) { + uintptr_t *addr = NULL; struct spirom_info spi = {0}; if (svc_get_spi_rom_info(&spi)) printk(BIOS_DEBUG, "Error getting SPI ROM info.\n"); - return spi.SpiBiosSmnBase; + if (!CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) + return spi.SpiBiosSmnBase; + + if (spi.SpiBiosSmnBase != 0) + if (svc_map_spi_rom(spi.SpiBiosSmnBase, CONFIG_ROM_SIZE, (void **)&addr)) + printk(BIOS_DEBUG, "Error mapping SPI ROM to address.\n"); + + return addr; } static uint32_t map_fch_devices(void) diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 87d126f2..fd546ce 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -235,6 +235,7 @@ uint32_t retval; struct vb2_context *ctx = NULL; uint32_t bootmode; + void *boot_dev_base; /* * Do not use printk() before console_init() @@ -350,7 +351,15 @@ if (retval) reboot_into_recovery(ctx, retval); + if (CONFIG(PSP_VERSTAGE_MAP_ENTIRE_SPIROM)) { + boot_dev_base = rdev_mmap_full(boot_device_ro()); + if (boot_dev_base) { + if (svc_unmap_spi_rom((void *)boot_dev_base)) + printk(BIOS_ERR, "Error unmapping SPI rom\n"); + } + } assert(!boot_dev_get_active_map_count()); + post_code(POSTCODE_UNMAP_FCH_DEVICES); unmap_fch_devices(); -- To view, visit https://review.coreboot.org/c/coreboot/+/79154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090928d35516efe8264c7f1b4ac474dca3c53588 Gerrit-Change-Number: 79154 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex: Set EPP to 45%
by Paul Menzel (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Subrata Banik, Tarun. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79204?usp=email ) Change subject: mb/google/rex: Set EPP to 45% ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79204/comment/0a1cd502_0934ba1f : PS1, Line 9: This updates energy performance preference value to 45%. Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/79204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia420e8b6bed252a8a1f59d36a4a71c2b8ec9524e Gerrit-Change-Number: 79204 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 20 Nov 2023 23:06:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Disable un-used C1 port for DB_NONE
by Paul Menzel (Code Review) 21 Nov '23

21 Nov '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Robert Chen, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79173?usp=email ) Change subject: mb/google/nissa/var/quandiso: Disable un-used C1 port for DB_NONE ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79173/comment/c5d608b5_cc78f283 : PS3, Line 7: DB_NONE What does DB mean? https://review.coreboot.org/c/coreboot/+/79173/comment/a324074a_70c9c9e2 : PS3, Line 11: Please document the schematic version. File src/mainboard/google/brya/variants/quandiso/fw_config.c: https://review.coreboot.org/c/coreboot/+/79173/comment/9fc93132_c5c0a552 : PS3, Line 96: printk(BIOS_INFO, "Disable USBC1 AUX Pins.\n"); Info level messages should be more elaborate. Maybe add: … according to fw_config. https://review.coreboot.org/c/coreboot/+/79173/comment/7dd88d50_6a4c5091 : PS3, Line 96: Pins pins -- To view, visit https://review.coreboot.org/c/coreboot/+/79173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Gerrit-Change-Number: 79173 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 20 Nov 2023 23:05:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/ipmi to lib: Fix misspellings & capitalization issues
by Jérémy Compostella (Code Review) 20 Nov '23

20 Nov '23

Attention is currently required from: Alexander Couzens, Christian Walter, Martin L Roth, Paul Menzel. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77637?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/ipmi to lib: Fix misspellings & capitalization issues ...................................................................... Patch Set 2: (1 comment) File src/include/nhlt.h: https://review.coreboot.org/c/coreboot/+/77637/comment/87c7f0f4_47c38e2b : PS2, Line 30: specially wasn't the intended word `specifically` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/77637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I926ec4c1c00339209ef656995031026935e52558 Gerrit-Change-Number: 77637 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Mon, 20 Nov 2023 22:58:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: acpi: Optimize enum acpi_tables layout
by Felix Singer (Code Review) 20 Nov '23

20 Nov '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79099?usp=email ) Change subject: acpi: Optimize enum acpi_tables layout ...................................................................... acpi: Optimize enum acpi_tables layout Arrange ACPI table enum in a vertical and alphabetized format. This change aims to reduce conflicts between patches. Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79099 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/acpi/acpi.h 1 file changed, 32 insertions(+), 5 deletions(-) Approvals: Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, approved Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fe7e5fd..9a9a66d 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -75,12 +75,39 @@ }; enum acpi_tables { - /* Tables defined by ACPI and used by coreboot */ - BERT, CEDT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, - MADT, MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, - SPCR, GTDT, + /* Alphabetic list of Tables defined by ACPI and used by coreboot */ + BERT, /* Boot Error Record Table */ + CEDT, /* CXL Early Discovery Table */ + DBG2, /* Debug Port Table 2 */ + DMAR, /* DMA Remapping Table */ + DSDT, /* Differentiated System Description Table */ + ECDT, /* Embedded Controller Boot Resources Table */ + EINJ, /* Error Injection Table */ + FACS, /* Firmware ACPI Control Structure */ + FADT, /* Fixed ACPI Description Table */ + GTDT, /* Generic Timer Description Table */ + HEST, /* Hardware Error Source Table */ + HMAT, /* Heterogeneous Memory Attribute Table */ + HPET, /* High Precision Event Timer Table */ + IVRS, /* I/O Virtualization Reporting Structure */ + LPIT, /* Low Power Idle Table */ + MADT, /* Multiple APIC Description Table */ + MCFG, /* PCI Express Memory Mapped Configuration */ + RSDP, /* Root System Description Pointer */ + RSDT, /* Root System Description Table */ + SLIT, /* System Locality Distance Information Table */ + SPCR, /* Serial Port Console Redirection Table */ + SRAT, /* System Resource Affinity Table */ + SSDT, /* Secondary System Description Table */ + TCPA, /* Trusted Computing Platform Alliance Table */ + TPM2, /* Trusted Platform Module 2.0 Table */ + XSDT, /* Extended System Description Table */ + /* Additional proprietary tables used by coreboot */ - VFCT, NHLT, SPMI, CRAT + CRAT, /* Component Resource Attribute Table */ + NHLT, /* Non HD audio Link Table */ + SPMI, /* Server Platform Management Interface table */ + VFCT /* VBIOS Fetch Table */ }; /* RSDP (Root System Description Pointer) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I192339df771d6a3ae67358fe46334fe2b216b974 Gerrit-Change-Number: 79099 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2023