coreboot-gerrit January 2023

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[S] Change in coreboot[master]: soc/intel/common: Move SGX supported API to cpulib
by Sridhar Siricilla (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Pratikkumar V Prajapati. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71116 ) Change subject: soc/intel/common: Move SGX supported API to cpulib ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Gerrit-Change-Number: 71116 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 03:54:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: WIP: mb/hp/t620: Add new board HP T620
by Damien Zammit (Code Review) 02 Jan '23

02 Jan '23

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[L] Change in coreboot[master]: WIP: mb/hp/t620: Add new board HP T620
by Damien Zammit (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Martin L Roth. Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71609 ) Change subject: WIP: mb/hp/t620: Add new board HP T620 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This is the board commit, last in patch series of bringing back fam16kb. I'm not sure why the MP initialization failed. log says: ``` [INFO ] CPU: AMD GX-217GA SOC with Radeon(tm) HD Graphics . [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 1 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [ERROR] Not all APs checked in: -1/1. [DEBUG] -1/1 eventually checked in? [ERROR] MP initialization failure. [DEBUG] CPU_CLUSTER: 0 init finished in 1523 msecs ... ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/71609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Gerrit-Change-Number: 71609 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 02:47:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelp2m/patform/sunrise: Add unit tests
by ron minnich (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Martin L Roth, Maxim Polyakov, David Hendricks. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67132 ) Change subject: intelp2m/patform/sunrise: Add unit tests ...................................................................... Patch Set 14: (1 comment) File util/intelp2m/Makefile: https://review.coreboot.org/c/coreboot/+/67132/comment/2c8cbb94_b3711dfe PS14, Line 9: go build -v -o $(PROJECT_NAME) I find myself wondering why you have the -o here. In my experience, a go build -v would build ./intelp2m, because we're in that directory? -- To view, visit https://review.coreboot.org/c/coreboot/+/67132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15c7483f120a330849d4bad036427be205b0911c Gerrit-Change-Number: 67132 Gerrit-PatchSet: 14 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 02:22:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelp2m/patform/sunrise: Add unit tests
by ron minnich (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Martin L Roth, Maxim Polyakov, David Hendricks. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67132 ) Change subject: intelp2m/patform/sunrise: Add unit tests ...................................................................... Patch Set 14: Code-Review+2 (2 comments) Patchset: PS14: looks fine, I did have one nit, which you might want to look at. File util/intelp2m/platforms/test/suite.go: https://review.coreboot.org/c/coreboot/+/67132/comment/dc2e3535_b94f3379 PS14, Line 47: err = fmt.Errorf(format, "LONG", m.Long, actually) in code like this it's a bit more idiomatic to do this: if condition { return error } if condition { return error } return nil no need to declare the error and it's a bit more like other code. -- To view, visit https://review.coreboot.org/c/coreboot/+/67132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15c7483f120a330849d4bad036427be205b0911c Gerrit-Change-Number: 67132 Gerrit-PatchSet: 14 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 00:59:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/topology: Add code to fill in topology on struct path
by Elyes Haouas (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Shuming Chu (Shuming), Arthur Heymans, Kyösti Mälkki, TangYiwei. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69222 ) Change subject: cpu/x86/topology: Add code to fill in topology on struct path ...................................................................... Patch Set 15: (5 comments) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/69222/comment/eed9e146_442542a3 PS15, Line 3: include <assert.h> If I'm not wrong, <assert.h> is not used. https://review.coreboot.org/c/coreboot/+/69222/comment/fda36e2d_598a1cf0 PS15, Line 4: <arch/cpu.h> I'd include <cpu/cpu.h> instead https://review.coreboot.org/c/coreboot/+/69222/comment/30178c8b_486d150d PS15, Line 26: enum cb_err maybe include <types.h> https://review.coreboot.org/c/coreboot/+/69222/comment/83762803_a40a9bef PS15, Line 34: Cpu CPU ? File src/include/cpu/x86/topology.h: https://review.coreboot.org/c/coreboot/+/69222/comment/f6270fad_8af866fc PS15, Line 10: device include <device/device.h> ? -- To view, visit https://review.coreboot.org/c/coreboot/+/69222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Gerrit-Change-Number: 69222 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Sun, 01 Jan 2023 23:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/haswell: Specify supported memory type
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71583 ) Change subject: nb/intel/haswell: Specify supported memory type ...................................................................... Patch Set 4: (2 comments) File src/northbridge/intel/haswell/Kconfig: https://review.coreboot.org/c/coreboot/+/71583/comment/79e21147_0e4b0588 PS2, Line 6: if NORTHBRIDGE_INTEL_HASWELL : : config NORTHBRIDGE_SPECIFIC_OPTIONS : def_bool y > Seems to be unrelated Done https://review.coreboot.org/c/coreboot/+/71583/comment/a3a26b15_b309a55a PS2, Line 18: select USE_DDR4 > Haswell does *not* support DDR4. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Gerrit-Change-Number: 71583 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 22:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/haswell: Specify supported memory type
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71583 to look at the new patch set (#3). Change subject: nb/intel/haswell: Specify supported memory type ...................................................................... nb/intel/haswell: Specify supported memory type Also add 'config NORTHBRIDGE_SPECIFIC_OPTIONS' section to reduce difference with the other Kconfig files. Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/Kconfig 1 file changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/71583/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Gerrit-Change-Number: 71583 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/ironlake: Specify supported memory type
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71584 ) Change subject: nb/intel/ironlake: Specify supported memory type ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71584/comment/bcccc93b_3e36df52 PS1, Line 7: intel/ironlake: Specify supported memory type > `nb/intel/ironlake` Done File src/northbridge/intel/ironlake/Kconfig: https://review.coreboot.org/c/coreboot/+/71584/comment/ae8edb5c_e6273a27 PS1, Line 6: if NORTHBRIDGE_INTEL_IRONLAKE : : config NORTHBRIDGE_SPECIFIC_OPTIONS : def_bool y > Seems unrelated Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Gerrit-Change-Number: 71584 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 22:47:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/ironlake: Specify supported memory type
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71584 to look at the new patch set (#2). Change subject: nb/intel/ironlake: Specify supported memory type ...................................................................... nb/intel/ironlake: Specify supported memory type Also add 'config NORTHBRIDGE_SPECIFIC_OPTIONS' section to reduce difference with the other Kconfig files. Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/Kconfig 1 file changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/71584/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Gerrit-Change-Number: 71584 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2023