coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: spd.h: Move enum ddr2_module_type to ddr2.h
by Jakub Czapiga (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Reka Norman, Elyes Haouas. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71546 ) Change subject: spd.h: Move enum ddr2_module_type to ddr2.h ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Reka, can you review this and next patch? I see you are maintaining SPD Utilities, so you know more about this stuff than I do. -- To view, visit https://review.coreboot.org/c/coreboot/+/71546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Gerrit-Change-Number: 71546 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:31:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jeff Daly, Vanessa Eusebio, Kyösti Mälkki, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71611 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71611/comment/a4c32b3b_bf6c7e49 PS1, Line 10: Tested how? -- To view, visit https://review.coreboot.org/c/coreboot/+/71611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ecd6b1bd0bdf1c3c1e32978a9048a22b294b15 Gerrit-Change-Number: 71611 Gerrit-PatchSet: 1 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:15:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi/Kconfig: Move unused ACPI_EINJ config option to vendorcode
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Lance Zhao, Nico Huber, David Hendricks, Tim Wawrzynczak, Eric Lai, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68593 ) Change subject: acpi/Kconfig: Move unused ACPI_EINJ config option to vendorcode ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68593/comment/48eeff56_29cc55f2 PS4, Line 8: It’d be great if you summarized the discussion in the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/68593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222478572a9e5efadd6719a164558833298e4c99 Gerrit-Change-Number: 68593 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:15:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Update USB2-C1 mapping
by 9elements QA (Code Review) 02 Jan '23

02 Jan '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70426 ) Change subject: mb/google/rex: Update USB2-C1 mapping ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/142975 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/142974 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/142973 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142972 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/142971 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/142970 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/142969 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/142968 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/142967 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/142966 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142965 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/142964 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/142963 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/142962 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/70426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Gerrit-Change-Number: 70426 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 10:58:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66190/comment/bc6aad40_9a877e91 PS22, Line 13: TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS > What memory vendor/model exactly? Updated in the commit description: Memory - x32 DDR5 SBS SODIMM 1DPC Vendor/Model - SK-Hynix/HMCG66MEBSA092N File src/mainboard/intel/mtlrvp/romstage.c: https://review.coreboot.org/c/coreboot/+/66190/comment/f2faa7a4_8e6c11ce PS22, Line 45: > Please remove the blank line at the end of the file. This is seen only during the review of the file. This file doesn't contain any blank line at the end of file in real. File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c: https://review.coreboot.org/c/coreboot/+/66190/comment/4e6670b7_144175e1 PS22, Line 12: 100ohm > 100 Ohm Done https://review.coreboot.org/c/coreboot/+/66190/comment/0040767b_eda18c22 PS22, Line 16: .targets = {50, 30, 30, 30, 25}, > Please document the datasheet, these are from. overriding rcomp target values isn't required as values gets configured through FSP. Below is the values configured as part of FSP, [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 60 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 30 [SPEW ] RcompTarget[WrDSCtl]: 30 [SPEW ] RcompTarget[WrDSClk]: 25 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 10:22:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Harsha B R has uploaded a new patch set (#23) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 DDR5 SBS SODIMM 1DPC Vendor/Model - SK-Hynix/HMCG66MEBSA092N BUG=b:224325352 TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> --- M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/romstage.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c 5 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/66190/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim: Create markarth variant
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Chao Gui, Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71610 ) Change subject: mb/google/skyrim: Create markarth variant ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71610/comment/29d20727_321d7bde PS1, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). Please move the dot/period before the ). It would be even be better if the script in the Chromium repository could be fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/71610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Gerrit-Change-Number: 71610 Gerrit-PatchSet: 1 Gerrit-Owner: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 09:25:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Update USB2-C1 mapping
by Subrata Banik (Code Review) 02 Jan '23

02 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70426 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Update USB2-C1 mapping ...................................................................... mb/google/rex: Update USB2-C1 mapping This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 30 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved Eran Mitrani: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4724605..0c83341 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -31,8 +31,8 @@ chip soc/intel/meteorlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 @@ -172,6 +172,13 @@ chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" @@ -179,13 +186,6 @@ device ref usb2_port2 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port4 on end - end - chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port5 on @@ -536,7 +536,7 @@ device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn - use usb2_port4 as usb2_port + use usb2_port1 as usb2_port use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/70426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Gerrit-Change-Number: 70426 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex: Remove USB2_8 Connection
by Subrata Banik (Code Review) 02 Jan '23

02 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71237 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Remove USB2_8 Connection ...................................................................... mb/google/rex: Remove USB2_8 Connection DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 2a8c14c..4724605 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -35,7 +35,6 @@ register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth -- To view, visit https://review.coreboot.org/c/coreboot/+/71237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Gerrit-Change-Number: 71237 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex: Revise config for the Proto 1 build
by Subrata Banik (Code Review) 02 Jan '23

02 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70867 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rex: Revise config for the Proto 1 build ...................................................................... mb/google/rex: Revise config for the Proto 1 build 1. Rename DB_USB4 for KB8010 while adding ANX7452 as different DB_USB4 option. 2. Add audio component for Soundwire. 3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S. Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867 Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 28 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, approved Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index e7244cb..2a8c14c 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -1,7 +1,8 @@ fw_config field AUDIO 0 3 option AUDIO_UNKNOWN 0 - option MAX98357_ALC5682I_I2S 1 + option MAX98360_ALC5682I_I2S 1 + option MAX98363_CS42L42_SNDW 2 end field CELLULAR 4 5 option CELLULAR_ABSENT 0 @@ -23,7 +24,8 @@ field DB_USB 12 13 option USB_UNKNOWN 0 option USB3_PS8815 1 - option USB4 2 + option USB4_KB8010 2 + option USB4_ANX7452 3 end end @@ -267,7 +269,7 @@ register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on - probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S end end chip drivers/intel/mipi_camera @@ -544,12 +546,12 @@ end device ref hda on chip drivers/generic/max98357a - register "hid" = ""MX98357A"" + register "hid" = ""MX98360A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D04)" register "sdmode_delay" = "5" device generic 0 on - probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/70867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Gerrit-Change-Number: 70867 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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