coreboot-gerrit January 2023

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[S] Change in coreboot[master]: apollolake/include/soc/meminit.h: Add missing stdbool
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71245 ) Change subject: apollolake/include/soc/meminit.h: Add missing stdbool ...................................................................... apollolake/include/soc/meminit.h: Add missing stdbool stdbool is added through types.h file. Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71245 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/apollolake/include/soc/meminit.h 1 file changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 06da347..aaa5f9b 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -3,9 +3,8 @@ #ifndef _SOC_APOLLOLAKE_MEMINIT_H_ #define _SOC_APOLLOLAKE_MEMINIT_H_ -#include <stddef.h> -#include <stdint.h> #include <fsp/soc_binding.h> +#include <types.h> /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. -- To view, visit https://review.coreboot.org/c/coreboot/+/71245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Gerrit-Change-Number: 71245 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71596 ) Change subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it ...................................................................... src: Move POST_BOOTBLOCK_CAR to common postcodes and use it This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 --- M src/commonlib/include/commonlib/console/post_codes.h M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/drivers/intel/fsp1_1/cache_as_ram.S M src/include/cpu/intel/post_codes.h 4 files changed, 22 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/71596/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..0283b5d 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -66,6 +66,12 @@ #define POST_ENTRY_C_START 0x13 /** + * \brief Entry into bootblock cache-as-RAM code + * + */ +#define POST_BOOTBLOCK_CAR 0x20 + +/** * \brief Entry into pci_scan_bus * * Entered pci_scan_bus() diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index f828d6f..617da53 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -15,7 +15,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* * Nothing to do here on qemu, RAM works just fine without any * initialization. @@ -103,7 +103,6 @@ #endif before_c_entry: - post_code(0x29) call bootblock_c_entry_bist /* Never returns */ .Lhlt: diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 6a19b87..571feb4 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -34,7 +34,7 @@ movd %eax, %mm1 cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Cache the rom and update the microcode */ cache_rom: @@ -181,8 +181,6 @@ pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2a) - /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h index 3db0aeb..6c1ca79 100644 --- a/src/include/cpu/intel/post_codes.h +++ b/src/include/cpu/intel/post_codes.h @@ -3,7 +3,6 @@ #ifndef CPU_INTEL_CAR_POST_CODES_H #define CPU_INTEL_CAR_POST_CODES_H -#define POST_BOOTBLOCK_CAR 0x20 #define POST_SOC_SET_DEF_MTRR_TYPE 0x21 #define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate #define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 -- To view, visit https://review.coreboot.org/c/coreboot/+/71596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Gerrit-Change-Number: 71596 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3
by Felix Singer (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71581 ) Change subject: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35607a86242c37e1578874b3a79ff0387a55b146 Gerrit-Change-Number: 71581 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 01:26:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: inc/cpu/x86: Make sure the post_code macro is only used in asm
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71595 ) Change subject: inc/cpu/x86: Make sure the post_code macro is only used in asm ...................................................................... inc/cpu/x86: Make sure the post_code macro is only used in asm Because this post_code macro could override the post_code function, make sure it's only used in assembly files. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If106ab9a3f8d635a013bfe793405914b20e2123c --- M src/include/cpu/x86/post_code.h 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71595/1 diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index db8f90d..c9680f7 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -5,6 +5,8 @@ #include <commonlib/console/post_codes.h> +#if __ASSEMBLY__ + #if CONFIG(POST_IO) && !(ENV_BOOTBLOCK && CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)) #define post_code(value) \ movb $value, %al; \ @@ -14,4 +16,6 @@ #define post_code(value) #endif +#endif /* __ASSEMBLY__ */ + #endif /* __X86_POST_CODE_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If106ab9a3f8d635a013bfe793405914b20e2123c Gerrit-Change-Number: 71595 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Ren Kuo, Reka Norman, Eric Lai. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71170 ) Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... Patch Set 7: Code-Review-1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71170/comment/2ca79fd4_9203365e PS7, Line 9: EVT build. Please don't mention project phases in public commits. -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 7 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 00:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/[google|intel]: Define and use POST_EC_INIT and POST_EC_INIT_DONE
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71594 ) Change subject: mb/[google|intel]: Define and use POST_EC_INIT and POST_EC_INIT_DONE ...................................................................... mb/[google|intel]: Define and use POST_EC_INIT and POST_EC_INIT_DONE Add postcode definitions for starting and finishing EC initialization. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I776d63a3a71b3518dccf12d54468633e141ca6fb --- M src/commonlib/include/commonlib/console/post_codes.h M src/mainboard/google/auron/ec.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/link/ec.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/ec.c M src/mainboard/intel/strago/ec.c 7 files changed, 47 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/71594/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..b8e0b33 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -418,6 +418,23 @@ #define POST_RESUME_FAILURE 0xef /** + * \brief Initialize the EC + * + * This postcode can be used in any stage to show that the EC is being + * initialized. + */ +#define POST_EC_INIT 0xf0 + + +/** + * \brief EC Initialization done + * + * This postcode can be used in any stage to show that the EC is finished + * being initialized. + */ +#define POST_EC_INIT_DONE 0xf1 + +/** * \brief Jumping to payload * * Called right before jumping to a payload. If the boot sequence stops with diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index a3ee95b..5afcc6d 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -17,7 +18,7 @@ int s3_wakeup = acpi_is_wakeup_s3(); printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, s3_wakeup); if (s3_wakeup) { @@ -26,5 +27,5 @@ ; } - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index 41ef91e..bc0ffe5 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -15,9 +16,9 @@ }; printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, acpi_is_wakeup_s3()); - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 6f87f1d..0688f26 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -15,9 +16,9 @@ }; printk(BIOS_DEBUG, "link_ec_init\n"); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, acpi_is_wakeup_s3()); - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 7588eff..27c3030 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -17,9 +18,9 @@ }; printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, s3_wakeup); - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index a3ee95b..5afcc6d 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -17,7 +18,7 @@ int s3_wakeup = acpi_is_wakeup_s3(); printk(BIOS_DEBUG, "mainboard_ec_init\n"); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, s3_wakeup); if (s3_wakeup) { @@ -26,5 +27,5 @@ ; } - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index e34ea7f..d522d8d 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" @@ -15,9 +16,9 @@ }; printk(BIOS_DEBUG, "%s\n", __func__); - post_code(0xf0); + post_code(POST_EC_INIT); google_chromeec_events_init(&info, acpi_is_wakeup_s3()); - post_code(0xf1); + post_code(POST_EC_INIT_DONE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/71594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I776d63a3a71b3518dccf12d54468633e141ca6fb Gerrit-Change-Number: 71594 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src: Add and use POST_BOOTBLOCK_C_ENTRY
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71593 ) Change subject: src: Add and use POST_BOOTBLOCK_C_ENTRY ...................................................................... src: Add and use POST_BOOTBLOCK_C_ENTRY Add a notification for entering the bootblock C code. This was already present on one platform, but this patch defines that and uses it in all of the bootblock_c_entry() functions. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I45a86ece016e098ca42a31207fdedda5c49708d7 --- M src/commonlib/include/commonlib/console/post_codes.h M src/cpu/intel/car/bootblock.c M src/cpu/qemu-x86/bootblock.c M src/drivers/amd/agesa/bootblock.c M src/soc/amd/common/block/cpu/noncar/bootblock.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/intel/alderlake/bootblock/bootblock.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/denverton_ns/bootblock/bootblock.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/jasperlake/bootblock/bootblock.c M src/soc/intel/meteorlake/bootblock/bootblock.c M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/xeon_sp/bootblock.c 18 files changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/71593/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..7fbc60a 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -35,6 +35,13 @@ */ #define POST_RESET_VECTOR_CORRECT 0x01 + +/** + * \brief Entry into bootblock_c_entry_bist or bootblock_c_entry + * + */ +#define POST_BOOTBLOCK_C_ENTRY 0x05 + /** * \brief Entry into protected mode * diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index c53379b..49fb86d 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -2,6 +2,7 @@ #include <arch/bootblock.h> #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <cpu/x86/bist.h> #include <stdint.h> @@ -9,6 +10,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { + post_code(POST_BOOTBLOCK_C_ENTRY); + saved_bist = bist; /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..514622f 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <cpu/x86/bist.h> asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05); + post_code(POST_BOOTBLOCK_C_ENTRY); /* Halt if there was a built in self test failure */ if (bist) { diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index df9876a..e287793 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <arch/bootblock.h> +#include <commonlib/console/post_codes.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h> @@ -25,6 +26,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + enable_pci_mmconf(); set_early_mtrrs(); diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c index 13bac18..d4a484e 100644 --- a/src/soc/amd/common/block/cpu/noncar/bootblock.c +++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c @@ -3,6 +3,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/cpu.h> #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/tsc.h> @@ -12,6 +13,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index f5451f85..f8a8dc2 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -14,6 +14,7 @@ #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> #include <amdblocks/post_codes.h> +#include <commonlib/console/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -58,6 +59,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + enable_pci_mmconf(); amd_initmmio(); /* diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a4..44a95d7 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -9,6 +10,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index c9b6d93..3630ed8 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <cpu/x86/pae.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -40,6 +41,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { pci_devfn_t dev; + post_code(POST_BOOTBLOCK_C_ENTRY); bootblock_systemagent_early_init(); diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 545642f..c5ae330 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <bootblock_common.h> #include <build.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <device/pci_ops.h> #include <fsp/util.h> @@ -17,6 +18,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index a138ec4..0e12e91 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -13,6 +14,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 0846c8e..bdeeac3 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -2,6 +2,7 @@ #include <assert.h> #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <device/pci.h> #include <device/pci_ops.h> #include <FsptUpd.h> @@ -48,6 +49,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); }; diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c index cc0bb8f..5de1c54 100644 --- a/src/soc/intel/elkhartlake/bootblock/bootblock.c +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> @@ -11,6 +12,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index ef5ada6..160cf64 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -9,6 +10,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index b8086a4..44a95d7 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -9,6 +10,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/meteorlake/bootblock/bootblock.c b/src/soc/intel/meteorlake/bootblock/bootblock.c index c7e1826..d4dac73 100644 --- a/src/soc/intel/meteorlake/bootblock/bootblock.c +++ b/src/soc/intel/meteorlake/bootblock/bootblock.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <soc/bootblock.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 2e1a099..4fd83be 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/pci_def.h> @@ -65,6 +66,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY)) light_sd_led(); diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 4b31f77..3dc86a3 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <cpu/cpu.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> @@ -11,6 +12,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* Call lib/bootblock.c main */ bootblock_main_with_basetime(base_timestamp); } diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5ea09ac..e975b18 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <bootblock_common.h> +#include <commonlib/console/post_codes.h> #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> @@ -39,6 +40,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_BOOTBLOCK_C_ENTRY); + /* * FSP-T does not respect its own API and trashes registers * coreboot uses to store its initial timestamp. -- To view, visit https://review.coreboot.org/c/coreboot/+/71593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45a86ece016e098ca42a31207fdedda5c49708d7 Gerrit-Change-Number: 71593 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vc/google: Add and use POST_CODE_CLEAR definition
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71592 ) Change subject: vc/google: Add and use POST_CODE_CLEAR definition ...................................................................... vc/google: Add and use POST_CODE_CLEAR definition The CR50 code clears the post code value. Add this as a #define. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c --- M src/commonlib/include/commonlib/console/post_codes.h M src/vendorcode/google/chromeos/cr50_enable_update.c 2 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/71592/1 diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index d838815..ef296bd 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -28,6 +28,12 @@ #define POST_CODES_H /** + * \brief Not an actual post-code - used to clear port80h + * + */ +#define POST_CODE_CLEAR 0x00 + +/** * \brief Entry into 'crt0.s'. reset code jumps to here * * First instruction that gets executed after the reset vector jumps. diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 9ac33a5..6beea91 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootstate.h> +#include <commonlib/console/post_codes.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <elog.h> @@ -133,7 +134,7 @@ mainboard_prepare_cr50_reset(); /* clear current post code avoid chatty eventlog on subsequent boot*/ - post_code(0); + post_code(POST_CODE_CLEAR); /* * Older Cr50 firmware doesn't support the timeout parameter for the -- To view, visit https://review.coreboot.org/c/coreboot/+/71592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Gerrit-Change-Number: 71592 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: drivers/amd: Update to use defined post codes
by Martin L Roth (Code Review) 01 Jan '23

01 Jan '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71591 ) Change subject: drivers/amd: Update to use defined post codes ...................................................................... drivers/amd: Update to use defined post codes Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/71591/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 0d678d1..e342039 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -12,6 +12,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +#include <amdblocks/post_codes.h> .section .init @@ -30,7 +31,7 @@ */ bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -56,7 +57,7 @@ movd %mm1, %eax pushl %eax /* tsc[31:0] */ - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry -- To view, visit https://review.coreboot.org/c/coreboot/+/71591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Gerrit-Change-Number: 71591 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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