coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: nb/intel/haswell: Specify supported memory type
by Angel Pons (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71583 ) Change subject: nb/intel/haswell: Specify supported memory type ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/haswell/Kconfig: https://review.coreboot.org/c/coreboot/+/71583/comment/303e42cb_e58a494a PS2, Line 6: if NORTHBRIDGE_INTEL_HASWELL : : config NORTHBRIDGE_SPECIFIC_OPTIONS : def_bool y Seems to be unrelated -- To view, visit https://review.coreboot.org/c/coreboot/+/71583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Gerrit-Change-Number: 71583 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 01 Jan 2023 17:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3
by Angel Pons (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Jason Glenesk, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71581 ) Change subject: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File Documentation/releases/coreboot-4.17-relnotes.md: https://review.coreboot.org/c/coreboot/+/71581/comment/79c4b145_a7b5c42f PS1, Line 302: V4 Hmmm, some paragraphs spell `V3` and `V4` in uppercase, whereas others spell `v3` and `v4` in lowercase. It'd be nice to make it consistent. -- To view, visit https://review.coreboot.org/c/coreboot/+/71581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35607a86242c37e1578874b3a79ff0387a55b146 Gerrit-Change-Number: 71581 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 15:57:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation/releases: Start getting ready for the 4.19 release
by Angel Pons (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Felix Singer, Jason Glenesk, Martin L Roth. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71590 ) Change subject: Documentation/releases: Start getting ready for the 4.19 release ...................................................................... Patch Set 1: Code-Review+1 (7 comments) File Documentation/releases/coreboot-4.19-relnotes.md: https://review.coreboot.org/c/coreboot/+/71590/comment/84382603_c063b93d PS1, Line 13: relevent typo: relev*a*nt https://review.coreboot.org/c/coreboot/+/71590/comment/84999c3b_d42392bc PS1, Line 42: optoins typo: options https://review.coreboot.org/c/coreboot/+/71590/comment/d2e1cccc_0079cde6 PS1, Line 46: nit: remove one space https://review.coreboot.org/c/coreboot/+/71590/comment/c26a9c26_aafd8033 PS1, Line 64: * AMD: Mayan for Morgana SoC : * GIGABYTE: GA-H61M-DS2 : * Google: Crystaldrift : * Google: Gladios : * Google: Marasov : * Google: Voltorb : * Intel: Meteorlake-P RVP : * Siemens: MC_EHL3 : * Star Labs: StarBook Mk VI (i3-1220P and i7-1260P) : * System76: darp8 : * System76: galp6 nit: Please be consistent with the spacing after the colon: some lines have one space, whereas others have two. https://review.coreboot.org/c/coreboot/+/71590/comment/5af84833_a58bf6ff PS1, Line 114: * src/soc/intel/xeon_sp/lbg This isn't a new platform, it's just a result of restructuring the code as part of CB:70009. It'd be better to drop it. https://review.coreboot.org/c/coreboot/+/71590/comment/d8655c73_da253576 PS1, Line 110: New SoCs : ------------------- : : * src/soc/amd/glinda : * src/soc/intel/xeon_sp/lbg : : : Removed processors : ------------------- : : * src/cpu/amd/agesa/family14 : * src/cpu/amd/agesa/family15tn : * src/cpu/amd/agesa/family16kb nit: drop the `src/` prefix? https://review.coreboot.org/c/coreboot/+/71590/comment/c9656524_e3435097 PS1, Line 124: Also list dropped northbridges/southbridges? -- To view, visit https://review.coreboot.org/c/coreboot/+/71590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3edbf3ebc74ebae5896196b43dd5be014f27a0ec Gerrit-Change-Number: 71590 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 15:55:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Create markarth variant
by Chao Gui (Code Review) 01 Jan '23

01 Jan '23

Chao Gui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71610 ) Change subject: mb/google/skyrim: Create markarth variant ...................................................................... mb/google/skyrim: Create markarth variant Create the markarth variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:262092858 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_MARKARTH Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Signed-off-by: Chao Gui <chaogui(a)google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/Kconfig.name A src/mainboard/google/skyrim/variants/markarth/include/variant/ec.h A src/mainboard/google/skyrim/variants/markarth/overridetree.cb 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/71610/1 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 5eee2d6..493ecb5 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -91,6 +91,7 @@ default "Morthal" if BOARD_GOOGLE_MORTHAL default "Frostflow" if BOARD_GOOGLE_FROSTFLOW default "Crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT + default "Markarth" if BOARD_GOOGLE_MARKARTH config OVERRIDE_DEVICETREE string @@ -103,6 +104,7 @@ default "morthal" if BOARD_GOOGLE_MORTHAL default "frostflow" if BOARD_GOOGLE_FROSTFLOW default "crystaldrift" if BOARD_GOOGLE_CRYSTALDRIFT + default "markarth" if BOARD_GOOGLE_MARKARTH config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name index 23aea48..e7c6505 100644 --- a/src/mainboard/google/skyrim/Kconfig.name +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -26,3 +26,7 @@ config BOARD_GOOGLE_CRYSTALDRIFT bool "-> Crystaldrift" select BOARD_GOOGLE_BASEBOARD_SKYRIM + +config BOARD_GOOGLE_MARKARTH + bool "-> Markarth" + select BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/mainboard/google/skyrim/variants/markarth/include/variant/ec.h b/src/mainboard/google/skyrim/variants/markarth/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb new file mode 100644 index 0000000..7a56f93 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/mendocino + device domain 0 on end +end # chip soc/amd/mendocino -- To view, visit https://review.coreboot.org/c/coreboot/+/71610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Gerrit-Change-Number: 71610 Gerrit-PatchSet: 1 Gerrit-Owner: Chao Gui <chaogui(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/braswell/Makefile.inc: Remove path to non-existent directories
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Paul Menzel. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71554 ) Change subject: soc/intel/braswell/Makefile.inc: Remove path to non-existent directories ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/braswell/Makefile.inc: https://review.coreboot.org/c/coreboot/+/71554/comment/c4058ce3_e8d82c5a PS2, Line 67: CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) > I think that the way is not wrong, however, none of boards (braswell) has a blob directory ... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8 Gerrit-Change-Number: 71554 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 14:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: WIP: mb/hp/t620: Add new board HP T620
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71609 ) Change subject: WIP: mb/hp/t620: Add new board HP T620 ...................................................................... Patch Set 1: (7 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/4e8210d6_03126b1b PS1, Line 11: This work was done during a coreboot hacking party! Board is AMD Fam16kb Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/780c7e08_c222e1d7 PS1, Line 36: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/1e7b4ef3_3d862f7a PS1, Line 41: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/8cf3383d_d1d09ff0 PS1, Line 48: cbfs_master_header 0x0 cbfs header 32 none Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/fd6d5ab0_743b310f PS1, Line 59: fallback/romstage 0x20e00 stage 386080 none Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/6ea45b66_0a5784d5 PS1, Line 69: ... Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483): https://review.coreboot.org/c/coreboot/+/71609/comment/c5040dba_fe1a0107 PS1, Line 80: [DEBUG] smbios_write_tables: 5fe8e000 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Gerrit-Change-Number: 71609 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/hp/t620: Add clone of biostar/a68n-5200
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71608 ) Change subject: mb/hp/t620: Add clone of biostar/a68n-5200 ...................................................................... Patch Set 1: (13 comments) File src/mainboard/hp/t620/BiosCallOuts.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/06edbb8d_468065ec PS1, Line 11: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/563dc4f4_8948154e PS1, Line 45: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/9b08aa43_f2580f15 PS1, Line 46: {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/84941c55_311018c2 PS1, Line 47: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} "(foo*)" should be "(foo *)" File src/mainboard/hp/t620/OemCustomize.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/604632cb_ebf3b780 PS1, Line 118: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/1a0b2ce7_a4f5e573 PS1, Line 119: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/2a3a8605_2d90c5d8 PS1, Line 120: MOTHER_BOARD_LAYERS(LAYERS_4), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/f33010bd_80927217 PS1, Line 122: MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/30e4ebf9_b854cce8 PS1, Line 123: CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/bdad75f8_9a9f7fd1 PS1, Line 124: ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/4cdb037c_0e074be0 PS1, Line 125: CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/6ad023f3_9a3608a0 PS1, Line 127: PSO_END please, no spaces at the start of a line File src/mainboard/hp/t620/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/75846232_6557eb3b PS1, Line 81: if (sum != pirq->checksum) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/71608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 71608 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Revert "{cpu/nb}/amd/family16: Remove platform"
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71603 ) Change subject: Revert "{cpu/nb}/amd/family16: Remove platform" ...................................................................... Patch Set 1: (12 comments) File src/northbridge/amd/agesa/family16kb/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/606ec202_1c46d2bb PS1, Line 7: { open brace '{' following struct go on the same line File src/northbridge/amd/agesa/family16kb/northbridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/1a460bcb_55829456 PS1, Line 51: if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/f8a58b6c_00317cc3 PS1, Line 72: if (dev && dev->enabled) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/dc59373c_6a20d164 PS1, Line 300: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/b4e17c68_d0ab5da2 PS1, Line 315: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/9db3d3f7_e3f78b27 PS1, Line 393: if (res) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/ae4e67a7_e13bbd03 PS1, Line 438: if (base_k > 4 * 1024 * 1024) break; // don't need to go to check trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/ed0d28df_d653711b PS1, Line 462: for (link = dev->link_list; link; link = link->next) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/7d66dc8d_5ca6f77f PS1, Line 525: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/10e79092_3a964b5d PS1, Line 541: if (link->children) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/860a4095_6a32656f PS1, Line 592: if (ApicIdCoreIdSize) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/1b298054_dd5fc9ff PS1, Line 699: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/71603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Gerrit-Change-Number: 71603 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:15:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Revert "sb/amd: Remove dropped platforms"
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71598 ) Change subject: Revert "sb/amd: Remove dropped platforms" ...................................................................... Patch Set 1: (134 comments) File src/southbridge/amd/agesa/hudson/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/20ed09a0_f787d4bb PS1, Line 7: { open brace '{' following struct go on the same line File src/southbridge/amd/agesa/hudson/enable_usbdebug.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2d2656c5_d0a9f7aa PS1, Line 38: reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ Possible repeated word: 'Port' File src/southbridge/amd/agesa/hudson/lpc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3df1a0ae_ca589f30 PS1, Line 50: on on LPC, it holds PCI grant, so no LPC slave cycle can Possible repeated word: 'on' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b9614ff1_bcc8ac95 PS1, Line 247: if ((var_num > 0) && ((base >= reg_var[0]) && Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a519ed39_38717ada PS1, Line 259: switch (var_num) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4bc8d662_b8aceeb2 PS1, Line 262: if (res->size <= 16) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/09c09ed1_4882d6aa PS1, Line 262: if (res->size <= 16) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/64b4b428_9f259c0c PS1, Line 268: if (res->size <= 16) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/936a62f7_d01940cf PS1, Line 273: if (res->size <= 16) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f05228df_f88c88ee PS1, Line 289: /* Set WideIO for as many IOs found (fall through is on purpose) */ Prefer 'fallthrough;' over fallthrough comment File src/southbridge/amd/agesa/hudson/sata.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/760f2a7f_26ebe2a4 PS1, Line 24: (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); "(foo*)" should be "(foo *)" File src/southbridge/amd/agesa/hudson/sd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9c005c2c_77e5465f PS1, Line 26: else { /* SD 2.0 mode */ else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b0336f47_44cc846f PS1, Line 32: else { /* Stepping >= A1 */ else should follow close brace '}' File src/southbridge/amd/agesa/hudson/smbus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1a6616a4_f1bc456a PS1, Line 38: if (val & 0x1c) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/24de9d34_eb2c4dee PS1, Line 54: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/908eafc7_144bd557 PS1, Line 67: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6098a0a4_92027c52 PS1, Line 81: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b3aaa40e_f9000b98 PS1, Line 97: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bfd7cf55_6d9ef541 PS1, Line 108: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/15774617_88a6d391 PS1, Line 124: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f3c2f306_783fb6dd PS1, Line 138: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4ff95a33_47d3c6a8 PS1, Line 157: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks File src/southbridge/amd/agesa/hudson/smbus_spd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/44fbb720_892dee87 PS1, Line 34: for (;;) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5e790d18_e7ca9063 PS1, Line 37: if (__rdtsc() > limit) break; trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/34bcae4e_17f4c9fe PS1, Line 38: if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/251929ad_376b6e1a PS1, Line 39: if ((status & 1) == 1) continue; // HostBusy set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/379716cb_32c7e966 PS1, Line 43: buffer [0] = __inbyte(iobase + 5); space prohibited before open square bracket '[' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6f69caa1_6f3b0a6e PS1, Line 44: if (status == 2) status = 0; // check for done with no errors trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/068574bf_b4122c15 PS1, Line 64: for (;;) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0a214d3a_e358a476 PS1, Line 67: if (__rdtsc() > limit) break; trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e3d36045_e0a93fbd PS1, Line 68: if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d6921f3f_713a894f PS1, Line 69: if ((status & 1) == 1) continue; // HostBusy set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9ac7ae9b_e9c626a6 PS1, Line 73: buffer [0] = __inbyte(iobase + 5); space prohibited before open square bracket '[' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/575cbcd4_ee7b7aec PS1, Line 74: if (status == 2) status = 0; // check for done with no errors trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bbaa5634_809775c7 PS1, Line 104: for (index = 1; index < count; index++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0003c82e_a8685f48 PS1, Line 106: error = readSmbusByte(iobase, SmbusSlaveAddress, &buffer [index]); space prohibited before open square bracket '[' File src/southbridge/amd/agesa/hudson/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dffdaca3_bebd4adf PS1, Line 63: while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4143c437_1ea681fd PS1, Line 112: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/72403672_078c1364 PS1, Line 121: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3caaff4c_d8564a02 PS1, Line 125: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks File src/southbridge/amd/cimx/sb800/Amd.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b7bf41d1_ae78ba93 PS1, Line 53: PreMemHeap = 0, ///< Create heap in cache. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/96bf8c78_a6c8036e PS1, Line 54: PostMemDram, ///< Create heap in memory. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d08e5546_a38f31c6 PS1, Line 55: ByHost ///< Create heap by Host. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/244a9e63_1d8ba7a8 PS1, Line 60: AccessWidth8 = 1, ///< Access width is 8 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d42784e5_3a5a3a4d PS1, Line 61: AccessWidth16, ///< Access width is 16 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cca6c855_d79834c4 PS1, Line 62: AccessWidth32, ///< Access width is 32 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f511e052_49a18db2 PS1, Line 63: AccessWidth64, ///< Access width is 64 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e1ad70e0_3347d128 PS1, Line 65: AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cdd03fbf_717feb0c PS1, Line 66: AccessS3SaveWidth16, ///< Save 16 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/91699365_1df0c0cd PS1, Line 67: AccessS3SaveWidth32, ///< Save 32 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d96f9864_5d1bdfe7 PS1, Line 68: AccessS3SaveWidth64, ///< Save 64 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b9820eb2_9f59dc84 PS1, Line 75: IN unsigned int ImageBasePtr; ///< The AGESA Image base address. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/47eda50b_099b912d PS1, Line 76: IN unsigned int Func; ///< The service desired, @sa dispatch.h. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3fe4d5aa_80de40c6 PS1, Line 77: IN unsigned int AltImageBasePtr; ///< Alternate Image location please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/8fe2e050_eeffb6c9 PS1, Line 78: IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eb6ef11f_ec3d6a89 PS1, Line 79: union { ///< Callback pointer please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2294c0d2_be895dd6 PS1, Line 80: IN unsigned long long PlaceHolder; ///< Place holder please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4a0f8ca0_30e1cae4 PS1, Line 81: IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/05c3b8e0_b7f89f45 PS1, Line 82: } CALLBACK; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e20af17b_5c63f6e2 PS1, Line 83: IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3cdb1e4c_6cbf71e9 PS1, Line 88: IN unsigned int Signature; ///< Binary Signature please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b2889631_17e2ef44 PS1, Line 89: IN signed char CreatorID[8]; ///< 8 characters ID please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e5816041_b0d6d710 PS1, Line 90: IN signed char Version[12]; ///< 12 characters version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b5d72b50_48552c61 PS1, Line 91: IN unsigned int ModuleInfoOffset; ///< Offset of module please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/72cc8d6a_957445c1 PS1, Line 92: IN unsigned int EntryPointAddress; ///< Entry address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e92397dd_274ca2aa PS1, Line 93: IN unsigned int ImageBase; ///< Image base please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/51f1155c_ac15a088 PS1, Line 94: IN unsigned int RelocTableOffset; ///< Relocate Table offset please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ec65061c_667ed5f0 PS1, Line 95: IN unsigned int ImageSize; ///< Size please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a994eb5c_5f66d125 PS1, Line 96: IN unsigned short Checksum; ///< Checksum please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/424dc612_892ed969 PS1, Line 97: IN unsigned char ImageType; ///< Type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6d857f7c_b0982ce9 PS1, Line 98: IN unsigned char V_Reserved; ///< Reserved please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/37675d7c_15a88f12 PS1, Line 103: IN unsigned int ModuleHeaderSignature; ///< Module signature please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f9450b1e_3508c7d1 PS1, Line 104: IN signed char ModuleIdentifier[8]; ///< 8 characters ID please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6882388f_c3efb489 PS1, Line 105: IN signed char ModuleVersion[12]; ///< 12 characters version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/38687bcb_99c5a8ad PS1, Line 106: IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ae4e4167_1e2fac26 PS1, Line 107: IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f803be51_eddbc26a PS1, Line 130: IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ef5120e3_9563a2d2 PS1, Line 131: IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eb702d64_ccd4fa2a PS1, Line 132: IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/940bd33e_222440e5 PS1, Line 133: IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/77f65f79_65cebe07 PS1, Line 142: HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1f449543_c69e3fc4 PS1, Line 143: HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a07d924e_7167ab38 PS1, Line 144: HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/33649dc0_29ee02e1 PS1, Line 145: HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/36d90692_d8f72d44 PS1, Line 146: HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/04ddc37e_d12446ed PS1, Line 147: HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2295200e_3131fe00 PS1, Line 148: HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1456db79_5ae129bb PS1, Line 149: HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bf7c520c_54c6f808 PS1, Line 150: HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f00a3990_47d6cf12 PS1, Line 151: HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ed275163_55859087 PS1, Line 152: HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/972b0875_4d045c73 PS1, Line 153: HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5f705113_2f440610 PS1, Line 154: HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dd58f29f_7a96f00b PS1, Line 155: HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1c4e7bde_1ee27ce8 PS1, Line 156: HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/324662b0_42718153 PS1, Line 157: HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks please, no spaces at the start of a line File src/southbridge/amd/cimx/sb800/AmdSbLib.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d7f3f068_8fe672ee PS1, Line 18: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e458c76d_b7983a65 PS1, Line 19: unsigned int AMDLogo; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eff317db_ca5beff5 PS1, Line 20: unsigned long long CreatorID; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e329503c_8aea6d42 PS1, Line 21: unsigned int Version1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5fc8dd55_59414bf6 PS1, Line 22: unsigned int Version2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/79d651f2_cc96c230 PS1, Line 23: unsigned int Version3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d6eeadf1_02a641b8 PS1, Line 24: unsigned int ModuleInfoOffset; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/90cb86f7_b4ee5fa7 PS1, Line 25: unsigned int EntryPoint; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6669edd3_0eab44bc PS1, Line 26: unsigned int ImageBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/c0f1bc41_267b129a PS1, Line 27: unsigned int RelocTableOffset; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/67920d6c_761b1c46 PS1, Line 28: unsigned int ImageSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b8a5e969_4dbd368f PS1, Line 29: unsigned short CheckSum; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6759c5ba_ebccc585 PS1, Line 30: unsigned char ImageType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4c4f1038_6d52cb10 PS1, Line 31: unsigned char Reserved2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5ef5d22d_c356e0b7 PS1, Line 134: { open brace '{' following enum go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/428cd24d_736bf52b PS1, Line 135: AccWidthUint8 = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0c81a928_f6ea122d PS1, Line 136: AccWidthUint16, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f62dff12_661afae6 PS1, Line 137: AccWidthUint32, please, no spaces at the start of a line File src/southbridge/amd/cimx/sb800/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d16779cb_483fdc66 PS1, Line 19: { open brace '{' following struct go on the same line File src/southbridge/amd/cimx/sb800/fan.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/c0659cd9_75248ccf PS1, Line 261: if (sb_chip->imc_tempin3_enabled) { suspicious code indentation after conditional statements File src/southbridge/amd/cimx/sb800/late.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e6cebdf7_41eac2a8 PS1, Line 96: if (!(val & HOST_CTL_AHCI_EN)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f9a1f232_b4c3c8bb PS1, Line 344: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/63c86325_db3c1a20 PS1, Line 374: if (dev->enabled) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1dd2f06e_4190cec6 PS1, Line 385: if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break; trailing statements should be on next line File src/southbridge/amd/cimx/sb800/lpc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0bb112f8_cbf70d3c PS1, Line 135: if (var_num >= 3) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5aca9eed_fff930a0 PS1, Line 137: switch (var_num) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/972e2b5f_6e1ec1b3 PS1, Line 157: /* Set WideIO for as many IOs found (fall through is on purpose) */ Prefer 'fallthrough;' over fallthrough comment File src/southbridge/amd/cimx/sb800/smbus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a11e371a_16a93846 PS1, Line 36: if (val & 0x1c) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/22b201ce_cd89ec01 PS1, Line 67: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e7796d4d_4e269be5 PS1, Line 82: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspicious code indentation after conditional statements Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/60dbc8fd_cad055fe PS1, Line 100: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a2557c71_4bcaa867 PS1, Line 130: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/84687465_cee371a7 PS1, Line 166: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks File src/southbridge/amd/cimx/sb800/smbus_spd.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dc77f30b_4d23e506 PS1, Line 32: #define SMBUS_FREQUENCY_CONST 66000000 / 4 Macros with complex values should be enclosed in parentheses File src/southbridge/amd/cimx/sb800/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cc6d4a97_783fb3ce PS1, Line 31: while ((read8((void *)(spibar + 2)) & 1) && trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9c2f0c3d_57d2406c PS1, Line 74: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e1e52625_2cc82841 PS1, Line 83: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e6062a26_5789bf66 PS1, Line 88: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/71598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888 Gerrit-Change-Number: 71598 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:15:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: WIP: mb/hp/t620: Add new board HP T620
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71609 ) Change subject: WIP: mb/hp/t620: Add new board HP T620 ...................................................................... WIP: mb/hp/t620: Add new board HP T620 This is the diff applied to the previous commit to change the biostar/a68n_5200 port into support for new board: HP T620 thin client. This work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. It has a socketed SOIC8 chip and SIO accessible serial, making it a good target for testing/maintaining this platform. coreboot console works over serial COMA by default. Board is fanless, so no need for fan control. TESTED: Boots SeaBIOS 1.14.0 and to debian 11, NIC works, serial works. Have had 120 days of uptime with this particular port and no issues. Missing: - Audio verb table (deleted) - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board) Caveat: Without VGA BIOS rom there are no displays. VGA ROM was extracted from /dev/mem @ 0xC0000 on a running system and one DP was tested to work. NB: Since bringing back AGESA code with resource allocator v4 and parallel mp init, this board no longer boots due to some kind of CBFS alignment issue, I need some help to figure this out. cbfs: This image contains the following sections that can be manipulated with this tool: 'RW_MRC_CACHE' (size 65536, offset 0) 'COREBOOT' (CBFS, size 8322560, offset 66048) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none config 0x80 raw 2327 LZMA (6878 decompressed) revision 0xa00 raw 717 none build_info 0xd00 raw 89 none fallback/dsdt.aml 0xd80 raw 5950 none cmos_layout.bin 0x2500 cmos_layout 616 none fallback/postcar 0x27c0 stage 21688 none payload_config 0x7cc0 raw 1621 none payload_revision 0x8340 raw 235 none (empty) 0x8480 null 31012 none apu/amdfw 0xfdc0 raw 69632 none fallback/romstage 0x20e00 stage 386080 none fallback/ramstage 0x7f2c0 stage 125180 LZMA (283964 decompressed) pci1002,9837.rom 0x9dc40 optionrom 65536 none fallback/payload 0xadc80 simple elf 72756 none (empty) 0xbf900 null 7524836 none bootblock 0x7ecb00 bootblock 12992 none ... Built hp/t620 (T620) tail of coreboot log: ... [INFO ] CBFS: Found 'pci1002,9837.rom' @0x9dc40 size 0x10000 in mcache @0x5ffdd2a4 [NOTE ] Mapping PCI device 10029837 to 10029830 [DEBUG] In CBFS, ROM address for PCI: 00:01.0 = 0xff8ade6c [DEBUG] Copying VBIOS image from 0xff8ade6c [DEBUG] ACPI: * VFCT at 5fe9d420 [DEBUG] ACPI: added table 8/32, length now 68 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 9/32, length now 72 [INFO ] ACPI: done. [DEBUG] ACPI tables: 89808 bytes. [DEBUG] smbios_write_tables: 5fe8e000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-1385-g5be491174b' [DEBUG] SMBIOS tables: 529 bytes. [DEBUG] Writing table forward entry at 0x00000500 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 80 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 428 Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/t620/BiosCallOuts.c M src/mainboard/hp/t620/Kconfig M src/mainboard/hp/t620/Kconfig.name M src/mainboard/hp/t620/board_info.txt M src/mainboard/hp/t620/bootblock.c M src/mainboard/hp/t620/devicetree.cb 6 files changed, 128 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/71609/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c index f1560c4..a0ac3f0 100644 --- a/src/mainboard/hp/t620/BiosCallOuts.c +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -5,8 +5,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include "imc.h" - const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, @@ -24,20 +22,6 @@ * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} }; @@ -47,113 +31,6 @@ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; @@ -164,7 +41,4 @@ { /* Azalia Controller OEM Codec Table Pointer */ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); } diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig index 256121c..f897bab 100644 --- a/src/mainboard/hp/t620/Kconfig +++ b/src/mainboard/hp/t620/Kconfig @@ -1,24 +1,22 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_BIOSTAR_A68N5200_CLONE +if BOARD_HP_T620 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_ITE_IT8728F + select SUPERIO_ASPEED_AST2400 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_8192 select GFXUMA config MAINBOARD_DIR default "hp/t620" config MAINBOARD_PART_NUMBER - default "A68N5200" + default "T620" config HW_MEM_HOLE_SIZEK hex @@ -40,4 +38,4 @@ bool default n -endif +endif # BOARD_HP_T620 diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name index e893341..fd55b76 100644 --- a/src/mainboard/hp/t620/Kconfig.name +++ b/src/mainboard/hp/t620/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200_CLONE - bool "A68N-5200-CLONE" +config BOARD_HP_T620 + bool "T620" diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt index b351b8e..4132ada 100644 --- a/src/mainboard/hp/t620/board_info.txt +++ b/src/mainboard/hp/t620/board_info.txt @@ -1 +1,2 @@ Category: eval +Socketed Flash: Y diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c index 70bc10c..5226f4a 100644 --- a/src/mainboard/hp/t620/bootblock.c +++ b/src/mainboard/hp/t620/bootblock.c @@ -4,27 +4,10 @@ #include <bootblock_common.h> #include <stdint.h> #include <device/pci_ops.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - u32 reg32; - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - reg32 = misc_read32(0x28); - reg32 &= 0xfff8ffff; - misc_write32(0x28, reg32); - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = misc_read32(0x40); - reg32 &= 0xffffbffb; - misc_write32(0x40, reg32); -} +#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART2) void bootblock_mainboard_early_init(void) { @@ -35,7 +18,7 @@ /* Set LPC decode enables. */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pci_write_config32(dev, 0x44, 0xff03ffc0); /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); @@ -47,11 +30,6 @@ byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Enable serial output on it8728f */ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* Enable serial output */ + aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb index c036b65..ed6fa58 100644 --- a/src/mainboard/hp/t620/devicetree.cb +++ b/src/mainboard/hp/t620/devicetree.cb @@ -8,15 +8,15 @@ end device domain 0 on - subsystemid 0x1022 0x1410 inherit + subsystemid 0x103c 0x2187 inherit chip northbridge/amd/agesa/family16kb device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal HDMI Audio device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC + device pci 2.1 off end + device pci 2.2 on end + device pci 2.3 on end device pci 2.4 off end # Edge Connector device pci 2.5 off end # Edge Connector end #chip northbridge/amd/agesa/family16kb @@ -28,42 +28,23 @@ device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pci 14.0 on end # SMBus + device pci 14.2 on end # Audio Azalia + device pci 14.3 on # LPC + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "0" + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 on # SUART2 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0x71 = 3 + irq 0xf0 = 2 + end + end end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F + end end #LPC device pci 14.7 off end # SD end #chip southbridge/amd/agesa/hudson @@ -75,12 +56,10 @@ device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + register "spdAddrLookup" = "{ + { {0xA0, 0xA2}, {0x00, 0x00}, }, + { {0x00, 0x00}, {0x00, 0x00}, }, }" end - - end #domain + end end #northbridge/amd/agesa/family16kb/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/71609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Gerrit-Change-Number: 71609 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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coreboot-gerrit January 2023