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Change subject: nb/intel/haswell: Specify supported memory type
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/intel/haswell/Kconfig:
https://review.coreboot.org/c/coreboot/+/71583/comment/bb67531a_48ebd3e2
PS2, Line 18: select USE_DDR4
Haswell does *not* support DDR4. The server platforms do, but they're a completely different beast (not supported in coreboot yet).
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Change subject: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File Documentation/releases/coreboot-4.17-relnotes.md:
https://review.coreboot.org/c/coreboot/+/71581/comment/79c4b145_a7b5c42f
PS1, Line 302: V4
Hmmm, some paragraphs spell `V3` and `V4` in uppercase, whereas others spell `v3` and `v4` in lowercase. It'd be nice to make it consistent.
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Change subject: Documentation/releases: Start getting ready for the 4.19 release
......................................................................
Patch Set 1: Code-Review+1
(7 comments)
File Documentation/releases/coreboot-4.19-relnotes.md:
https://review.coreboot.org/c/coreboot/+/71590/comment/84382603_c063b93d
PS1, Line 13: relevent
typo: relev*a*nt
https://review.coreboot.org/c/coreboot/+/71590/comment/84999c3b_d42392bc
PS1, Line 42: optoins
typo: options
https://review.coreboot.org/c/coreboot/+/71590/comment/d2e1cccc_0079cde6
PS1, Line 46:
nit: remove one space
https://review.coreboot.org/c/coreboot/+/71590/comment/c26a9c26_aafd8033
PS1, Line 64: * AMD: Mayan for Morgana SoC
: * GIGABYTE: GA-H61M-DS2
: * Google: Crystaldrift
: * Google: Gladios
: * Google: Marasov
: * Google: Voltorb
: * Intel: Meteorlake-P RVP
: * Siemens: MC_EHL3
: * Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
: * System76: darp8
: * System76: galp6
nit: Please be consistent with the spacing after the colon: some lines have one space, whereas others have two.
https://review.coreboot.org/c/coreboot/+/71590/comment/5af84833_a58bf6ff
PS1, Line 114: * src/soc/intel/xeon_sp/lbg
This isn't a new platform, it's just a result of restructuring the code as part of CB:70009. It'd be better to drop it.
https://review.coreboot.org/c/coreboot/+/71590/comment/d8655c73_da253576
PS1, Line 110: New SoCs
: -------------------
:
: * src/soc/amd/glinda
: * src/soc/intel/xeon_sp/lbg
:
:
: Removed processors
: -------------------
:
: * src/cpu/amd/agesa/family14
: * src/cpu/amd/agesa/family15tn
: * src/cpu/amd/agesa/family16kb
nit: drop the `src/` prefix?
https://review.coreboot.org/c/coreboot/+/71590/comment/c9656524_e3435097
PS1, Line 124:
Also list dropped northbridges/southbridges?
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Change subject: soc/intel/braswell/Makefile.inc: Remove path to non-existent directories
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/braswell/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/71554/comment/c4058ce3_e8d82c5a
PS2, Line 67: CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
> I think that the way is not wrong, however, none of boards (braswell) has a blob directory ...
Done
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Change subject: WIP: mb/hp/t620: Add new board HP T620
......................................................................
Patch Set 1:
(7 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/4e8210d6_03126b1b
PS1, Line 11: This work was done during a coreboot hacking party! Board is AMD Fam16kb
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/780c7e08_c222e1d7
PS1, Line 36:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/1e7b4ef3_3d862f7a
PS1, Line 41:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/8cf3383d_d1d09ff0
PS1, Line 48: cbfs_master_header 0x0 cbfs header 32 none
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/fd6d5ab0_743b310f
PS1, Line 59: fallback/romstage 0x20e00 stage 386080 none
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/6ea45b66_0a5784d5
PS1, Line 69: ...
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167483):
https://review.coreboot.org/c/coreboot/+/71609/comment/c5040dba_fe1a0107
PS1, Line 80: [DEBUG] smbios_write_tables: 5fe8e000
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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