Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71598 )
Change subject: Revert "sb/amd: Remove dropped platforms"
......................................................................
Revert "sb/amd: Remove dropped platforms"
This reverts commit 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051.
Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
M src/drivers/amd/agesa/state_machine.c
M src/northbridge/amd/agesa/state_machine.h
A src/southbridge/amd/agesa/Kconfig
A src/southbridge/amd/agesa/Makefile.inc
A src/southbridge/amd/agesa/hudson/Kconfig
A src/southbridge/amd/agesa/hudson/Makefile.inc
A src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl
A src/southbridge/amd/agesa/hudson/acpi/audio.asl
A src/southbridge/amd/agesa/hudson/acpi/fch.asl
A src/southbridge/amd/agesa/hudson/acpi/lpc.asl
A src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
A src/southbridge/amd/agesa/hudson/acpi/pcie.asl
A src/southbridge/amd/agesa/hudson/acpi/smbus.asl
A src/southbridge/amd/agesa/hudson/acpi/usb.asl
A src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
A src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
A src/southbridge/amd/agesa/hudson/bootblock.c
A src/southbridge/amd/agesa/hudson/chip.h
A src/southbridge/amd/agesa/hudson/early_setup.c
A src/southbridge/amd/agesa/hudson/enable_usbdebug.c
A src/southbridge/amd/agesa/hudson/fadt.c
A src/southbridge/amd/agesa/hudson/hda.c
A src/southbridge/amd/agesa/hudson/hudson.c
A src/southbridge/amd/agesa/hudson/hudson.h
A src/southbridge/amd/agesa/hudson/ide.c
A src/southbridge/amd/agesa/hudson/imc.c
A src/southbridge/amd/agesa/hudson/imc.h
A src/southbridge/amd/agesa/hudson/lpc.c
A src/southbridge/amd/agesa/hudson/pci.c
A src/southbridge/amd/agesa/hudson/pci_devs.h
A src/southbridge/amd/agesa/hudson/pcie.c
A src/southbridge/amd/agesa/hudson/ramtop.c
A src/southbridge/amd/agesa/hudson/reset.c
A src/southbridge/amd/agesa/hudson/resume.c
A src/southbridge/amd/agesa/hudson/sata.c
A src/southbridge/amd/agesa/hudson/sd.c
A src/southbridge/amd/agesa/hudson/sm.c
A src/southbridge/amd/agesa/hudson/smbus.c
A src/southbridge/amd/agesa/hudson/smbus.h
A src/southbridge/amd/agesa/hudson/smbus_spd.c
A src/southbridge/amd/agesa/hudson/smi.c
A src/southbridge/amd/agesa/hudson/smi.h
A src/southbridge/amd/agesa/hudson/smi_util.c
A src/southbridge/amd/agesa/hudson/smihandler.c
A src/southbridge/amd/agesa/hudson/spi.c
A src/southbridge/amd/agesa/hudson/usb.c
A src/southbridge/amd/cimx/Kconfig
A src/southbridge/amd/cimx/Makefile.inc
A src/southbridge/amd/cimx/sb800/Amd.h
A src/southbridge/amd/cimx/sb800/AmdSbLib.h
A src/southbridge/amd/cimx/sb800/Kconfig
A src/southbridge/amd/cimx/sb800/Makefile.inc
A src/southbridge/amd/cimx/sb800/SBPLATFORM.h
A src/southbridge/amd/cimx/sb800/acpi/audio.asl
A src/southbridge/amd/cimx/sb800/acpi/fch.asl
A src/southbridge/amd/cimx/sb800/acpi/lpc.asl
A src/southbridge/amd/cimx/sb800/acpi/misc_io.asl
A src/southbridge/amd/cimx/sb800/acpi/pcie.asl
A src/southbridge/amd/cimx/sb800/acpi/smbus.asl
A src/southbridge/amd/cimx/sb800/acpi/usb.asl
A src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
A src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
A src/southbridge/amd/cimx/sb800/bootblock.c
A src/southbridge/amd/cimx/sb800/cfg.c
A src/southbridge/amd/cimx/sb800/cfg.h
A src/southbridge/amd/cimx/sb800/chip.h
A src/southbridge/amd/cimx/sb800/early.c
A src/southbridge/amd/cimx/sb800/fadt.c
A src/southbridge/amd/cimx/sb800/fan.c
A src/southbridge/amd/cimx/sb800/fan.h
A src/southbridge/amd/cimx/sb800/gpio_oem.h
A src/southbridge/amd/cimx/sb800/late.c
A src/southbridge/amd/cimx/sb800/lpc.c
A src/southbridge/amd/cimx/sb800/lpc.h
A src/southbridge/amd/cimx/sb800/pci_devs.h
A src/southbridge/amd/cimx/sb800/ramtop.c
A src/southbridge/amd/cimx/sb800/reset.c
A src/southbridge/amd/cimx/sb800/sb_cimx.h
A src/southbridge/amd/cimx/sb800/smbus.c
A src/southbridge/amd/cimx/sb800/smbus.h
A src/southbridge/amd/cimx/sb800/smbus_spd.c
A src/southbridge/amd/cimx/sb800/smbus_spd.h
A src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/common/Makefile.inc
M src/southbridge/amd/pi/hudson/acpi/fch.asl
M src/southbridge/amd/pi/hudson/hudson.c
M src/vendorcode/amd/Makefile.inc
A src/vendorcode/amd/cimx/Makefile.inc
A src/vendorcode/amd/cimx/sb800/ACPILIB.c
A src/vendorcode/amd/cimx/sb800/ACPILIB.h
A src/vendorcode/amd/cimx/sb800/AMDLIB.c
A src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
A src/vendorcode/amd/cimx/sb800/AMDSBLIB.h
A src/vendorcode/amd/cimx/sb800/AZALIA.c
A src/vendorcode/amd/cimx/sb800/DISPATCHER.c
A src/vendorcode/amd/cimx/sb800/EC.c
A src/vendorcode/amd/cimx/sb800/ECLIB.c
A src/vendorcode/amd/cimx/sb800/ECfan.h
A src/vendorcode/amd/cimx/sb800/ECfanLIB.c
A src/vendorcode/amd/cimx/sb800/ECfanc.c
A src/vendorcode/amd/cimx/sb800/GEC.c
A src/vendorcode/amd/cimx/sb800/Gpp.c
A src/vendorcode/amd/cimx/sb800/IOLIB.c
A src/vendorcode/amd/cimx/sb800/LEGACY.c
A src/vendorcode/amd/cimx/sb800/MEMLIB.c
A src/vendorcode/amd/cimx/sb800/Makefile.inc
A src/vendorcode/amd/cimx/sb800/OEM.h
A src/vendorcode/amd/cimx/sb800/PCILIB.c
A src/vendorcode/amd/cimx/sb800/PMIO2LIB.c
A src/vendorcode/amd/cimx/sb800/PMIOLIB.c
A src/vendorcode/amd/cimx/sb800/SATA.c
A src/vendorcode/amd/cimx/sb800/SB800.h
A src/vendorcode/amd/cimx/sb800/SBCMN.c
A src/vendorcode/amd/cimx/sb800/SBDEF.h
A src/vendorcode/amd/cimx/sb800/SBMAIN.c
A src/vendorcode/amd/cimx/sb800/SBPELIB.c
A src/vendorcode/amd/cimx/sb800/SBPort.c
A src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
A src/vendorcode/amd/cimx/sb800/SBTYPE.h
A src/vendorcode/amd/cimx/sb800/SMM.c
A src/vendorcode/amd/cimx/sb800/SbModInf.c
A src/vendorcode/amd/cimx/sb800/USB.c
122 files changed, 19,210 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/71598/1
--
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Gerrit-Branch: master
Gerrit-Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888
Gerrit-Change-Number: 71598
Gerrit-PatchSet: 1
Gerrit-Owner: Damien Zammit
Gerrit-MessageType: newchange
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71597 )
Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468):
https://review.coreboot.org/c/coreboot/+/71597/comment/1f4c9aa9_bd0d714d
PS2, Line 11: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468):
https://review.coreboot.org/c/coreboot/+/71597/comment/d5e4732b_860a574e
PS2, Line 14: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468):
https://review.coreboot.org/c/coreboot/+/71597/comment/1e4f31a6_c0173957
PS2, Line 17: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468):
https://review.coreboot.org/c/coreboot/+/71597/comment/4cb2e6ca_4f731885
PS2, Line 20: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Gerrit-Branch: master
Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Gerrit-Change-Number: 71597
Gerrit-PatchSet: 2
Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sun, 01 Jan 2023 06:43:43 +0000
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71597 )
Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467):
https://review.coreboot.org/c/coreboot/+/71597/comment/0511bb1a_36b4da34
PS1, Line 11: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467):
https://review.coreboot.org/c/coreboot/+/71597/comment/8fa70c32_0915b9e2
PS1, Line 14: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467):
https://review.coreboot.org/c/coreboot/+/71597/comment/6e43af2a_edbbf2a6
PS1, Line 17: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467):
https://review.coreboot.org/c/coreboot/+/71597/comment/f2de7be0_796166d3
PS1, Line 20: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Possible unwrapped commit description (prefer a maximum 72 chars per line)
--
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Gerrit-Change-Number: 71597
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Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>
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Gerrit-Comment-Date: Sun, 01 Jan 2023 06:42:49 +0000
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71596 )
Change subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
......................................................................
src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/include/cpu/intel/post_codes.h
4 files changed, 22 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/71596/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index d838815..0283b5d 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -66,6 +66,12 @@
#define POST_ENTRY_C_START 0x13
/**
+ * \brief Entry into bootblock cache-as-RAM code
+ *
+ */
+#define POST_BOOTBLOCK_CAR 0x20
+
+/**
* \brief Entry into pci_scan_bus
*
* Entered pci_scan_bus()
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
index f828d6f..617da53 100644
--- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S
+++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -15,7 +15,7 @@
bootblock_pre_c_entry:
cache_as_ram:
- post_code(0x20)
+ post_code(POST_BOOTBLOCK_CAR)
/*
* Nothing to do here on qemu, RAM works just fine without any
* initialization.
@@ -103,7 +103,6 @@
#endif
before_c_entry:
- post_code(0x29)
call bootblock_c_entry_bist
/* Never returns */
.Lhlt:
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index 6a19b87..571feb4 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -34,7 +34,7 @@
movd %eax, %mm1
cache_as_ram:
- post_code(0x20)
+ post_code(POST_BOOTBLOCK_CAR)
/* Cache the rom and update the microcode */
cache_rom:
@@ -181,8 +181,6 @@
pushl %eax /* tsc[31:0] */
before_romstage:
- post_code(0x2a)
-
/* Call bootblock_c_entry(uint64_t base_timestamp) */
call bootblock_c_entry
diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h
index 3db0aeb..6c1ca79 100644
--- a/src/include/cpu/intel/post_codes.h
+++ b/src/include/cpu/intel/post_codes.h
@@ -3,7 +3,6 @@
#ifndef CPU_INTEL_CAR_POST_CODES_H
#define CPU_INTEL_CAR_POST_CODES_H
-#define POST_BOOTBLOCK_CAR 0x20
#define POST_SOC_SET_DEF_MTRR_TYPE 0x21
#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate
#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22
--
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Gerrit-PatchSet: 1
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
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Attention is currently required from: Jason Glenesk, Martin L Roth, Angel Pons.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71581 )
Change subject: Docs/releases: Update 4.17 & 4.18 notes to remove RESOURCE_ALLOCATOR_V3
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Change-Number: 71581
Gerrit-PatchSet: 1
Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71595 )
Change subject: inc/cpu/x86: Make sure the post_code macro is only used in asm
......................................................................
inc/cpu/x86: Make sure the post_code macro is only used in asm
Because this post_code macro could override the post_code function,
make sure it's only used in assembly files.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: If106ab9a3f8d635a013bfe793405914b20e2123c
---
M src/include/cpu/x86/post_code.h
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71595/1
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index db8f90d..c9680f7 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -5,6 +5,8 @@
#include <commonlib/console/post_codes.h>
+#if __ASSEMBLY__
+
#if CONFIG(POST_IO) && !(ENV_BOOTBLOCK && CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
#define post_code(value) \
movb $value, %al; \
@@ -14,4 +16,6 @@
#define post_code(value)
#endif
+#endif /* __ASSEMBLY__ */
+
#endif /* __X86_POST_CODE_H__ */
--
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