coreboot-gerrit January 2023

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[XL] Change in coreboot[master]: Revert "vendorcode/amd/agesa/family16: Drop unused platform"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71602 ) Change subject: Revert "vendorcode/amd/agesa/family16: Drop unused platform" ...................................................................... Revert "vendorcode/amd/agesa/family16: Drop unused platform" This reverts commit 7036ded25d3a051902862e2a7bdfe15916f0951d. Change-Id: I1782946f293c866c9a88f2a7824b0fe7dc4e6297 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/agesa/Makefile.inc A src/vendorcode/amd/agesa/f16kb/AGESA.h A src/vendorcode/amd/agesa/f16kb/AMD.h A src/vendorcode/amd/agesa/f16kb/Config/OptionApmInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionC6Install.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCditInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpbInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuCacheFlushOnHaltInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuCoreLevelingInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFamiliesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuSpecificServicesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCratInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionDmiInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionGfxRecoveryInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionHtInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionHtcInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionIdsInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionIoCstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionL3FeaturesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionLowPwrPstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMmioMapInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMsgBasedC1eInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPrefetchModeInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPreserveMailboxInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPsiInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPstateHpcModeInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionS3ScriptInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionSlitInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionSratInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionTdpLimitingInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionWheaInstall.h A src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h A src/vendorcode/amd/agesa/f16kb/Dispatcher.h A src/vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h A src/vendorcode/amd/agesa/f16kb/Include/CommonReturns.h A src/vendorcode/amd/agesa/f16kb/Include/Filecode.h A src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h A src/vendorcode/amd/agesa/f16kb/Include/GnbInterface.h A src/vendorcode/amd/agesa/f16kb/Include/Ids.h A src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h A src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h A src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h A src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h A src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h A src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h A src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h A src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h A src/vendorcode/amd/agesa/f16kb/Include/OptionPstate.h A src/vendorcode/amd/agesa/f16kb/Include/OptionSlit.h A src/vendorcode/amd/agesa/f16kb/Include/OptionSrat.h A src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h A src/vendorcode/amd/agesa/f16kb/Include/Options.h A src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h A src/vendorcode/amd/agesa/f16kb/Include/PlatformMemoryConfiguration.h A src/vendorcode/amd/agesa/f16kb/Include/Topology.h A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c A src/vendorcode/amd/agesa/f16kb/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/PreserveMailbox.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateGather.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEnvInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuServices.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdFch.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/FchPlatform.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbFam16.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNbCommonHardware.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htTopologies.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CRAT/mfCrat.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmlvddr3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnS3kb.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c A 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src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtlrdimm3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/ma.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/merrhdl.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mp.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mport.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mt.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h A src/vendorcode/amd/agesa/f16kb/gcccar.inc 729 files changed, 229,121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/71602/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1782946f293c866c9a88f2a7824b0fe7dc4e6297 Gerrit-Change-Number: 71602 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: Revert "vendorcode/amd/agesa: Drop unused common code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71601 ) Change subject: Revert "vendorcode/amd/agesa: Drop unused common code" ...................................................................... Revert "vendorcode/amd/agesa: Drop unused common code" This reverts commit 0f12381083fdfc7bb3e6f3b2ac5cd6247506c543. Change-Id: I2726767999b10e1fa3527a67719a4f7c1b93eb5c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/Makefile.inc A src/vendorcode/amd/agesa/Kconfig A src/vendorcode/amd/agesa/Makefile.inc A src/vendorcode/amd/agesa/common/Makefile.inc A src/vendorcode/amd/agesa/common/agesa-entry-cfg.h A src/vendorcode/amd/agesa/common/agesa-entry.c A src/vendorcode/amd/agesa/common/amdlib.c A src/vendorcode/amd/agesa/common/amdlib.h A src/vendorcode/amd/agesa/common/debug_util.c A src/vendorcode/amd/agesa/common/debug_util.h 10 files changed, 2,215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/71601/1 diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc index 9cdbe60..8cce5e6 100644 --- a/src/vendorcode/amd/Makefile.inc +++ b/src/vendorcode/amd/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += pi +subdirs-y += agesa subdirs-y += cimx diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..4bc6a3d --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config IDS_OPTIONS_HOOKED_UP + bool + help + to Kconfig options. + Historically, IDS configuration was defined in a mainboard-specific + `OptionsIds.h` header. Select this on platforms where IDS config is + hooked up to Kconfig options instead. + +if IDS_OPTIONS_HOOKED_UP + +config IDS_ENABLED + bool "Enable AGESA IDS (Integrated Debug Services) support" + default y + help + This is the master switch for the IDS sub-system. Use this option to + enable or remove the entire IDS feature set. This switch must be TRUE + for any of the other options to function. + +comment "Warning: IDS options may not work. Enable at your own risk!" + depends on IDS_ENABLED + +config IDS_CONTROL_ENABLED + bool "Enable IDS User Interface controls" + depends on IDS_ENABLED + help + This is the main switch for the IDS configuration controls. This + switch must be TRUE for any of the configuration controls to function. + + This seems to allow AGESA to retrieve settings from CMOS. + +config IDS_PERF_ANALYSIS + bool "Enable IDS performance analysis" + depends on IDS_ENABLED + help + This is the main switch for the IDS performance analysis controls, + macros and support code needed to enable time data gathering. This + switch must be TRUE for any of the performance analysis features to + function. + +config IDS_TRACING_ENABLED + bool "Enable IDS console" + depends on IDS_ENABLED + help + This is the main switch for the IDS console controls, macros and + support code needed to enable tracing of algorithms. This switch + must be TRUE for any of the tracing features to function. + +config IDS_TRACING_CONSOLE_SERIAL + bool "Use serial port as IDS console" + depends on IDS_TRACING_ENABLED + default DRIVERS_UART_8250IO && CONSOLE_SERIAL + help + Use an I/O-mapped serial port to output IDS messages. + +endif # IDS_OPTIONS_HOOKED_UP + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +endchoice + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc new file mode 100644 index 0000000..9d78195 --- /dev/null +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -0,0 +1,41 @@ + +ifeq ($(CONFIG_CPU_AMD_AGESA),y) + +subdirs-y += common + +classes-y += libagesa +libagesa-y = +libagesa-generic-ccopts += -D__LIBAGESA__ +libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +libagesa-generic-ccopts += -Wno-pragma-pack -Wno-unused-but-set-variable +libagesa-generic-ccopts += -Wno-implicit-fallthrough + +romstage-generic-ccopts += -Wno-pragma-pack +ramstage-generic-ccopts += -Wno-pragma-pack + +AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing + +CFLAGS_x86_32 += $(AGESA_CFLAGS) +CFLAGS_x86_64 += $(AGESA_CFLAGS) + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +$(eval $(call create_class_compiler,libagesa,x86_32)) +else +$(eval $(call create_class_compiler,libagesa,x86_64)) +endif + +$(obj)/libagesa.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + $(AR_libagesa) rcsDT $@ $+ + +romstage-libs += $(obj)/libagesa.a +ramstage-libs += $(obj)/libagesa.a + +# buildOpts should be in libagesa +$(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) +$(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) + +$(obj)/romstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) +$(obj)/ramstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) + +endif diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc new file mode 100644 index 0000000..a7ddc7f --- /dev/null +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -0,0 +1,36 @@ +#***************************************************************************** +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +romstage-y += agesa-entry.c +ramstage-y += agesa-entry.c + +libagesa-y += debug_util.c +libagesa-y += amdlib.c + +# Do not optimise performance-critical low-level IO for size with -Os, +# request -O2 with -falign-functions. + +$(obj)/libagesa/vendorcode/amd/agesa/common/amdlib.o: CFLAGS_libagesa += -O2 diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h new file mode 100644 index 0000000..3302574 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -0,0 +1,82 @@ +#ifndef AGESA_ENTRY_CFG_H +#define AGESA_ENTRY_CFG_H + + +#if ENV_RAMINIT + +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE + +#define AGESA_ENTRY_INIT_RESUME CONFIG(HAVE_ACPI_RESUME) + +#else + +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE CONFIG(HAVE_ACPI_RESUME) + +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE \ + (CONFIG(HAVE_ACPI_RESUME) || \ + CONFIG(ENABLE_MRC_CACHE)) + +#endif + +/* Not required. */ +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +/* Required for any multi-core. */ +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + +/* Deprecated, reference source is removed from the tree. */ +#define AGESA_ENTRY_INIT_RECOVERY FALSE + +/* Defaults below. */ + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#endif + +#endif /* AGESA_ENTRY_CFG_H */ diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c new file mode 100644 index 0000000..42f12b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -0,0 +1,165 @@ +#include <Porting.h> +#include <AMD.h> +#include <AGESA.h> + +#include "CommonReturns.h" + +#include <heapManager.h> +#include <CreateStruct.h> + +#include <Options.h> + +#include <agesa-entry-cfg.h> + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL } +}; + +CONST UINTN InitializerCount = ARRAY_SIZE(FuncParamsInfo); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; diff --git a/src/vendorcode/amd/agesa/common/amdlib.c b/src/vendorcode/amd/agesa/common/amdlib.c new file mode 100644 index 0000000..dbfdce8 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/amdlib.c @@ -0,0 +1,1266 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "amdlib.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE LIB_AMDLIB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT8 +ReadIo8 ( + IN UINT16 Address + ) +{ + return __inbyte (Address); +} +UINT16 +ReadIo16 ( + IN UINT16 Address + ) +{ + return __inword (Address); +} +UINT32 +ReadIo32 ( + IN UINT16 Address + ) +{ + return __indword (Address); +} +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ) +{ + __outbyte (Address, Data); +} +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ) +{ + __outword (Address, Data); +} +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ) +{ + __outdword (Address, Data); +} +STATIC +UINT64 SetFsBase ( + UINT64 address + ) +{ + UINT64 hwcr; + hwcr = __readmsr (0xC0010015); + __writemsr (0xC0010015, hwcr | 1 << 17); + __writemsr (0xC0000100, address); + return hwcr; +} +STATIC +VOID +RestoreHwcr ( + UINT64 + value + ) +{ + __writemsr (0xC0010015, value); +} +UINT8 +Read64Mem8 ( + IN UINT64 Address + ) +{ + UINT8 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT8 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsbyte (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT16 +Read64Mem16 ( + IN UINT64 Address + ) +{ + UINT16 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT16 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsword (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT32 +Read64Mem32 ( + IN UINT64 Address + ) +{ + UINT32 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT32 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsdword (0); + RestoreHwcr (hwcrSave); + return dataRead; + } +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT8 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsbyte (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT16 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT32 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsdword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ) +{ + *Value = 0; + switch (RegNum){ + case CR4_REG: + *Value = __readcr4 (); + break; + case DR0_REG: + *Value = __readdr (0); + break; + case DR1_REG: + *Value = __readdr (1); + break; + case DR2_REG: + *Value = __readdr (2); + break; + case DR3_REG: + *Value = __readdr (3); + break; + case DR7_REG: + *Value = __readdr (7); + break; + default: + *Value = -1; + break; + } +} +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ) +{ + switch (RegNum){ + case CR4_REG: + __writecr4 (Value); + break; + case DR0_REG: + __writedr (0, Value); + break; + case DR1_REG: + __writedr (1, Value); + break; + case DR2_REG: + __writedr (2, Value); + break; + case DR3_REG: + __writedr (3, Value); + break; + case DR7_REG: + __writedr (7, Value); + break; + default: + break; + } +} +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ) +{ + __wbinvd (); +} +VOID +LibAmdHDTBreakPoint ( + VOID + ) +{ + __writemsr (0xC001100A, __readmsr (0xC001100A) | 1); + __debugbreak (); // do you really need icebp? If so, go back to asm code +} +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ) +{ + UINTN Index; + for (Index = 0; Index < 32; Index++){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value +) +{ + uint8_t bit = 31; + do { + if (value & (1 << 31)) + return bit; + + value <<= 1; + bit--; + + } while (value != 0); + + return 0xFF; /* Error code indicating no bit found */ +} + +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + *Value = __readmsr (MsrAddress); +} +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + CONST IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __writemsr (MsrAddress, *Value); +} +void LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA* Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} +UINT64 +ReadTSC ( + VOID + ) +{ + return __rdtsc (); +} +VOID +LibAmdSimNowEnterDebugger ( + VOID + ) +{ + STATIC CONST UINT8 opcode [] = {0x60, // pushad + 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2 + 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B + 0x0F, 0xA2, // cpuid + 0x61, // popad + 0xC3 // ret + }; + ((VOID (*)(VOID)) (size_t) opcode) (); // call the function +} + +#ifdef __SSE3__ +VOID F10RevDProbeFilterCritical ( + IN PCI_ADDR PciAddress, + IN UINT32 PciRegister + ) +{ + UINT64 msrsave; + msrsave = __readmsr (0xC001001F); + __writemsr (0xC001001F, msrsave | 1ULL << 46); // EnableCf8ExtCfg + _mm_mfence (); + __outdword (0xCF8, PciAddress.AddressValue); + _mm_mfence (); + __outdword (0xCFC, PciRegister | 2); + _mm_mfence (); + __writemsr (0xC001001F, msrsave); +} + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ) +{ + UINT64 hwcrSave; + UINT8 *address32; + UINTN Index; + address32 = 0; + hwcrSave = SetFsBase (Address); + for (Index = 0; Index < Count; Index++){ + _mm_mfence (); + _mm_clflush_fs (&address32 [Index * 64]); + } + RestoreHwcr (hwcrSave); +} +#endif //__SSE3__ + +VOID +StopHere ( + VOID + ) +{ + VOLATILE UINTN x = 1; + while (x); +} + +VOID +LibAmdFinit() +{ + /* TODO: finit */ + __asm__ volatile ("finit"); +} +/*---------------------------------------------------------------------------------------*/ +/** + * Read IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to save data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = ReadIo8 (IoAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = ReadIo16 (IoAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = ReadIo32 (IoAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + WriteIo8 (IoAddress, *(UINT8 *) Value); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + WriteIo16 (IoAddress, *(UINT16 *) Value); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + WriteIo32 (IoAddress, *(UINT32 *) Value); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * IO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value = 0; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll IO register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data Data to compare + * @param[in] DataMask And mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = Read64Mem8 (MemAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = Read64Mem16 (MemAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = Read64Mem32 (MemAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Write64Mem8 (MemAddress, *((UINT8 *) Value)); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Write64Mem16 (MemAddress, *((UINT16 *) Value)); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Write64Mem32 (MemAddress, *((UINT32 *) Value)); + break; + default: + ASSERT (FALSE); + break; + } +} +/*---------------------------------------------------------------------------------------*/ +/** + * Memory/MMIO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll Mmio + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000ull; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000ull; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * PCI read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data OR Data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll PCI config space register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get MMIO base address for PCI accesses + * + * @param[out] MmioAddress PCI MMIO base address + * @param[out] MmioSize Size of region in bytes + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE MmioAddress/MmioSize are valid + */ +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN MmioIsEnabled; + UINT32 EncodedSize; + UINT64 MsrReg; + + ASSERT (StdHeader != NULL); + + MmioIsEnabled = FALSE; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); + if ((MsrReg & BIT0) != 0) { + *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull; + EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2); + *MmioSize = ((1 << EncodedSize) * 0x100000); + MmioIsEnabled = TRUE; + } + return MmioIsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[out] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + LibAmdPciRead (AccessWidth32, Address, Value, StdHeader); + *Value >>= Lowbit; // Shift + + // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 Mask; + + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32) 0xFFFFFFFF; + } + + LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader); + Temp &= ~(Mask << Lowbit); + Temp |= (*Value & Mask) << Lowbit; + LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate next capability pointer + * + * Given a SBDFO this routine will find the next PCI capabilities list entry. + * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is + * returned. + * To start a new search from the head of the list, specify a SBDFO with an offset of zero. + * + * @param[in,out] Address Pci address + * @param[in] StdHeader Standard configuration header + */ + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Base; + UINT32 Offset; + UINT32 Temp; + PCI_ADDR TempAddress; + + ASSERT (Address != NULL); + ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO); + + Base.AddressValue = Address->AddressValue; + Offset = Base.Address.Register; + Base.Address.Register = 0; + + Address->AddressValue = (UINT32) ILLEGAL_SBDFO; + + // Verify that the SBDFO points to a valid PCI device SANITY CHECK + LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader); + if (Temp == 0xFFFFFFFF) { + ASSERT (FALSE); + return; // There is no device at this address + } + + // Verify that the device supports a capability list + TempAddress.AddressValue = Base.AddressValue + 0x04; + LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader); + if (Temp == 0) { + return; // This PCI device does not support capability lists + } + + if (Offset != 0) { + // If we are continuing on an existing list + TempAddress.AddressValue = Base.AddressValue + Offset; + LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader); + } else { + // We are starting on a new list + TempAddress.AddressValue = Base.AddressValue + 0x34; + LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader); + } + + if (Temp == 0) { + return; // We have reached the end of the capabilities list + } + + // Error detection and recovery- The statement below protects against + // PCI devices with broken PCI capabilities lists. Detect a pointer + // that is not uint32 aligned, points into the first 64 reserved DWORDs + // or points back to itself. + if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) { + ASSERT (FALSE); + return; + } + + Address->AddressValue = Base.AddressValue + Temp; + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set memory with value + * + * + * @param[in,out] Destination Pointer to memory range + * @param[in] Value Value to set memory with + * @param[in] FillLength Size of the memory range + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + ASSERT (StdHeader != NULL); + Dest = Destination; + while ((FillLength--) != 0) { + *Dest++ = Value; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Copy memory + * + * + * @param[in,out] Destination Pointer to destination buffer + * @param[in] Source Pointer to source buffer + * @param[in] CopyLength buffer length + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + CONST UINT8 *SourcePtr; + ASSERT (StdHeader != NULL); + Dest = Destination; + SourcePtr = Source; + while ((CopyLength--) != 0) { + *Dest++ = *SourcePtr++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] StdHeader Standard configuration header (Optional) + */ + +// Returns the package type mask for the processor +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorPackageType; + CPUID_DATA CpuId; + + LibAmdCpuidRead (0x80000001, &CpuId, StdHeader); + ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + return (UINT32) (1 << ProcessorPackageType); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @param[in] Data data + * @param[in] DataMask data + * @param[out] TemData typecast data + * @param[out] TempDataMask typecast data + */ + + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *TemData = (UINT32)*(UINT8 *) Data; + *TempDataMask = (UINT32)*(UINT8 *) DataMask; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *TemData = (UINT32)*(UINT16 *) Data; + *TempDataMask = (UINT32)*(UINT16 *) DataMask; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *TemData = *(UINT32 *) Data; + *TempDataMask = *(UINT32 *) DataMask; + break; + default: + IDS_ERROR_TRAP; + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @retval Width in number of bytes + */ + + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ) +{ + UINT8 Width; + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Width = 1; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Width = 2; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Width = 4; + break; + case AccessWidth64: + case AccessS3SaveWidth64: + Width = 8; + break; + default: + Width = 0; + IDS_ERROR_TRAP; + break; + } + return Width; +} + +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} + +UINT8 +ReadNumberOfCpuCores( + VOID + ) +{ + CPUID_DATA Value; + CpuidRead (0x80000008, &Value); + return Value.ECX_Reg & 0xff; +} diff --git a/src/vendorcode/amd/agesa/common/amdlib.h b/src/vendorcode/amd/agesa/common/amdlib.h new file mode 100644 index 0000000..5ba3952 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/amdlib.h @@ -0,0 +1,398 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _AMD_LIB_H_ +#define _AMD_LIB_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +// Reg Values for ReadCpuReg and WriteCpuReg +#define CR0_REG 0x00 +#define CR4_REG 0x04 +#define DR0_REG 0x10 +#define DR1_REG 0x11 +#define DR2_REG 0x12 +#define DR3_REG 0x13 +#define DR7_REG 0x17 + +UINT8 +ReadIo8 ( + IN UINT16 Address + ); + +UINT16 +ReadIo16 ( + IN UINT16 Address + ); + +UINT32 +ReadIo32 ( + IN UINT16 Address + ); + +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ); + +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ); + +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ); + +UINT8 +Read64Mem8 ( + IN UINT64 Address + ); + +UINT16 +Read64Mem16 ( + IN UINT64 Address + ); + +UINT32 +Read64Mem32 ( + IN UINT64 Address + ); + +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ); + +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ); + +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ); + +UINT64 +ReadTSC ( + VOID + ); + +// MSR +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + CONST IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// IO +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Memory or MMIO +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// PCI +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// CPUID +VOID +LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Utility Functions +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value + ); +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ); + +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ); +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ); + +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ); + +VOID +LibAmdSimNowEnterDebugger (VOID); + +VOID +LibAmdHDTBreakPoint (VOID); + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ); + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ); + +VOID F10RevDProbeFilterCritical ( + IN PCI_ADDR PciAddress, + IN UINT32 PciRegister + ); + +VOID +LibAmdFinit ( + VOID + ); + +VOID +StopHere ( + VOID + ); + +/* For f14 or older. */ +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ); + +UINT8 +ReadNumberOfCpuCores( + VOID + ); + +/* From 16kb, no implementation supplied. */ +VOID +LibAmdFnclex ( + VOID); + +VOID +LibAmdReadMxcsr ( + OUT UINT32 *Value + ); +VOID +LibAmdWriteMxcsr ( + IN UINT32 *Value + ); + + +#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000..29d0841 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include <AGESA.h> +#include <AMD.h> +#include <heapManager.h> + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000..a8d9a33 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/71601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2726767999b10e1fa3527a67719a4f7c1b93eb5c Gerrit-Change-Number: 71601 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: Revert "cpu/amd/agesa: Remove leftover code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71600 ) Change subject: Revert "cpu/amd/agesa: Remove leftover code" ...................................................................... Revert "cpu/amd/agesa: Remove leftover code" This reverts commit 81a4fefce223ba358310aec2d988484202c176e2. Change-Id: Icf2b15a158fc4a22e07d0051e4f23dd804a4a148 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/amd/Kconfig M src/cpu/amd/Makefile.inc A src/cpu/amd/agesa/Kconfig A src/cpu/amd/agesa/Makefile.inc A src/cpu/amd/smm/Makefile.inc A src/cpu/amd/smm/smm_init.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/Kconfig M src/vendorcode/amd/Kconfig M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 14 files changed, 191 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/71600/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 18bc961..7f99137 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -101,7 +101,7 @@ static inline bool cpu_is_amd(void) { - return CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON); + return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON); } static inline bool cpu_is_intel(void) diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 0369ebd..db8989d 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1 +1,2 @@ +source "src/cpu/amd/agesa/Kconfig" source "src/cpu/amd/pi/Kconfig" diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 94089bd..5c07a66 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -1 +1,2 @@ +subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa subdirs-$(CONFIG_CPU_AMD_PI) += pi diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig new file mode 100644 index 0000000..d46d2ed --- /dev/null +++ b/src/cpu/amd/agesa/Kconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CPU_AMD_AGESA + bool + default n + select ARCH_X86 + select DRIVERS_AMD_PI + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME + select SSE2 + select CACHE_MRC_SETTINGS + +if CPU_AMD_AGESA + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in AGESA vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config ENABLE_MRC_CACHE + bool "Use cached memory configuration" + default n + select SPI_FLASH + help + Try to restore memory training results + from non-volatile memory. + +endif # CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc new file mode 100644 index 0000000..4cacc51 --- /dev/null +++ b/src/cpu/amd/agesa/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc new file mode 100644 index 0000000..97a6694 --- /dev/null +++ b/src/cpu/amd/smm/Makefile.inc @@ -0,0 +1,2 @@ + +ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c new file mode 100644 index 0000000..75dd4506 --- /dev/null +++ b/src/cpu/amd/smm/smm_init.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <cpu/x86/smi_deprecated.h> +#include <string.h> + +void smm_init(void) +{ + msr_t msr, syscfg_orig, mtrr_aseg_orig; + + /* Back up MSRs for later restore */ + syscfg_orig = rdmsr(SYSCFG_MSR); + mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); + + /* MTRR changes don't like an enabled cache */ + disable_cache(); + + msr = syscfg_orig; + + /* Allow changes to MTRR extended attributes */ + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + /* turn the extended attributes off until we fix + * them so A0000 is routed to memory + */ + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* set DRAM access to 0xa0000 */ + msr.lo = 0x18181818; + msr.hi = 0x18181818; + wrmsr(MTRR_FIX_16K_A0000, msr); + + /* enable the extended features */ + msr = syscfg_orig; + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + enable_cache(); + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start); + wbinvd(); + disable_cache(); + + /* Restore SYSCFG and MTRR */ + wrmsr(SYSCFG_MSR, syscfg_orig); + wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); + enable_cache(); + + /* CPU MSR are set in CPU init */ +} + +void smm_init_completion(void) +{ +} diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index fbbf044..6d80c4c 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -21,4 +21,7 @@ ramstage-y += heapmanager.c ramstage-y += acpi_tables.c +romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c +ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c + endif diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c index c4a4e18..1c09d3f 100644 --- a/src/drivers/amd/agesa/acpi_tables.c +++ b/src/drivers/amd/agesa/acpi_tables.c @@ -8,7 +8,8 @@ /* Fields were removed from the structure and we cannot add them back * without new builds of the binaryPI blobs. */ -#if CONFIG(NORTHBRIDGE_AMD_PI_00730F01) +#if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \ + CONFIG(NORTHBRIDGE_AMD_PI_00730F01) #define HAS_ACPI_SRAT TRUE #define HAS_ACPI_SLIT TRUE diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index b819dff..2ff4d44 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -14,6 +14,10 @@ #include <AMD.h> +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) +#include "Dispatcher.h" +#endif + #if ENV_RAMINIT #include <PlatformMemoryConfiguration.h> CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; @@ -21,6 +25,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader) { +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) const char ModuleIdentifier[] = AGESA_ID; const void *agesa, *image; size_t file_size; @@ -32,6 +37,7 @@ image = LibAmdLocateImage(agesa, agesa + file_size, 4096, ModuleIdentifier); StdHeader->ImageBasePtr = (void *)image; +#endif } void agesa_set_interface(struct sysinfo *cb) @@ -40,13 +46,15 @@ cb->StdHeader.CalloutPtr = GetBiosCallout; - agesa_locate_image(&cb->StdHeader); - AMD_IMAGE_HEADER *image = - (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; - ASSERT(image); - AMD_MODULE_HEADER *module = - (void *)(uintptr_t)image->ModuleInfoOffset; - ASSERT(module && module->ModuleDispatcher); + if (CONFIG(CPU_AMD_AGESA_BINARY_PI)) { + agesa_locate_image(&cb->StdHeader); + AMD_IMAGE_HEADER *image = + (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; + ASSERT(image); + AMD_MODULE_HEADER *module = + (void *)(uintptr_t)image->ModuleInfoOffset; + ASSERT(module && module->ModuleDispatcher); + } } AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, @@ -54,9 +62,14 @@ { MODULE_ENTRY dispatcher; +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) + dispatcher = AmdAgesaDispatcher; +#endif +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr; AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset; dispatcher = module->ModuleDispatcher; +#endif StdHeader->Func = func; return dispatcher(StdHeader); diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ccfbbf..6f6e3d63 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA bool + default CPU_AMD_AGESA if NORTHBRIDGE_AMD_AGESA diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index b095916..2378616 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -1,10 +1,42 @@ # SPDX-License-Identifier: GPL-2.0-only -if CPU_AMD_PI || SOC_AMD_PI +if CPU_AMD_AGESA || CPU_AMD_PI || SOC_AMD_PI menu "AMD Platform Initialization" +choice + prompt "AGESA source" + default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI + default CPU_AMD_AGESA_BINARY_PI if SOC_AMD_PI + default CPU_AMD_AGESA_OPENSOURCE if CPU_AMD_AGESA + help + Select the method for including the AMD Platform Initialization + code into coreboot. Platform Initialization code is required for + all AMD processors. + +config CPU_AMD_AGESA_BINARY_PI + bool "binary PI" + help + Use a binary PI package. Generally, these will be stored in the + "3rdparty/blobs" directory. For some processors, these must be obtained + directly from AMD Embedded Processors Group + (http://www.amd.com/embedded). + +config CPU_AMD_AGESA_OPENSOURCE + bool "open-source AGESA" + help + Build the PI package ("AGESA") from source code in the "vendorcode" + directory. + +endchoice + +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + +if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" +endif config AGESA_EXTRA_TIMESTAMPS bool "Add instrumentation for AGESA calls" diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 96c3ea9..71898a3 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -85,7 +85,7 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -classes-y += libagesa +classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) @@ -136,7 +136,7 @@ $(AGESA_POST_MEM_ELF_RMOD): $(AGESA_POST_MEM_ELF) -cbfs-files-y += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME) $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE) $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip @@ -144,7 +144,7 @@ # 64 byte alignment. $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096 -cbfs-files-y += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG) @@ -158,7 +158,7 @@ files_added:: warn_no_agesa else -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) $(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE) ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index d36671a..9b4659e 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -108,7 +108,7 @@ agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c) endif -classes-y += libagesa +classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) @@ -135,7 +135,7 @@ ####################################################################### -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) $(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) -- To view, visit https://review.coreboot.org/c/coreboot/+/71600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf2b15a158fc4a22e07d0051e4f23dd804a4a148 Gerrit-Change-Number: 71600 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: Revert "nb/amd/agesa: Remove leftover code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71599 ) Change subject: Revert "nb/amd/agesa: Remove leftover code" ...................................................................... Revert "nb/amd/agesa: Remove leftover code" This reverts commit 1a010236cf922fc28cfb36b604bdf17a9ea3cb82. Change-Id: If26ce3136f809d5b0714fc344ddff1f8df3789bc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/northbridge/amd/agesa/Kconfig 1 file changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/71599/1 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig new file mode 100644 index 0000000..2ccfbbf --- /dev/null +++ b/src/northbridge/amd/agesa/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_AMD_AGESA + bool + +if NORTHBRIDGE_AMD_AGESA + +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0x80000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present, for example, graphic cards. + +config CONSOLE_VGA_MULTI + bool + default n + +config S3_VGA_ROM_RUN + bool + default n + +source "src/northbridge/amd/agesa/*/Kconfig" + +# TODO: Reservation for heap seems excessive +config HEAP_SIZE + hex + default 0xc0000 + +endif # NORTHBRIDGE_AMD_AGESA -- To view, visit https://review.coreboot.org/c/coreboot/+/71599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If26ce3136f809d5b0714fc344ddff1f8df3789bc Gerrit-Change-Number: 71599 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: Revert "sb/amd: Remove dropped platforms"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71598 ) Change subject: Revert "sb/amd: Remove dropped platforms" ...................................................................... Revert "sb/amd: Remove dropped platforms" This reverts commit 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051. Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/state_machine.h A src/southbridge/amd/agesa/Kconfig A src/southbridge/amd/agesa/Makefile.inc A src/southbridge/amd/agesa/hudson/Kconfig A src/southbridge/amd/agesa/hudson/Makefile.inc A src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl A src/southbridge/amd/agesa/hudson/acpi/audio.asl A src/southbridge/amd/agesa/hudson/acpi/fch.asl A src/southbridge/amd/agesa/hudson/acpi/lpc.asl A src/southbridge/amd/agesa/hudson/acpi/pci_int.asl A src/southbridge/amd/agesa/hudson/acpi/pcie.asl A src/southbridge/amd/agesa/hudson/acpi/smbus.asl A src/southbridge/amd/agesa/hudson/acpi/usb.asl A src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h A src/southbridge/amd/agesa/hudson/amd_pci_int_types.h A src/southbridge/amd/agesa/hudson/bootblock.c A src/southbridge/amd/agesa/hudson/chip.h A src/southbridge/amd/agesa/hudson/early_setup.c A src/southbridge/amd/agesa/hudson/enable_usbdebug.c A src/southbridge/amd/agesa/hudson/fadt.c A src/southbridge/amd/agesa/hudson/hda.c A src/southbridge/amd/agesa/hudson/hudson.c A src/southbridge/amd/agesa/hudson/hudson.h A src/southbridge/amd/agesa/hudson/ide.c A src/southbridge/amd/agesa/hudson/imc.c A src/southbridge/amd/agesa/hudson/imc.h A src/southbridge/amd/agesa/hudson/lpc.c A src/southbridge/amd/agesa/hudson/pci.c A src/southbridge/amd/agesa/hudson/pci_devs.h A src/southbridge/amd/agesa/hudson/pcie.c A src/southbridge/amd/agesa/hudson/ramtop.c A src/southbridge/amd/agesa/hudson/reset.c A src/southbridge/amd/agesa/hudson/resume.c A src/southbridge/amd/agesa/hudson/sata.c A src/southbridge/amd/agesa/hudson/sd.c A src/southbridge/amd/agesa/hudson/sm.c A src/southbridge/amd/agesa/hudson/smbus.c A src/southbridge/amd/agesa/hudson/smbus.h A src/southbridge/amd/agesa/hudson/smbus_spd.c A src/southbridge/amd/agesa/hudson/smi.c A src/southbridge/amd/agesa/hudson/smi.h A src/southbridge/amd/agesa/hudson/smi_util.c A src/southbridge/amd/agesa/hudson/smihandler.c A src/southbridge/amd/agesa/hudson/spi.c A src/southbridge/amd/agesa/hudson/usb.c A src/southbridge/amd/cimx/Kconfig A src/southbridge/amd/cimx/Makefile.inc A src/southbridge/amd/cimx/sb800/Amd.h A src/southbridge/amd/cimx/sb800/AmdSbLib.h A src/southbridge/amd/cimx/sb800/Kconfig A src/southbridge/amd/cimx/sb800/Makefile.inc A src/southbridge/amd/cimx/sb800/SBPLATFORM.h A src/southbridge/amd/cimx/sb800/acpi/audio.asl A src/southbridge/amd/cimx/sb800/acpi/fch.asl A src/southbridge/amd/cimx/sb800/acpi/lpc.asl A src/southbridge/amd/cimx/sb800/acpi/misc_io.asl A src/southbridge/amd/cimx/sb800/acpi/pcie.asl A src/southbridge/amd/cimx/sb800/acpi/smbus.asl A src/southbridge/amd/cimx/sb800/acpi/usb.asl A src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h A src/southbridge/amd/cimx/sb800/amd_pci_int_types.h A src/southbridge/amd/cimx/sb800/bootblock.c A src/southbridge/amd/cimx/sb800/cfg.c A src/southbridge/amd/cimx/sb800/cfg.h A src/southbridge/amd/cimx/sb800/chip.h A src/southbridge/amd/cimx/sb800/early.c A src/southbridge/amd/cimx/sb800/fadt.c A src/southbridge/amd/cimx/sb800/fan.c A src/southbridge/amd/cimx/sb800/fan.h A src/southbridge/amd/cimx/sb800/gpio_oem.h A src/southbridge/amd/cimx/sb800/late.c A src/southbridge/amd/cimx/sb800/lpc.c A src/southbridge/amd/cimx/sb800/lpc.h A src/southbridge/amd/cimx/sb800/pci_devs.h A src/southbridge/amd/cimx/sb800/ramtop.c A src/southbridge/amd/cimx/sb800/reset.c A src/southbridge/amd/cimx/sb800/sb_cimx.h A src/southbridge/amd/cimx/sb800/smbus.c A src/southbridge/amd/cimx/sb800/smbus.h A src/southbridge/amd/cimx/sb800/smbus_spd.c A src/southbridge/amd/cimx/sb800/smbus_spd.h A src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/common/Makefile.inc M src/southbridge/amd/pi/hudson/acpi/fch.asl M src/southbridge/amd/pi/hudson/hudson.c M src/vendorcode/amd/Makefile.inc A src/vendorcode/amd/cimx/Makefile.inc A src/vendorcode/amd/cimx/sb800/ACPILIB.c A src/vendorcode/amd/cimx/sb800/ACPILIB.h A src/vendorcode/amd/cimx/sb800/AMDLIB.c A src/vendorcode/amd/cimx/sb800/AMDSBLIB.c A src/vendorcode/amd/cimx/sb800/AMDSBLIB.h A src/vendorcode/amd/cimx/sb800/AZALIA.c A src/vendorcode/amd/cimx/sb800/DISPATCHER.c A src/vendorcode/amd/cimx/sb800/EC.c A src/vendorcode/amd/cimx/sb800/ECLIB.c A src/vendorcode/amd/cimx/sb800/ECfan.h A src/vendorcode/amd/cimx/sb800/ECfanLIB.c A src/vendorcode/amd/cimx/sb800/ECfanc.c A src/vendorcode/amd/cimx/sb800/GEC.c A src/vendorcode/amd/cimx/sb800/Gpp.c A src/vendorcode/amd/cimx/sb800/IOLIB.c A src/vendorcode/amd/cimx/sb800/LEGACY.c A src/vendorcode/amd/cimx/sb800/MEMLIB.c A src/vendorcode/amd/cimx/sb800/Makefile.inc A src/vendorcode/amd/cimx/sb800/OEM.h A src/vendorcode/amd/cimx/sb800/PCILIB.c A src/vendorcode/amd/cimx/sb800/PMIO2LIB.c A src/vendorcode/amd/cimx/sb800/PMIOLIB.c A src/vendorcode/amd/cimx/sb800/SATA.c A src/vendorcode/amd/cimx/sb800/SB800.h A src/vendorcode/amd/cimx/sb800/SBCMN.c A src/vendorcode/amd/cimx/sb800/SBDEF.h A src/vendorcode/amd/cimx/sb800/SBMAIN.c A src/vendorcode/amd/cimx/sb800/SBPELIB.c A src/vendorcode/amd/cimx/sb800/SBPort.c A src/vendorcode/amd/cimx/sb800/SBSUBFUN.h A src/vendorcode/amd/cimx/sb800/SBTYPE.h A src/vendorcode/amd/cimx/sb800/SMM.c A src/vendorcode/amd/cimx/sb800/SbModInf.c A src/vendorcode/amd/cimx/sb800/USB.c 122 files changed, 19,210 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/71598/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888 Gerrit-Change-Number: 71598 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
by Subrata Banik (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Sridhar Siricilla, Pratikkumar V Prajapati. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71569 ) Change subject: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Gerrit-Change-Number: 71569 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 08:43:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71597 ) Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 2: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468): https://review.coreboot.org/c/coreboot/+/71597/comment/1f4c9aa9_bd0d714d PS2, Line 11: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468): https://review.coreboot.org/c/coreboot/+/71597/comment/d5e4732b_860a574e PS2, Line 14: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468): https://review.coreboot.org/c/coreboot/+/71597/comment/1e4f31a6_c0173957 PS2, Line 17: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167468): https://review.coreboot.org/c/coreboot/+/71597/comment/4cb2e6ca_4f731885 PS2, Line 20: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Gerrit-Change-Number: 71597 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 06:43:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71597 ) Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 1: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467): https://review.coreboot.org/c/coreboot/+/71597/comment/0511bb1a_36b4da34 PS1, Line 11: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467): https://review.coreboot.org/c/coreboot/+/71597/comment/8fa70c32_0915b9e2 PS1, Line 14: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467): https://review.coreboot.org/c/coreboot/+/71597/comment/6e43af2a_edbbf2a6 PS1, Line 17: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167467): https://review.coreboot.org/c/coreboot/+/71597/comment/f2de7be0_796166d3 PS1, Line 20: cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Gerrit-Change-Number: 71597 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 06:42:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
by Elyes Haouas (Code Review) 01 Jan '23

01 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71597 ) Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory ...................................................................... vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc 1 file changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/71597/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 96c3ea9..2ac4987 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -32,7 +32,6 @@ BINARY_PI_INC = -I$(AGESA_ROOT) BINARY_PI_INC += -I$(AGESA_ROOT)/binaryPI BINARY_PI_INC += -I$(AGESA_ROOT)/Include -BINARY_PI_INC += -I$(AGESA_ROOT)/Lib BINARY_PI_INC += -I$(AGESA_ROOT)/Proc BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Common BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU -- To view, visit https://review.coreboot.org/c/coreboot/+/71597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Gerrit-Change-Number: 71597 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: apollolake/include/soc/meminit.h: Add missing stdbool
by 9elements QA (Code Review) 01 Jan '23

01 Jan '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71245 ) Change subject: apollolake/include/soc/meminit.h: Add missing stdbool ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 2 / 14 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/142898 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/142897 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/142896 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142895 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/142894 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/142893 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/142892 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/142891 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/142890 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/142889 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142888 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/142887 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/142886 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/142885 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/71245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I317faf322a7e73b706724802d99815ab50e655e2 Gerrit-Change-Number: 71245 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Jan 2023 05:03:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2023