coreboot-gerrit January 2023

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[XL] Change in coreboot[master]: mb/hp/t620: Add clone of biostar/a68n-5200
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71608 ) Change subject: mb/hp/t620: Add clone of biostar/a68n-5200 ...................................................................... Patch Set 1: (13 comments) File src/mainboard/hp/t620/BiosCallOuts.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/06edbb8d_468065ec PS1, Line 11: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/563dc4f4_8948154e PS1, Line 45: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/9b08aa43_f2580f15 PS1, Line 46: {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/84941c55_311018c2 PS1, Line 47: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} "(foo*)" should be "(foo *)" File src/mainboard/hp/t620/OemCustomize.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/604632cb_ebf3b780 PS1, Line 118: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/1a0b2ce7_a4f5e573 PS1, Line 119: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/2a3a8605_2d90c5d8 PS1, Line 120: MOTHER_BOARD_LAYERS(LAYERS_4), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/f33010bd_80927217 PS1, Line 122: MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/30e4ebf9_b854cce8 PS1, Line 123: CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/bdad75f8_9a9f7fd1 PS1, Line 124: ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/4cdb037c_0e074be0 PS1, Line 125: CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/6ad023f3_9a3608a0 PS1, Line 127: PSO_END please, no spaces at the start of a line File src/mainboard/hp/t620/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167482): https://review.coreboot.org/c/coreboot/+/71608/comment/75846232_6557eb3b PS1, Line 81: if (sum != pirq->checksum) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/71608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 71608 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:16:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: Revert "{cpu/nb}/amd/family16: Remove platform"
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71603 ) Change subject: Revert "{cpu/nb}/amd/family16: Remove platform" ...................................................................... Patch Set 1: (12 comments) File src/northbridge/amd/agesa/family16kb/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/606ec202_1c46d2bb PS1, Line 7: { open brace '{' following struct go on the same line File src/northbridge/amd/agesa/family16kb/northbridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/1a460bcb_55829456 PS1, Line 51: if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/f8a58b6c_00317cc3 PS1, Line 72: if (dev && dev->enabled) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/dc59373c_6a20d164 PS1, Line 300: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/b4e17c68_d0ab5da2 PS1, Line 315: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/9db3d3f7_e3f78b27 PS1, Line 393: if (res) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/ae4e67a7_e13bbd03 PS1, Line 438: if (base_k > 4 * 1024 * 1024) break; // don't need to go to check trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/ed0d28df_d653711b PS1, Line 462: for (link = dev->link_list; link; link = link->next) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/7d66dc8d_5ca6f77f PS1, Line 525: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/10e79092_3a964b5d PS1, Line 541: if (link->children) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/860a4095_6a32656f PS1, Line 592: if (ApicIdCoreIdSize) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167477): https://review.coreboot.org/c/coreboot/+/71603/comment/1b298054_dd5fc9ff PS1, Line 699: if (dev->path.type == DEVICE_PATH_DOMAIN) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/71603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Gerrit-Change-Number: 71603 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:15:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: Revert "sb/amd: Remove dropped platforms"
by build bot (Jenkins) (Code Review) 01 Jan '23

01 Jan '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71598 ) Change subject: Revert "sb/amd: Remove dropped platforms" ...................................................................... Patch Set 1: (134 comments) File src/southbridge/amd/agesa/hudson/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/20ed09a0_f787d4bb PS1, Line 7: { open brace '{' following struct go on the same line File src/southbridge/amd/agesa/hudson/enable_usbdebug.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2d2656c5_d0a9f7aa PS1, Line 38: reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ Possible repeated word: 'Port' File src/southbridge/amd/agesa/hudson/lpc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3df1a0ae_ca589f30 PS1, Line 50: on on LPC, it holds PCI grant, so no LPC slave cycle can Possible repeated word: 'on' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b9614ff1_bcc8ac95 PS1, Line 247: if ((var_num > 0) && ((base >= reg_var[0]) && Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a519ed39_38717ada PS1, Line 259: switch (var_num) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4bc8d662_b8aceeb2 PS1, Line 262: if (res->size <= 16) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/09c09ed1_4882d6aa PS1, Line 262: if (res->size <= 16) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/64b4b428_9f259c0c PS1, Line 268: if (res->size <= 16) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/936a62f7_d01940cf PS1, Line 273: if (res->size <= 16) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f05228df_f88c88ee PS1, Line 289: /* Set WideIO for as many IOs found (fall through is on purpose) */ Prefer 'fallthrough;' over fallthrough comment File src/southbridge/amd/agesa/hudson/sata.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/760f2a7f_26ebe2a4 PS1, Line 24: (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); "(foo*)" should be "(foo *)" File src/southbridge/amd/agesa/hudson/sd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9c005c2c_77e5465f PS1, Line 26: else { /* SD 2.0 mode */ else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b0336f47_44cc846f PS1, Line 32: else { /* Stepping >= A1 */ else should follow close brace '}' File src/southbridge/amd/agesa/hudson/smbus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1a6616a4_f1bc456a PS1, Line 38: if (val & 0x1c) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/24de9d34_eb2c4dee PS1, Line 54: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/908eafc7_144bd557 PS1, Line 67: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6098a0a4_92027c52 PS1, Line 81: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b3aaa40e_f9000b98 PS1, Line 97: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bfd7cf55_6d9ef541 PS1, Line 108: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/15774617_88a6d391 PS1, Line 124: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f3c2f306_783fb6dd PS1, Line 138: if (smbus_wait_until_ready(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4ff95a33_47d3c6a8 PS1, Line 157: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks File src/southbridge/amd/agesa/hudson/smbus_spd.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/44fbb720_892dee87 PS1, Line 34: for (;;) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5e790d18_e7ca9063 PS1, Line 37: if (__rdtsc() > limit) break; trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/34bcae4e_17f4c9fe PS1, Line 38: if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/251929ad_376b6e1a PS1, Line 39: if ((status & 1) == 1) continue; // HostBusy set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/379716cb_32c7e966 PS1, Line 43: buffer [0] = __inbyte(iobase + 5); space prohibited before open square bracket '[' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6f69caa1_6f3b0a6e PS1, Line 44: if (status == 2) status = 0; // check for done with no errors trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/068574bf_b4122c15 PS1, Line 64: for (;;) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0a214d3a_e358a476 PS1, Line 67: if (__rdtsc() > limit) break; trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e3d36045_e0a93fbd PS1, Line 68: if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d6921f3f_713a894f PS1, Line 69: if ((status & 1) == 1) continue; // HostBusy set, keep waiting trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9ac7ae9b_e9c626a6 PS1, Line 73: buffer [0] = __inbyte(iobase + 5); space prohibited before open square bracket '[' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/575cbcd4_ee7b7aec PS1, Line 74: if (status == 2) status = 0; // check for done with no errors trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bbaa5634_809775c7 PS1, Line 104: for (index = 1; index < count; index++) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0003c82e_a8685f48 PS1, Line 106: error = readSmbusByte(iobase, SmbusSlaveAddress, &buffer [index]); space prohibited before open square bracket '[' File src/southbridge/amd/agesa/hudson/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dffdaca3_bebd4adf PS1, Line 63: while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4143c437_1ea681fd PS1, Line 112: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/72403672_078c1364 PS1, Line 121: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3caaff4c_d8564a02 PS1, Line 125: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks File src/southbridge/amd/cimx/sb800/Amd.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b7bf41d1_ae78ba93 PS1, Line 53: PreMemHeap = 0, ///< Create heap in cache. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/96bf8c78_a6c8036e PS1, Line 54: PostMemDram, ///< Create heap in memory. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d08e5546_a38f31c6 PS1, Line 55: ByHost ///< Create heap by Host. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/244a9e63_1d8ba7a8 PS1, Line 60: AccessWidth8 = 1, ///< Access width is 8 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d42784e5_3a5a3a4d PS1, Line 61: AccessWidth16, ///< Access width is 16 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cca6c855_d79834c4 PS1, Line 62: AccessWidth32, ///< Access width is 32 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f511e052_49a18db2 PS1, Line 63: AccessWidth64, ///< Access width is 64 bits. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e1ad70e0_3347d128 PS1, Line 65: AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cdd03fbf_717feb0c PS1, Line 66: AccessS3SaveWidth16, ///< Save 16 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/91699365_1df0c0cd PS1, Line 67: AccessS3SaveWidth32, ///< Save 32 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d96f9864_5d1bdfe7 PS1, Line 68: AccessS3SaveWidth64, ///< Save 64 bits data. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b9820eb2_9f59dc84 PS1, Line 75: IN unsigned int ImageBasePtr; ///< The AGESA Image base address. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/47eda50b_099b912d PS1, Line 76: IN unsigned int Func; ///< The service desired, @sa dispatch.h. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3fe4d5aa_80de40c6 PS1, Line 77: IN unsigned int AltImageBasePtr; ///< Alternate Image location please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/8fe2e050_eeffb6c9 PS1, Line 78: IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eb6ef11f_ec3d6a89 PS1, Line 79: union { ///< Callback pointer please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2294c0d2_be895dd6 PS1, Line 80: IN unsigned long long PlaceHolder; ///< Place holder please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4a0f8ca0_30e1cae4 PS1, Line 81: IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/05c3b8e0_b7f89f45 PS1, Line 82: } CALLBACK; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e20af17b_5c63f6e2 PS1, Line 83: IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/3cdb1e4c_6cbf71e9 PS1, Line 88: IN unsigned int Signature; ///< Binary Signature please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b2889631_17e2ef44 PS1, Line 89: IN signed char CreatorID[8]; ///< 8 characters ID please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e5816041_b0d6d710 PS1, Line 90: IN signed char Version[12]; ///< 12 characters version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b5d72b50_48552c61 PS1, Line 91: IN unsigned int ModuleInfoOffset; ///< Offset of module please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/72cc8d6a_957445c1 PS1, Line 92: IN unsigned int EntryPointAddress; ///< Entry address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e92397dd_274ca2aa PS1, Line 93: IN unsigned int ImageBase; ///< Image base please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/51f1155c_ac15a088 PS1, Line 94: IN unsigned int RelocTableOffset; ///< Relocate Table offset please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ec65061c_667ed5f0 PS1, Line 95: IN unsigned int ImageSize; ///< Size please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a994eb5c_5f66d125 PS1, Line 96: IN unsigned short Checksum; ///< Checksum please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/424dc612_892ed969 PS1, Line 97: IN unsigned char ImageType; ///< Type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6d857f7c_b0982ce9 PS1, Line 98: IN unsigned char V_Reserved; ///< Reserved please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/37675d7c_15a88f12 PS1, Line 103: IN unsigned int ModuleHeaderSignature; ///< Module signature please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f9450b1e_3508c7d1 PS1, Line 104: IN signed char ModuleIdentifier[8]; ///< 8 characters ID please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6882388f_c3efb489 PS1, Line 105: IN signed char ModuleVersion[12]; ///< 12 characters version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/38687bcb_99c5a8ad PS1, Line 106: IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ae4e4167_1e2fac26 PS1, Line 107: IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f803be51_eddbc26a PS1, Line 130: IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ef5120e3_9563a2d2 PS1, Line 131: IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eb702d64_ccd4fa2a PS1, Line 132: IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/940bd33e_222440e5 PS1, Line 133: IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/77f65f79_65cebe07 PS1, Line 142: HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1f449543_c69e3fc4 PS1, Line 143: HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a07d924e_7167ab38 PS1, Line 144: HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/33649dc0_29ee02e1 PS1, Line 145: HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/36d90692_d8f72d44 PS1, Line 146: HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/04ddc37e_d12446ed PS1, Line 147: HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/2295200e_3131fe00 PS1, Line 148: HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1456db79_5ae129bb PS1, Line 149: HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/bf7c520c_54c6f808 PS1, Line 150: HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f00a3990_47d6cf12 PS1, Line 151: HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/ed275163_55859087 PS1, Line 152: HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/972b0875_4d045c73 PS1, Line 153: HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5f705113_2f440610 PS1, Line 154: HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dd58f29f_7a96f00b PS1, Line 155: HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1c4e7bde_1ee27ce8 PS1, Line 156: HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/324662b0_42718153 PS1, Line 157: HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks please, no spaces at the start of a line File src/southbridge/amd/cimx/sb800/AmdSbLib.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d7f3f068_8fe672ee PS1, Line 18: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e458c76d_b7983a65 PS1, Line 19: unsigned int AMDLogo; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/eff317db_ca5beff5 PS1, Line 20: unsigned long long CreatorID; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e329503c_8aea6d42 PS1, Line 21: unsigned int Version1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5fc8dd55_59414bf6 PS1, Line 22: unsigned int Version2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/79d651f2_cc96c230 PS1, Line 23: unsigned int Version3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d6eeadf1_02a641b8 PS1, Line 24: unsigned int ModuleInfoOffset; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/90cb86f7_b4ee5fa7 PS1, Line 25: unsigned int EntryPoint; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6669edd3_0eab44bc PS1, Line 26: unsigned int ImageBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/c0f1bc41_267b129a PS1, Line 27: unsigned int RelocTableOffset; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/67920d6c_761b1c46 PS1, Line 28: unsigned int ImageSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/b8a5e969_4dbd368f PS1, Line 29: unsigned short CheckSum; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/6759c5ba_ebccc585 PS1, Line 30: unsigned char ImageType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/4c4f1038_6d52cb10 PS1, Line 31: unsigned char Reserved2; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5ef5d22d_c356e0b7 PS1, Line 134: { open brace '{' following enum go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/428cd24d_736bf52b PS1, Line 135: AccWidthUint8 = 0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0c81a928_f6ea122d PS1, Line 136: AccWidthUint16, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f62dff12_661afae6 PS1, Line 137: AccWidthUint32, please, no spaces at the start of a line File src/southbridge/amd/cimx/sb800/chip.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/d16779cb_483fdc66 PS1, Line 19: { open brace '{' following struct go on the same line File src/southbridge/amd/cimx/sb800/fan.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/c0659cd9_75248ccf PS1, Line 261: if (sb_chip->imc_tempin3_enabled) { suspicious code indentation after conditional statements File src/southbridge/amd/cimx/sb800/late.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e6cebdf7_41eac2a8 PS1, Line 96: if (!(val & HOST_CTL_AHCI_EN)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/f9a1f232_b4c3c8bb PS1, Line 344: if (sb_config->AzaliaController == AZALIA_DISABLE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/63c86325_db3c1a20 PS1, Line 374: if (dev->enabled) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/1dd2f06e_4190cec6 PS1, Line 385: if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break; trailing statements should be on next line File src/southbridge/amd/cimx/sb800/lpc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/0bb112f8_cbf70d3c PS1, Line 135: if (var_num >= 3) Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/5aca9eed_fff930a0 PS1, Line 137: switch (var_num) { Too many leading tabs - consider code refactoring Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/972e2b5f_6e1ec1b3 PS1, Line 157: /* Set WideIO for as many IOs found (fall through is on purpose) */ Prefer 'fallthrough;' over fallthrough comment File src/southbridge/amd/cimx/sb800/smbus.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a11e371a_16a93846 PS1, Line 36: if (val & 0x1c) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/22b201ce_cd89ec01 PS1, Line 67: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e7796d4d_4e269be5 PS1, Line 82: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspicious code indentation after conditional statements Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/60dbc8fd_cad055fe PS1, Line 100: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/a2557c71_4bcaa867 PS1, Line 130: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/84687465_cee371a7 PS1, Line 166: if (smbus_wait_until_done(smbus_io_base) < 0) { braces {} are not necessary for single statement blocks File src/southbridge/amd/cimx/sb800/smbus_spd.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/dc77f30b_4d23e506 PS1, Line 32: #define SMBUS_FREQUENCY_CONST 66000000 / 4 Macros with complex values should be enclosed in parentheses File src/southbridge/amd/cimx/sb800/spi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/cc6d4a97_783fb3ce PS1, Line 31: while ((read8((void *)(spibar + 2)) & 1) && trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/9c2f0c3d_57d2406c PS1, Line 74: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e1e52625_2cc82841 PS1, Line 83: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167472): https://review.coreboot.org/c/coreboot/+/71598/comment/e6062a26_5789bf66 PS1, Line 88: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/71598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72d8ac5ceddf46f2b3f0c95c0f122c661ec7e888 Gerrit-Change-Number: 71598 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 01 Jan 2023 11:15:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: WIP: mb/hp/t620: Add new board HP T620
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71609 ) Change subject: WIP: mb/hp/t620: Add new board HP T620 ...................................................................... WIP: mb/hp/t620: Add new board HP T620 This is the diff applied to the previous commit to change the biostar/a68n_5200 port into support for new board: HP T620 thin client. This work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. It has a socketed SOIC8 chip and SIO accessible serial, making it a good target for testing/maintaining this platform. coreboot console works over serial COMA by default. Board is fanless, so no need for fan control. TESTED: Boots SeaBIOS 1.14.0 and to debian 11, NIC works, serial works. Have had 120 days of uptime with this particular port and no issues. Missing: - Audio verb table (deleted) - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board) Caveat: Without VGA BIOS rom there are no displays. VGA ROM was extracted from /dev/mem @ 0xC0000 on a running system and one DP was tested to work. NB: Since bringing back AGESA code with resource allocator v4 and parallel mp init, this board no longer boots due to some kind of CBFS alignment issue, I need some help to figure this out. cbfs: This image contains the following sections that can be manipulated with this tool: 'RW_MRC_CACHE' (size 65536, offset 0) 'COREBOOT' (CBFS, size 8322560, offset 66048) It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none config 0x80 raw 2327 LZMA (6878 decompressed) revision 0xa00 raw 717 none build_info 0xd00 raw 89 none fallback/dsdt.aml 0xd80 raw 5950 none cmos_layout.bin 0x2500 cmos_layout 616 none fallback/postcar 0x27c0 stage 21688 none payload_config 0x7cc0 raw 1621 none payload_revision 0x8340 raw 235 none (empty) 0x8480 null 31012 none apu/amdfw 0xfdc0 raw 69632 none fallback/romstage 0x20e00 stage 386080 none fallback/ramstage 0x7f2c0 stage 125180 LZMA (283964 decompressed) pci1002,9837.rom 0x9dc40 optionrom 65536 none fallback/payload 0xadc80 simple elf 72756 none (empty) 0xbf900 null 7524836 none bootblock 0x7ecb00 bootblock 12992 none ... Built hp/t620 (T620) tail of coreboot log: ... [INFO ] CBFS: Found 'pci1002,9837.rom' @0x9dc40 size 0x10000 in mcache @0x5ffdd2a4 [NOTE ] Mapping PCI device 10029837 to 10029830 [DEBUG] In CBFS, ROM address for PCI: 00:01.0 = 0xff8ade6c [DEBUG] Copying VBIOS image from 0xff8ade6c [DEBUG] ACPI: * VFCT at 5fe9d420 [DEBUG] ACPI: added table 8/32, length now 68 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 9/32, length now 72 [INFO ] ACPI: done. [DEBUG] ACPI tables: 89808 bytes. [DEBUG] smbios_write_tables: 5fe8e000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-1385-g5be491174b' [DEBUG] SMBIOS tables: 529 bytes. [DEBUG] Writing table forward entry at 0x00000500 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 80 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 428 Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/t620/BiosCallOuts.c M src/mainboard/hp/t620/Kconfig M src/mainboard/hp/t620/Kconfig.name M src/mainboard/hp/t620/board_info.txt M src/mainboard/hp/t620/bootblock.c M src/mainboard/hp/t620/devicetree.cb 6 files changed, 128 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/71609/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c index f1560c4..a0ac3f0 100644 --- a/src/mainboard/hp/t620/BiosCallOuts.c +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -5,8 +5,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include "imc.h" - const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, @@ -24,20 +22,6 @@ * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} }; @@ -47,113 +31,6 @@ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; @@ -164,7 +41,4 @@ { /* Azalia Controller OEM Codec Table Pointer */ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); } diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig index 256121c..f897bab 100644 --- a/src/mainboard/hp/t620/Kconfig +++ b/src/mainboard/hp/t620/Kconfig @@ -1,24 +1,22 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_BIOSTAR_A68N5200_CLONE +if BOARD_HP_T620 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_ITE_IT8728F + select SUPERIO_ASPEED_AST2400 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_8192 select GFXUMA config MAINBOARD_DIR default "hp/t620" config MAINBOARD_PART_NUMBER - default "A68N5200" + default "T620" config HW_MEM_HOLE_SIZEK hex @@ -40,4 +38,4 @@ bool default n -endif +endif # BOARD_HP_T620 diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name index e893341..fd55b76 100644 --- a/src/mainboard/hp/t620/Kconfig.name +++ b/src/mainboard/hp/t620/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200_CLONE - bool "A68N-5200-CLONE" +config BOARD_HP_T620 + bool "T620" diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt index b351b8e..4132ada 100644 --- a/src/mainboard/hp/t620/board_info.txt +++ b/src/mainboard/hp/t620/board_info.txt @@ -1 +1,2 @@ Category: eval +Socketed Flash: Y diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c index 70bc10c..5226f4a 100644 --- a/src/mainboard/hp/t620/bootblock.c +++ b/src/mainboard/hp/t620/bootblock.c @@ -4,27 +4,10 @@ #include <bootblock_common.h> #include <stdint.h> #include <device/pci_ops.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - u32 reg32; - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - reg32 = misc_read32(0x28); - reg32 &= 0xfff8ffff; - misc_write32(0x28, reg32); - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = misc_read32(0x40); - reg32 &= 0xffffbffb; - misc_write32(0x40, reg32); -} +#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART2) void bootblock_mainboard_early_init(void) { @@ -35,7 +18,7 @@ /* Set LPC decode enables. */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pci_write_config32(dev, 0x44, 0xff03ffc0); /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); @@ -47,11 +30,6 @@ byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Enable serial output on it8728f */ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* Enable serial output */ + aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb index c036b65..ed6fa58 100644 --- a/src/mainboard/hp/t620/devicetree.cb +++ b/src/mainboard/hp/t620/devicetree.cb @@ -8,15 +8,15 @@ end device domain 0 on - subsystemid 0x1022 0x1410 inherit + subsystemid 0x103c 0x2187 inherit chip northbridge/amd/agesa/family16kb device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal HDMI Audio device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC + device pci 2.1 off end + device pci 2.2 on end + device pci 2.3 on end device pci 2.4 off end # Edge Connector device pci 2.5 off end # Edge Connector end #chip northbridge/amd/agesa/family16kb @@ -28,42 +28,23 @@ device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pci 14.0 on end # SMBus + device pci 14.2 on end # Audio Azalia + device pci 14.3 on # LPC + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "0" + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 on # SUART2 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0x71 = 3 + irq 0xf0 = 2 + end + end end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F + end end #LPC device pci 14.7 off end # SD end #chip southbridge/amd/agesa/hudson @@ -75,12 +56,10 @@ device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + register "spdAddrLookup" = "{ + { {0xA0, 0xA2}, {0x00, 0x00}, }, + { {0x00, 0x00}, {0x00, 0x00}, }, }" end - - end #domain + end end #northbridge/amd/agesa/family16kb/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/71609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Gerrit-Change-Number: 71609 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: mb/hp/t620: Add clone of biostar/a68n-5200
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71608 ) Change subject: mb/hp/t620: Add clone of biostar/a68n-5200 ...................................................................... mb/hp/t620: Add clone of biostar/a68n-5200 HP T620 was ported to coreboot based on the biostar/a68n-5200 port. This commit is a direct clone of the previous board, with the name changed to make it pass jenkins, and extra SPDX headers on empty files. Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/hp/t620/BiosCallOuts.c A src/mainboard/hp/t620/Kconfig A src/mainboard/hp/t620/Kconfig.name A src/mainboard/hp/t620/Makefile.inc A src/mainboard/hp/t620/OemCustomize.c A src/mainboard/hp/t620/OptionsIds.h A src/mainboard/hp/t620/acpi/AmdImc.asl A src/mainboard/hp/t620/acpi/gpe.asl A src/mainboard/hp/t620/acpi/mainboard.asl A src/mainboard/hp/t620/acpi/routing.asl A src/mainboard/hp/t620/acpi/sata.asl A src/mainboard/hp/t620/acpi/sleep.asl A src/mainboard/hp/t620/acpi/superio.asl A src/mainboard/hp/t620/acpi/thermal.asl A src/mainboard/hp/t620/acpi/usb_oc.asl A src/mainboard/hp/t620/board_info.txt A src/mainboard/hp/t620/bootblock.c A src/mainboard/hp/t620/buildOpts.c A src/mainboard/hp/t620/cmos.layout A src/mainboard/hp/t620/devicetree.cb A src/mainboard/hp/t620/dsdt.asl A src/mainboard/hp/t620/irq_tables.c A src/mainboard/hp/t620/mainboard.c 23 files changed, 1,259 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/71608/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c new file mode 100644 index 0000000..f1560c4 --- /dev/null +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <FchPlatform.h> + +#include "imc.h" + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * AMD Olivehill Platform ALC272 Verb Table + */ +static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x411111F0}, // Port A - LOUT2 + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a19840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01813030}, // Port C - LINE1 + {0x1b, 0x411111F0}, // Port E - LINE2 + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x01441120}, // - SPDIF_OUT1 + {0x21, 0x01214010}, // Port I - HPOUT + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST OlivehillCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control, the recommended way */ + if (CONFIG(HUDSON_IMC_FWM)) { + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. + */ + } else { + /* HWM fan control, the way not recommended */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + } +} + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; + FchParams_reset->QeEnabled = FALSE; +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); + + /* Fan Control */ + oem_fan_control(FchParams_env); +} diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig new file mode 100644 index 0000000..256121c --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_BIOSTAR_A68N5200_CLONE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select SUPERIO_ITE_IT8728F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + default "hp/t620" + +config MAINBOARD_PART_NUMBER + default "A68N5200" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default n + +endif diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name new file mode 100644 index 0000000..e893341 --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BIOSTAR_A68N5200_CLONE + bool "A68N-5200-CLONE" diff --git a/src/mainboard/hp/t620/Makefile.inc b/src/mainboard/hp/t620/Makefile.inc new file mode 100644 index 0000000..549801d --- /dev/null +++ b/src/mainboard/hp/t620/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/hp/t620/OemCustomize.c b/src/mainboard/hp/t620/OemCustomize.c new file mode 100644 index 0000000..18db540 --- /dev/null +++ b/src/mainboard/hp/t620/OemCustomize.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <PlatformMemoryConfiguration.h> + +#include <northbridge/amd/agesa/state_machine.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERRIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS(LAYERS_4), + + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/t620/OptionsIds.h b/src/mainboard/hp/t620/OptionsIds.h new file mode 100644 index 0000000..130d852 --- /dev/null +++ b/src/mainboard/hp/t620/OptionsIds.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +#endif diff --git a/src/mainboard/hp/t620/acpi/AmdImc.asl b/src/mainboard/hp/t620/acpi/AmdImc.asl new file mode 100644 index 0000000..4483834 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/AmdImc.asl @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Local0 = 0 + While (Local0 != 0xfa) { + Local0 = MRG0 + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 1 + MRG2 = 0 + MSTI = 0x98 + WACK() + + MRG0 = 0 + MRG1 = 0xb4 + MRG2 = 0 + MSTI = 0x96 + WACK() +} + +//Wake +Method (IMWK, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} diff --git a/src/mainboard/hp/t620/acpi/gpe.asl b/src/mainboard/hp/t620/acpi/gpe.asl new file mode 100644 index 0000000..778c7f7 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/gpe.asl @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/hp/t620/acpi/mainboard.asl b/src/mainboard/hp/t620/acpi/mainboard.asl new file mode 100644 index 0000000..9b18e72 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/hp/t620/acpi/routing.asl b/src/mainboard/hp/t620/acpi/routing.asl new file mode 100644 index 0000000..9bce4b2 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/routing.asl @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/hp/t620/acpi/sata.asl b/src/mainboard/hp/t620/acpi/sata.asl new file mode 100644 index 0000000..659a076 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sata.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* No SATA functionality */ diff --git a/src/mainboard/hp/t620/acpi/sleep.asl b/src/mainboard/hp/t620/acpi/sleep.asl new file mode 100644 index 0000000..fc26c30 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sleep.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + USBS = 1 + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/hp/t620/acpi/superio.asl b/src/mainboard/hp/t620/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/hp/t620/acpi/thermal.asl b/src/mainboard/hp/t620/acpi/thermal.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/thermal.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/hp/t620/acpi/usb_oc.asl b/src/mainboard/hp/t620/acpi/usb_oc.asl new file mode 100644 index 0000000..a5846fe --- /dev/null +++ b/src/mainboard/hp/t620/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/hp/t620/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c new file mode 100644 index 0000000..70bc10c --- /dev/null +++ b/src/mainboard/hp/t620/bootblock.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +static void sbxxx_enable_48mhzout(void) +{ + u32 reg32; + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + reg32 = misc_read32(0x28); + reg32 &= 0xfff8ffff; + misc_write32(0x28, reg32); + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + reg32 = misc_read32(0x40); + reg32 &= 0xffffbffb; + misc_write32(0x40, reg32); +} + +void bootblock_mainboard_early_init(void) +{ + u8 byte; + + /* Enable the AcpiMmio space */ + pm_io_write8(0x24, 1); + + /* Set LPC decode enables. */ + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + + /* enable SIO LPC decode */ + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Enable serial output on it8728f */ + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/t620/buildOpts.c b/src/mainboard/hp/t620/buildOpts.c new file mode 100644 index 0000000..f5c2181 --- /dev/null +++ b/src/mainboard/hp/t620/buildOpts.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE + +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +#include <PlatformInstall.h> diff --git a/src/mainboard/hp/t620/cmos.layout b/src/mainboard/hp/t620/cmos.layout new file mode 100644 index 0000000..a11e1dd --- /dev/null +++ b/src/mainboard/hp/t620/cmos.layout @@ -0,0 +1,35 @@ +#***************************************************************************** +# SPDX-License-Identifier: GPL-2.0-only + +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb new file mode 100644 index 0000000..c036b65 --- /dev/null +++ b/src/mainboard/hp/t620/devicetree.cb @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 off end # mPCIe slot + device pci 2.3 off end # Realtek NIC + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + #register "multi_function_register_1" = "0x01" + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 + end + device pnp 2e.4 on # Hardware Monitor + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + irq 0xf1 = 0x00 + irq 0xf2 = 0x04 + irq 0xf3 = 0xa0 + irq 0xf5 = 0x0f + irq 0xf9 = 0xa0 + irq 0xfa = 0x04 + end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + end + device pnp 2e.6 off end # KBC? + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end + device pnp 2e.9 off end + device pnp 2e.a off end # IR + end # ITE IT8728F + end #LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/agesa/hudson + + chip northbridge/amd/agesa/family16kb + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end + + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/t620/dsdt.asl b/src/mainboard/hp/t620/dsdt.asl new file mode 100644 index 0000000..c86cf27 --- /dev/null +++ b/src/mainboard/hp/t620/dsdt.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_SB) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/hp/t620/irq_tables.c b/src/mainboard/hp/t620/irq_tables.c new file mode 100644 index 0000000..6d75c05 --- /dev/null +++ b/src/mainboard/hp/t620/irq_tables.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <string.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/hp/t620/mainboard.c b/src/mainboard/hp/t620/mainboard.c new file mode 100644 index 0000000..3ebc0c1 --- /dev/null +++ b/src/mainboard/hp/t620/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(struct device *dev) +{ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/71608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 71608 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71607 ) Change subject: amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb ...................................................................... amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb Change-Id: I6b159433c111525aed1451acfd2540eab8fdc8f7 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/cpu/amd/agesa/Makefile.inc M src/soc/amd/common/block/cpu/smm/smm_relocate.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/71607/1 diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 5d8f6df..fd727e6 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_relocate.c diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index 4d33b65..4f23826 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -92,3 +92,8 @@ .per_cpu_smm_trigger = smm_relocation_handler, .post_mp_init = global_smi_enable, }; + +const struct mp_ops amd_mp_ops_no_smm = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/71607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b159433c111525aed1451acfd2540eab8fdc8f7 Gerrit-Change-Number: 71607 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: agesa/common: Add missing VOID
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71606 ) Change subject: agesa/common: Add missing VOID ...................................................................... agesa/common: Add missing VOID Change-Id: Ifd2339ef69e14ffa48c2b652a76b4dce5b35277b Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/agesa/common/amdlib.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/71606/1 diff --git a/src/vendorcode/amd/agesa/common/amdlib.c b/src/vendorcode/amd/agesa/common/amdlib.c index dbfdce8..fb1cf94 100644 --- a/src/vendorcode/amd/agesa/common/amdlib.c +++ b/src/vendorcode/amd/agesa/common/amdlib.c @@ -457,7 +457,9 @@ } VOID -LibAmdFinit() +LibAmdFinit( + VOID + ) { /* TODO: finit */ __asm__ volatile ("finit"); -- To view, visit https://review.coreboot.org/c/coreboot/+/71606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd2339ef69e14ffa48c2b652a76b4dce5b35277b Gerrit-Change-Number: 71606 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: cpu/amd/smm: Remove dead code
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71605 ) Change subject: cpu/amd/smm: Remove dead code ...................................................................... cpu/amd/smm: Remove dead code Change-Id: I9c2d3f23be45c8ae76609e0e650864e4ad7a5ad3 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- D src/cpu/amd/smm/Makefile.inc D src/cpu/amd/smm/smm_init.c 2 files changed, 10 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/71605/1 diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc deleted file mode 100644 index 97a6694..0000000 --- a/src/cpu/amd/smm/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ - -ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c deleted file mode 100644 index 75dd4506..0000000 --- a/src/cpu/amd/smm/smm_init.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <string.h> - -void smm_init(void) -{ - msr_t msr, syscfg_orig, mtrr_aseg_orig; - - /* Back up MSRs for later restore */ - syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); - - /* MTRR changes don't like an enabled cache */ - disable_cache(); - - msr = syscfg_orig; - - /* Allow changes to MTRR extended attributes */ - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - /* turn the extended attributes off until we fix - * them so A0000 is routed to memory - */ - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* set DRAM access to 0xa0000 */ - msr.lo = 0x18181818; - msr.hi = 0x18181818; - wrmsr(MTRR_FIX_16K_A0000, msr); - - /* enable the extended features */ - msr = syscfg_orig; - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start); - wbinvd(); - disable_cache(); - - /* Restore SYSCFG and MTRR */ - wrmsr(SYSCFG_MSR, syscfg_orig); - wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); - enable_cache(); - - /* CPU MSR are set in CPU init */ -} - -void smm_init_completion(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/71605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2d3f23be45c8ae76609e0e650864e4ad7a5ad3 Gerrit-Change-Number: 71605 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71604 ) Change subject: nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4 ...................................................................... nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4 Change-Id: Id02f119b786c19cd3fc185cae7f1abcd2daa2b67 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/northbridge/amd/agesa/family16kb/Kconfig 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/71604/1 diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index faea30d..8953377 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool - select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB -- To view, visit https://review.coreboot.org/c/coreboot/+/71604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id02f119b786c19cd3fc185cae7f1abcd2daa2b67 Gerrit-Change-Number: 71604 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: Revert "{cpu/nb}/amd/family16: Remove platform"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71603 ) Change subject: Revert "{cpu/nb}/amd/family16: Remove platform" ...................................................................... Revert "{cpu/nb}/amd/family16: Remove platform" This reverts commit 49af4f7f9197e559b2c7142129441679bb1d24a2. Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/Makefile.inc A src/cpu/amd/agesa/family16kb/Kconfig A src/cpu/amd/agesa/family16kb/Makefile.inc A src/cpu/amd/agesa/family16kb/acpi/cpu.asl A src/cpu/amd/agesa/family16kb/chip_name.c A src/cpu/amd/agesa/family16kb/fixme.c A src/cpu/amd/agesa/family16kb/model_16_init.c A src/northbridge/amd/agesa/Makefile.inc A src/northbridge/amd/agesa/family16kb/Kconfig A src/northbridge/amd/agesa/family16kb/Makefile.inc A src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl A src/northbridge/amd/agesa/family16kb/acpi_tables.c A src/northbridge/amd/agesa/family16kb/chip.h A src/northbridge/amd/agesa/family16kb/dimmSpd.c A src/northbridge/amd/agesa/family16kb/northbridge.c A src/northbridge/amd/agesa/family16kb/pci_devs.h A src/northbridge/amd/agesa/family16kb/state_machine.c M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c 20 files changed, 1,342 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/71603/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d46d2ed..f6c4f16 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -2,6 +2,7 @@ config CPU_AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY16_KB default n select ARCH_X86 select DRIVERS_AMD_PI @@ -43,3 +44,5 @@ from non-volatile memory. endif # CPU_AMD_AGESA + +source "src/cpu/amd/agesa/family16kb/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4cacc51..5d8f6df 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb + romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..60bf64f --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CPU_AMD_AGESA_FAMILY16_KB + bool + select SMM_ASEG + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_AGESA_FAMILY16_KB + +config FORCE_AM1_SOCKET_SUPPORT + bool + default n + help + Force AGESA to ignore package type mismatch between CPU and northbridge + in memory code. This enables Socket AM1 support with current AGESA + version for Kabini platform. + Enable this option only if you have Socket AM1 board. + Note that the AGESA release shipped with coreboot does not officially + support the AM1 socket. Selecting this option might damage your hardware. + +endif diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..9464372 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fixme.c + +ramstage-y += fixme.c +ramstage-y += chip_name.c +ramstage-y += model_16_init.c + +subdirs-y += ../../mtrr diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl new file mode 100644 index 0000000..d589ae8 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Processor Object + * + */ +Scope (\_SB) {/* define processor scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c new file mode 100644 index 0000000..0ca021c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations cpu_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD CPU Family 16h Model 00h-0Fh") +}; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c new file mode 100644 index 0000000..da2744c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/hpet.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> +#include <amdlib.h> + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c new file mode 100644 index 0000000..0f11136 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/cpu.h> +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +static void model_16_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Model 16 Init.\n"); + + msr_t msr; + int msrno; +#if CONFIG(LOGICAL_CPUS) + u32 siblings; +#endif + + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ + disable_cache(); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr(MTRR_FIX_16K_A0000, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); + for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) + wrmsr(msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + if (acpi_is_wakeup_s3()) + restore_mtrr(); + + x86_mtrr_check(); + enable_cache(); + + /* zero the machine check error status registers */ + mca_clear_status(); + +#if CONFIG(LOGICAL_CPUS) + siblings = get_cpu_count() - 1; // minus BSP + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + /* Write protect SMM space with SMMLOCK. */ + lock_smm(); +} + +static struct device_operations cpu_dev_ops = { + .init = model_16_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc new file mode 100644 index 0000000..f586623 --- /dev/null +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb + +endif diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..8cf919a --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + bool + select LEGACY_SMP_INIT + select RESOURCE_ALLOCATOR_V3 + +if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xF8000000 + +config ECAM_MMCONF_BUS_NUMBER + default 64 + +config VGA_BIOS_ID + string + default "1002,9830" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +endif # NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..e387ee5 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += dimmSpd.c + +ramstage-y += northbridge.c +ramstage-y += acpi_tables.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl new file mode 100644 index 0000000..a635247 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PICM) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include <soc/amd/common/acpi/thermal_zone.asl> +} diff --git a/src/northbridge/amd/agesa/family16kb/acpi_tables.c b/src/northbridge/amd/agesa/family16kb/acpi_tables.c new file mode 100644 index 0000000..cf88cfa --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi_tables.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h new file mode 100644 index 0000000..239bc69 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family16kb_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c new file mode 100644 index 0000000..1f9d970 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include <Porting.h> +#include <AGESA.h> +#include "chip.h" + +#include <northbridge/amd/agesa/dimmSpd.h> + +/** + * Gets the SMBus address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) +{ + UINT8 spdAddress; + + DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); + if (dev == NULL) + return AGESA_ERROR; + + DEVTREE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info; + if (config == NULL) + return AGESA_ERROR; + + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + int err = hudson_readSpd(spdAddress, (void *)info->Buffer, DDR3_SPD_SIZE); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c new file mode 100644 index 0000000..250c491 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -0,0 +1,741 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <Porting.h> +#include <AGESA.h> +#include <Options.h> +#include <Topology.h> +#include <northbridge/amd/nb_common.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define MAX_NODE_NUMS MAX_NODES + +static unsigned int node_nums; +static unsigned int sblink; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; +static unsigned int fx_devs = 0; + +static struct device *get_node_pci(u32 nodeid, u32 fn) +{ + return pcidev_on_root(DEV_CDB + nodeid, fn); +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i + 1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned int reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned int reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + struct device *dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + +static u32 amdfam16_nodeid(struct device *dev) +{ + return (dev->path.pci.devfn >> 3) - DEV_CDB; +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid << 4) | (linkn << 12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +static void read_resources(struct device *dev) +{ + /* + * This MMCONF resource must be reserved in the PCI_DOMAIN. + * It is not honored by the coreboot resource allocator if it is in + * the APIC_CLUSTER. + */ + mmconf_resource(dev, MMIO_CONF_BASE); + + /* There should be no BAR. */ +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(struct device *dev, unsigned int nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG(MULTIPLE_VGA_ADAPTERS) + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary, link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(struct device *dev) +{ + unsigned int nodeid; + + /* Find the nodeid */ + nodeid = amdfam16_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(const struct device *device) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + +static unsigned long agesa_write_acpi_tables(const struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN_UP(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; + + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *)current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *)current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *)current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *)current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); + if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *)current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp, ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, +}; + +static const struct pci_driver family16_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_16H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_10H_NB_HT, +}; + +static void fam16_finalize(void *chip_info) +{ + struct device *dev; + u32 value; + dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = pcidev_on_root(1, 1); + if (dev != NULL) { + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD FAM16 Northbridge") + .enable_dev = 0, + .final = fam16_finalize, +}; + +static void domain_read_resources(struct device *dev) +{ + unsigned int reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned int nodeid, reg_link; + struct device *reg_dev; + if (reg < 0xc0) { // mmio + nodeid = (limit & 0xf) + (base & 0x30); + } else { // io + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + + pci_domain_read_resources(dev); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned int hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk; + u32 hole; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 2) { // we find the hole + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i = 0; i < node_nums; i++) { + resource_t base_k, limit_k; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node + if (base_k > 4 * 1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +static void domain_set_resources(struct device *dev) +{ + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) - 1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64 * 1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) + mmio_basek = mem_hole.hole_startk; +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk, sizek; // 4 1T + + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + + sizek = limitk - basek; + + /* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */ + if (basek < 640 && sizek > 768) { + ram_resource_kb(dev, (idx | i), basek, 640 - basek); + idx += 0x10; + basek = 768; + sizek = limitk - basek; + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accommodate pci memory space */ + if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned int pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek > 0) { + ram_resource_kb(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4 * 1024 * 1024) { + sizek = 0; + } + else { + uint64_t topmem2 = amd_topmem2(); + basek = 4 * 1024 * 1024; + sizek = topmem2 / 1024 - basek; + } + } + + ram_resource_kb(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + } + + add_uma_resource_below_tolm(dev, 7); + + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static const char *domain_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, +}; + +static void sysconf_init(struct device *dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0] +} + +static void cpu_bus_scan(struct device *dev) +{ + struct bus *cpu_bus; + struct device *dev_mc; + int i, j; + int coreid_bits; + int core_max = 0; + unsigned int ApicIdCoreIdSize; + unsigned int core_nums; + int siblings = 0; + unsigned int family; + + dev_mc = pcidev_on_root(DEV_CDB, 0); + if (!dev_mc) { + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); + die(""); + } + sysconf_init(dev_mc); + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + struct device *cdb_dev; + unsigned int devn; + struct bus *pbus; + + devn = DEV_CDB + i; + pbus = dev_mc->bus; + + /* Find the cpu's pci device */ + cdb_dev = pcidev_on_root(devn, 0); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for (fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = pcidev_on_root(devn, 0); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + add_more_links(cdb_dev, 4); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = pcidev_on_root(devn, 3); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 7) {//f16 + cdb_dev = pcidev_on_root(devn, 5); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply APIC enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } +} + +static void cpu_bus_init(struct device *dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = { + CHIP_NAME("AMD FAM16 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x10029830: + case 0x10029831: + case 0x10029832: + case 0x10029833: + case 0x10029834: + case 0x10029835: + case 0x10029836: + case 0x10029837: + case 0x10029838: + case 0x10029839: + case 0x1002983A: + case 0x1002983D: + new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS + break; + default: + break; + } + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h new file mode 100644 index 0000000..f226cd3 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_FAM16KB_PCI_DEVS_H_ +#define _AMD_FAM16KB_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +/* Internal Audio Controller */ +#define ACTL_FUNC 1 +#define ACTL_DEVFN PCI_DEVFN(GFX_DEV, ACTL_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT1_FUNC 0x1 +#define NB_PCIE_PORT2_FUNC 0x2 +#define NB_PCIE_PORT3_FUNC 0x3 +#define NB_PCIE_PORT4_FUNC 0x4 +#define NB_PCIE_PORT5_FUNC 0x5 +#define NB_PCIE_DEV 2 +#define NB_PCIE_PORT_DEVID 0x1439 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT1_FUNC) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT2_FUNC) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT3_FUNC) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT4_FUNC) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT5_FUNC) + +#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..cbf0313 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/biosram.h> + +#include <Porting.h> +#include <AGESA.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + AGESA_STATUS status; + + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; + + if (CONFIG(ENABLE_MRC_CACHE)) { + status = OemInitResume(&Post->MemConfig.MemContext); + if (status == AGESA_SUCCESS) + Post->MemConfig.MemRestoreCtl = 1; + } +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(&Resume->S3DataBlock); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(&S3Late->S3DataBlock); +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(&S3Save->S3DataBlock); +} diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 4bc6a3d..4468cc3 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -159,6 +159,20 @@ default 181 range 1 255 +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + config CUSTOM_SPD_TWTR int "[26]: Min Internal Write to Read Command Delay, tWTR" default 105 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c index 08d7fcb..d3c8303 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c @@ -489,7 +489,10 @@ return TRUE; } } - return FALSE; + if (CONFIG(FORCE_AM1_SOCKET_SUPPORT)) + return TRUE; + else + return FALSE; } /* -----------------------------------------------------------------------------*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/71603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Gerrit-Change-Number: 71603 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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coreboot-gerrit January 2023