coreboot-gerrit January 2023

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[XL] Change in coreboot[master]: mb/hp/t620: Add clone of biostar/a68n-5200
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71608 ) Change subject: mb/hp/t620: Add clone of biostar/a68n-5200 ...................................................................... mb/hp/t620: Add clone of biostar/a68n-5200 HP T620 was ported to coreboot based on the biostar/a68n-5200 port. This commit is a direct clone of the previous board, with the name changed to make it pass jenkins, and extra SPDX headers on empty files. Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/hp/t620/BiosCallOuts.c A src/mainboard/hp/t620/Kconfig A src/mainboard/hp/t620/Kconfig.name A src/mainboard/hp/t620/Makefile.inc A src/mainboard/hp/t620/OemCustomize.c A src/mainboard/hp/t620/OptionsIds.h A src/mainboard/hp/t620/acpi/AmdImc.asl A src/mainboard/hp/t620/acpi/gpe.asl A src/mainboard/hp/t620/acpi/mainboard.asl A src/mainboard/hp/t620/acpi/routing.asl A src/mainboard/hp/t620/acpi/sata.asl A src/mainboard/hp/t620/acpi/sleep.asl A src/mainboard/hp/t620/acpi/superio.asl A src/mainboard/hp/t620/acpi/thermal.asl A src/mainboard/hp/t620/acpi/usb_oc.asl A src/mainboard/hp/t620/board_info.txt A src/mainboard/hp/t620/bootblock.c A src/mainboard/hp/t620/buildOpts.c A src/mainboard/hp/t620/cmos.layout A src/mainboard/hp/t620/devicetree.cb A src/mainboard/hp/t620/dsdt.asl A src/mainboard/hp/t620/irq_tables.c A src/mainboard/hp/t620/mainboard.c 23 files changed, 1,259 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/71608/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c new file mode 100644 index 0000000..f1560c4 --- /dev/null +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <FchPlatform.h> + +#include "imc.h" + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * AMD Olivehill Platform ALC272 Verb Table + */ +static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x411111F0}, // Port A - LOUT2 + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a19840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01813030}, // Port C - LINE1 + {0x1b, 0x411111F0}, // Port E - LINE2 + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x01441120}, // - SPDIF_OUT1 + {0x21, 0x01214010}, // Port I - HPOUT + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST OlivehillCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* Hardware Monitor Fan Control + * Hardware limitation: + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + /* Enable IMC fan control, the recommended way */ + if (CONFIG(HUDSON_IMC_FWM)) { + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. + */ + } else { + /* HWM fan control, the way not recommended */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + } +} + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; + FchParams_reset->QeEnabled = FALSE; +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); + + /* Fan Control */ + oem_fan_control(FchParams_env); +} diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig new file mode 100644 index 0000000..256121c --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_BIOSTAR_A68N5200_CLONE + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select SUPERIO_ITE_IT8728F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select GFXUMA + +config MAINBOARD_DIR + default "hp/t620" + +config MAINBOARD_PART_NUMBER + default "A68N5200" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default n + +endif diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name new file mode 100644 index 0000000..e893341 --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_BIOSTAR_A68N5200_CLONE + bool "A68N-5200-CLONE" diff --git a/src/mainboard/hp/t620/Makefile.inc b/src/mainboard/hp/t620/Makefile.inc new file mode 100644 index 0000000..549801d --- /dev/null +++ b/src/mainboard/hp/t620/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/hp/t620/OemCustomize.c b/src/mainboard/hp/t620/OemCustomize.c new file mode 100644 index 0000000..18db540 --- /dev/null +++ b/src/mainboard/hp/t620/OemCustomize.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <PlatformMemoryConfiguration.h> + +#include <northbridge/amd/agesa/state_machine.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERRIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS(LAYERS_4), + + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/t620/OptionsIds.h b/src/mainboard/hp/t620/OptionsIds.h new file mode 100644 index 0000000..130d852 --- /dev/null +++ b/src/mainboard/hp/t620/OptionsIds.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +#endif diff --git a/src/mainboard/hp/t620/acpi/AmdImc.asl b/src/mainboard/hp/t620/acpi/AmdImc.asl new file mode 100644 index 0000000..4483834 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/AmdImc.asl @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Local0 = 0 + While (Local0 != 0xfa) { + Local0 = MRG0 + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 1 + MRG2 = 0 + MSTI = 0x98 + WACK() + + MRG0 = 0 + MRG1 = 0xb4 + MRG2 = 0 + MSTI = 0x96 + WACK() +} + +//Wake +Method (IMWK, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} diff --git a/src/mainboard/hp/t620/acpi/gpe.asl b/src/mainboard/hp/t620/acpi/gpe.asl new file mode 100644 index 0000000..778c7f7 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/gpe.asl @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/hp/t620/acpi/mainboard.asl b/src/mainboard/hp/t620/acpi/mainboard.asl new file mode 100644 index 0000000..9b18e72 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/hp/t620/acpi/routing.asl b/src/mainboard/hp/t620/acpi/routing.asl new file mode 100644 index 0000000..9bce4b2 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/routing.asl @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/hp/t620/acpi/sata.asl b/src/mainboard/hp/t620/acpi/sata.asl new file mode 100644 index 0000000..659a076 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sata.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* No SATA functionality */ diff --git a/src/mainboard/hp/t620/acpi/sleep.asl b/src/mainboard/hp/t620/acpi/sleep.asl new file mode 100644 index 0000000..fc26c30 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sleep.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + USBS = 1 + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/hp/t620/acpi/superio.asl b/src/mainboard/hp/t620/acpi/superio.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/hp/t620/acpi/thermal.asl b/src/mainboard/hp/t620/acpi/thermal.asl new file mode 100644 index 0000000..853b087 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/thermal.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/hp/t620/acpi/usb_oc.asl b/src/mainboard/hp/t620/acpi/usb_oc.asl new file mode 100644 index 0000000..a5846fe --- /dev/null +++ b/src/mainboard/hp/t620/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/hp/t620/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c new file mode 100644 index 0000000..70bc10c --- /dev/null +++ b/src/mainboard/hp/t620/bootblock.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +static void sbxxx_enable_48mhzout(void) +{ + u32 reg32; + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + reg32 = misc_read32(0x28); + reg32 &= 0xfff8ffff; + misc_write32(0x28, reg32); + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + reg32 = misc_read32(0x40); + reg32 &= 0xffffbffb; + misc_write32(0x40, reg32); +} + +void bootblock_mainboard_early_init(void) +{ + u8 byte; + + /* Enable the AcpiMmio space */ + pm_io_write8(0x24, 1); + + /* Set LPC decode enables. */ + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + + /* enable SIO LPC decode */ + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + + /* Enable serial output on it8728f */ + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/t620/buildOpts.c b/src/mainboard/hp/t620/buildOpts.c new file mode 100644 index 0000000..f5c2181 --- /dev/null +++ b/src/mainboard/hp/t620/buildOpts.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE + +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +#include <PlatformInstall.h> diff --git a/src/mainboard/hp/t620/cmos.layout b/src/mainboard/hp/t620/cmos.layout new file mode 100644 index 0000000..a11e1dd --- /dev/null +++ b/src/mainboard/hp/t620/cmos.layout @@ -0,0 +1,35 @@ +#***************************************************************************** +# SPDX-License-Identifier: GPL-2.0-only + +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb new file mode 100644 index 0000000..c036b65 --- /dev/null +++ b/src/mainboard/hp/t620/devicetree.cb @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 off end # mPCIe slot + device pci 2.3 off end # Realtek NIC + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + #register "multi_function_register_1" = "0x01" + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 + end + device pnp 2e.4 on # Hardware Monitor + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + irq 0xf1 = 0x00 + irq 0xf2 = 0x04 + irq 0xf3 = 0xa0 + irq 0xf5 = 0x0f + irq 0xf9 = 0xa0 + irq 0xfa = 0x04 + end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + end + device pnp 2e.6 off end # KBC? + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end + device pnp 2e.9 off end + device pnp 2e.a off end # IR + end # ITE IT8728F + end #LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/agesa/hudson + + chip northbridge/amd/agesa/family16kb + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end + + end #domain +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/t620/dsdt.asl b/src/mainboard/hp/t620/dsdt.asl new file mode 100644 index 0000000..c86cf27 --- /dev/null +++ b/src/mainboard/hp/t620/dsdt.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_SB) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/hp/t620/irq_tables.c b/src/mainboard/hp/t620/irq_tables.c new file mode 100644 index 0000000..6d75c05 --- /dev/null +++ b/src/mainboard/hp/t620/irq_tables.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <string.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/hp/t620/mainboard.c b/src/mainboard/hp/t620/mainboard.c new file mode 100644 index 0000000..3ebc0c1 --- /dev/null +++ b/src/mainboard/hp/t620/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(struct device *dev) +{ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/71608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 71608 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71607 ) Change subject: amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb ...................................................................... amd smm: Add missing amd_mp_ops_no_smm struct and tie in to fam16kb Change-Id: I6b159433c111525aed1451acfd2540eab8fdc8f7 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/cpu/amd/agesa/Makefile.inc M src/soc/amd/common/block/cpu/smm/smm_relocate.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/71607/1 diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 5d8f6df..fd727e6 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -5,3 +5,4 @@ romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_relocate.c diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index 4d33b65..4f23826 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -92,3 +92,8 @@ .per_cpu_smm_trigger = smm_relocation_handler, .post_mp_init = global_smi_enable, }; + +const struct mp_ops amd_mp_ops_no_smm = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/71607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b159433c111525aed1451acfd2540eab8fdc8f7 Gerrit-Change-Number: 71607 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: agesa/common: Add missing VOID
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71606 ) Change subject: agesa/common: Add missing VOID ...................................................................... agesa/common: Add missing VOID Change-Id: Ifd2339ef69e14ffa48c2b652a76b4dce5b35277b Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/agesa/common/amdlib.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/71606/1 diff --git a/src/vendorcode/amd/agesa/common/amdlib.c b/src/vendorcode/amd/agesa/common/amdlib.c index dbfdce8..fb1cf94 100644 --- a/src/vendorcode/amd/agesa/common/amdlib.c +++ b/src/vendorcode/amd/agesa/common/amdlib.c @@ -457,7 +457,9 @@ } VOID -LibAmdFinit() +LibAmdFinit( + VOID + ) { /* TODO: finit */ __asm__ volatile ("finit"); -- To view, visit https://review.coreboot.org/c/coreboot/+/71606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd2339ef69e14ffa48c2b652a76b4dce5b35277b Gerrit-Change-Number: 71606 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: cpu/amd/smm: Remove dead code
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71605 ) Change subject: cpu/amd/smm: Remove dead code ...................................................................... cpu/amd/smm: Remove dead code Change-Id: I9c2d3f23be45c8ae76609e0e650864e4ad7a5ad3 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- D src/cpu/amd/smm/Makefile.inc D src/cpu/amd/smm/smm_init.c 2 files changed, 10 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/71605/1 diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc deleted file mode 100644 index 97a6694..0000000 --- a/src/cpu/amd/smm/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ - -ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c deleted file mode 100644 index 75dd4506..0000000 --- a/src/cpu/amd/smm/smm_init.c +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> -#include <cpu/x86/smi_deprecated.h> -#include <string.h> - -void smm_init(void) -{ - msr_t msr, syscfg_orig, mtrr_aseg_orig; - - /* Back up MSRs for later restore */ - syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); - - /* MTRR changes don't like an enabled cache */ - disable_cache(); - - msr = syscfg_orig; - - /* Allow changes to MTRR extended attributes */ - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - /* turn the extended attributes off until we fix - * them so A0000 is routed to memory - */ - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* set DRAM access to 0xa0000 */ - msr.lo = 0x18181818; - msr.hi = 0x18181818; - wrmsr(MTRR_FIX_16K_A0000, msr); - - /* enable the extended features */ - msr = syscfg_orig; - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - enable_cache(); - /* copy the real SMM handler */ - memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start); - wbinvd(); - disable_cache(); - - /* Restore SYSCFG and MTRR */ - wrmsr(SYSCFG_MSR, syscfg_orig); - wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); - enable_cache(); - - /* CPU MSR are set in CPU init */ -} - -void smm_init_completion(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/71605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2d3f23be45c8ae76609e0e650864e4ad7a5ad3 Gerrit-Change-Number: 71605 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71604 ) Change subject: nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4 ...................................................................... nb/amd/agesa/family16kb: Enable RESOURCE_ALLOCATOR_V4 Change-Id: Id02f119b786c19cd3fc185cae7f1abcd2daa2b67 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/northbridge/amd/agesa/family16kb/Kconfig 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/71604/1 diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index faea30d..8953377 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,7 +2,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool - select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB -- To view, visit https://review.coreboot.org/c/coreboot/+/71604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id02f119b786c19cd3fc185cae7f1abcd2daa2b67 Gerrit-Change-Number: 71604 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: Revert "{cpu/nb}/amd/family16: Remove platform"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71603 ) Change subject: Revert "{cpu/nb}/amd/family16: Remove platform" ...................................................................... Revert "{cpu/nb}/amd/family16: Remove platform" This reverts commit 49af4f7f9197e559b2c7142129441679bb1d24a2. Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/Makefile.inc A src/cpu/amd/agesa/family16kb/Kconfig A src/cpu/amd/agesa/family16kb/Makefile.inc A src/cpu/amd/agesa/family16kb/acpi/cpu.asl A src/cpu/amd/agesa/family16kb/chip_name.c A src/cpu/amd/agesa/family16kb/fixme.c A src/cpu/amd/agesa/family16kb/model_16_init.c A src/northbridge/amd/agesa/Makefile.inc A src/northbridge/amd/agesa/family16kb/Kconfig A src/northbridge/amd/agesa/family16kb/Makefile.inc A src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl A src/northbridge/amd/agesa/family16kb/acpi_tables.c A src/northbridge/amd/agesa/family16kb/chip.h A src/northbridge/amd/agesa/family16kb/dimmSpd.c A src/northbridge/amd/agesa/family16kb/northbridge.c A src/northbridge/amd/agesa/family16kb/pci_devs.h A src/northbridge/amd/agesa/family16kb/state_machine.c M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c 20 files changed, 1,342 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/71603/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d46d2ed..f6c4f16 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -2,6 +2,7 @@ config CPU_AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY16_KB default n select ARCH_X86 select DRIVERS_AMD_PI @@ -43,3 +44,5 @@ from non-volatile memory. endif # CPU_AMD_AGESA + +source "src/cpu/amd/agesa/family16kb/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4cacc51..5d8f6df 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,4 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only + +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb + romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..60bf64f --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CPU_AMD_AGESA_FAMILY16_KB + bool + select SMM_ASEG + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_AGESA_FAMILY16_KB + +config FORCE_AM1_SOCKET_SUPPORT + bool + default n + help + Force AGESA to ignore package type mismatch between CPU and northbridge + in memory code. This enables Socket AM1 support with current AGESA + version for Kabini platform. + Enable this option only if you have Socket AM1 board. + Note that the AGESA release shipped with coreboot does not officially + support the AM1 socket. Selecting this option might damage your hardware. + +endif diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..9464372 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += fixme.c + +ramstage-y += fixme.c +ramstage-y += chip_name.c +ramstage-y += model_16_init.c + +subdirs-y += ../../mtrr diff --git a/src/cpu/amd/agesa/family16kb/acpi/cpu.asl b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl new file mode 100644 index 0000000..d589ae8 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/acpi/cpu.asl @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Processor Object + * + */ +Scope (\_SB) {/* define processor scope */ + Device (P000) { + Name(_HID, "ACPI0007") + Name(_UID, 0) + } + + Device (P001) { + Name(_HID, "ACPI0007") + Name(_UID, 1) + } + + Device (P002) { + Name(_HID, "ACPI0007") + Name(_UID, 2) + } + + Device (P003) { + Name(_HID, "ACPI0007") + Name(_UID, 3) + } + + Device (P004) { + Name(_HID, "ACPI0007") + Name(_UID, 4) + } + + Device (P005) { + Name(_HID, "ACPI0007") + Name(_UID, 5) + } + + Device (P006) { + Name(_HID, "ACPI0007") + Name(_UID, 6) + } + + Device (P007) { + Name(_HID, "ACPI0007") + Name(_UID, 7) + } +} /* End _SB scope */ diff --git a/src/cpu/amd/agesa/family16kb/chip_name.c b/src/cpu/amd/agesa/family16kb/chip_name.c new file mode 100644 index 0000000..0ca021c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/chip_name.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations cpu_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD CPU Family 16h Model 00h-0Fh") +}; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c new file mode 100644 index 0000000..da2744c --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/hpet.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <northbridge/amd/agesa/agesa_helper.h> +#include <AGESA.h> +#include <amdlib.h> + +void amd_initcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of SB800 legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); +} diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c new file mode 100644 index 0000000..0f11136 --- /dev/null +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/cpu.h> +#include <amdblocks/smm.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +static void model_16_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Model 16 Init.\n"); + + msr_t msr; + int msrno; +#if CONFIG(LOGICAL_CPUS) + u32 siblings; +#endif + + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. + */ + disable_cache(); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr(MTRR_FIX_16K_A0000, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); + for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) + wrmsr(msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + if (acpi_is_wakeup_s3()) + restore_mtrr(); + + x86_mtrr_check(); + enable_cache(); + + /* zero the machine check error status registers */ + mca_clear_status(); + +#if CONFIG(LOGICAL_CPUS) + siblings = get_cpu_count() - 1; // minus BSP + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + /* Write protect SMM space with SMMLOCK. */ + lock_smm(); +} + +static struct device_operations cpu_dev_ops = { + .init = model_16_init, +}; + +static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc new file mode 100644 index 0000000..f586623 --- /dev/null +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y) + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb + +endif diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig new file mode 100644 index 0000000..8cf919a --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + bool + select LEGACY_SMP_INIT + select RESOURCE_ALLOCATOR_V3 + +if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xF8000000 + +config ECAM_MMCONF_BUS_NUMBER + default 64 + +config VGA_BIOS_ID + string + default "1002,9830" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +endif # NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc new file mode 100644 index 0000000..e387ee5 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += dimmSpd.c + +ramstage-y += northbridge.c +ramstage-y += acpi_tables.c + +romstage-y += state_machine.c +ramstage-y += state_machine.c diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl new file mode 100644 index 0000000..a635247 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ +Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + +/* Describe the Northbridge devices */ + +Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ +{ + Return(Zero) +} + +Method(_STA, 0, NotSerialized) +{ + Return(0x0B) /* Status is visible */ +} + +Method(_PRT,0, NotSerialized) +{ + If(PICM) + { + Return(APR0) /* APIC mode */ + } + Return (PR0) /* PIC Mode */ +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Gpp 0 */ +Device(PBR4) { + Name(_ADR, 0x00020001) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR4 */ + +/* Gpp 1 */ +Device(PBR5) { + Name(_ADR, 0x00020002) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR5 */ + +/* Gpp 2 */ +Device(PBR6) { + Name(_ADR, 0x00020003) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR6 */ + +/* Gpp 3 */ +Device(PBR7) { + Name(_ADR, 0x00020004) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR7 */ + +/* Gpp 4 */ +Device(PBR8) { + Name(_ADR, 0x00020005) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PICM) { Return(APS8) } /* APIC mode */ + Return (PS8) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR8 */ + +Device(K10M) { + Name (_ADR, 0x00180003) + #include <soc/amd/common/acpi/thermal_zone.asl> +} diff --git a/src/northbridge/amd/agesa/family16kb/acpi_tables.c b/src/northbridge/amd/agesa/family16kb/acpi_tables.c new file mode 100644 index 0000000..cf88cfa --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/acpi_tables.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/ioapic.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB800 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + /* TODO: Remove the hardcode */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS + 1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/northbridge/amd/agesa/family16kb/chip.h b/src/northbridge/amd/agesa/family16kb/chip.h new file mode 100644 index 0000000..239bc69 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _NB_AGESA_CHIP_H_ +#define _NB_AGESA_CHIP_H_ + +struct northbridge_amd_agesa_family16kb_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c new file mode 100644 index 0000000..1f9d970 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include <Porting.h> +#include <AGESA.h> +#include "chip.h" + +#include <northbridge/amd/agesa/dimmSpd.h> + +/** + * Gets the SMBus address for an SPD from the array in devicetree.cb + * then read the SPD into the supplied buffer. + */ +AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) +{ + UINT8 spdAddress; + + DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); + if (dev == NULL) + return AGESA_ERROR; + + DEVTREE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info; + if (config == NULL) + return AGESA_ERROR; + + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) + return AGESA_ERROR; + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) + return AGESA_ERROR; + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + int err = hudson_readSpd(spdAddress, (void *)info->Buffer, DDR3_SPD_SIZE); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c new file mode 100644 index 0000000..250c491 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -0,0 +1,741 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/pci_ops.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> +#include <Porting.h> +#include <AGESA.h> +#include <Options.h> +#include <Topology.h> +#include <northbridge/amd/nb_common.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define MAX_NODE_NUMS MAX_NODES + +static unsigned int node_nums; +static unsigned int sblink; +static struct device *__f0_dev[MAX_NODE_NUMS]; +static struct device *__f1_dev[MAX_NODE_NUMS]; +static struct device *__f2_dev[MAX_NODE_NUMS]; +static struct device *__f4_dev[MAX_NODE_NUMS]; +static unsigned int fx_devs = 0; + +static struct device *get_node_pci(u32 nodeid, u32 fn) +{ + return pcidev_on_root(DEV_CDB + nodeid, fn); +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i + 1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned int reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned int reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for (i = 0; i < fx_devs; i++) { + struct device *dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) +{ + u32 temp; + + if (fx_devs == 0) + get_fx_devs(); + + + temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] + if (!(temp & 1)) + return 0; // this memory range is not enabled + /* + * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits + * for physical address and the convert to KiB by shifting 10 bits left + */ + *basek = ((temp & 0xffff0000)) >> (10 - 8); + /* + * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but + * ORed with 0xffff to get real limit before shifting. + */ + temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] + *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); + *limitk += 1; // round up last byte + + return 1; +} + +static u32 amdfam16_nodeid(struct device *dev) +{ + return (dev->path.pci.devfn >> 3) - DEV_CDB; +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid << 4) | (linkn << 12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +static void read_resources(struct device *dev) +{ + /* + * This MMCONF resource must be reserved in the PCI_DOMAIN. + * It is not honored by the coreboot resource allocator if it is in + * the APIC_CLUSTER. + */ + mmconf_resource(dev, MMIO_CONF_BASE); + + /* There should be no BAR. */ +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(struct device *dev, unsigned int nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG(MULTIPLE_VGA_ADAPTERS) + extern struct device *vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary, link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if ((vga_pri->bus->secondary >= link->secondary) && + (vga_pri->bus->secondary <= link->subordinate)) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(struct device *dev) +{ + unsigned int nodeid; + + /* Find the nodeid */ + nodeid = amdfam16_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +static void northbridge_fill_ssdt_generator(const struct device *device) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static void patch_ssdt_processor_scope(acpi_header_t *ssdt) +{ + unsigned int len = ssdt->length - sizeof(acpi_header_t); + unsigned int i; + + for (i = sizeof(acpi_header_t); i < len; i++) { + /* Search for _PR_ scope and replace it with _SB_ */ + if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) + *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; + } + /* Recalculate checksum */ + ssdt->checksum = 0; + ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); +} + +static unsigned long agesa_write_acpi_tables(const struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN_UP(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; + + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *)current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *)current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *)current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *)current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN_UP(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); + if (ssdt != NULL) { + patch_ssdt_processor_scope(ssdt); + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *)current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp, ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, +}; + +static const struct pci_driver family16_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_16H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VID_AMD, + .device = PCI_DID_AMD_10H_NB_HT, +}; + +static void fam16_finalize(void *chip_info) +{ + struct device *dev; + u32 value; + dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = pcidev_on_root(1, 1); + if (dev != NULL) { + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_ops = { + CHIP_NAME("AMD FAM16 Northbridge") + .enable_dev = 0, + .final = fam16_finalize, +}; + +static void domain_read_resources(struct device *dev) +{ + unsigned int reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg += 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned int nodeid, reg_link; + struct device *reg_dev; + if (reg < 0xc0) { // mmio + nodeid = (limit & 0xf) + (base & 0x30); + } else { // io + nodeid = (limit & 0xf) + ((base >> 4) & 0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + + pci_domain_read_resources(dev); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned int hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk; + u32 hole; + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 2) { // we find the hole + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i = 0; i < node_nums; i++) { + resource_t base_k, limit_k; + if (!get_dram_base_limit(i, &base_k, &limit_k)) + continue; // no memory on this node + if (base_k > 4 * 1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned int)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +static void domain_set_resources(struct device *dev) +{ + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) - 1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64 * 1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) + mmio_basek = mem_hole.hole_startk; +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + resource_t basek, limitk, sizek; // 4 1T + + if (!get_dram_base_limit(i, &basek, &limitk)) + continue; // no memory on this node + + sizek = limitk - basek; + + /* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */ + if (basek < 640 && sizek > 768) { + ram_resource_kb(dev, (idx | i), basek, 640 - basek); + idx += 0x10; + basek = 768; + sizek = limitk - basek; + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accommodate pci memory space */ + if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned int pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek > 0) { + ram_resource_kb(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4 * 1024 * 1024) { + sizek = 0; + } + else { + uint64_t topmem2 = amd_topmem2(); + basek = 4 * 1024 * 1024; + sizek = topmem2 / 1024 - basek; + } + } + + ram_resource_kb(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + } + + add_uma_resource_below_tolm(dev, 7); + + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static const char *domain_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, +}; + +static void sysconf_init(struct device *dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64) >> 8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1; //NodeCnt[2:0] +} + +static void cpu_bus_scan(struct device *dev) +{ + struct bus *cpu_bus; + struct device *dev_mc; + int i, j; + int coreid_bits; + int core_max = 0; + unsigned int ApicIdCoreIdSize; + unsigned int core_nums; + int siblings = 0; + unsigned int family; + + dev_mc = pcidev_on_root(DEV_CDB, 0); + if (!dev_mc) { + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); + die(""); + } + sysconf_init(dev_mc); + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008) >> 12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + struct device *cdb_dev; + unsigned int devn; + struct bus *pbus; + + devn = DEV_CDB + i; + pbus = dev_mc->bus; + + /* Find the cpu's pci device */ + cdb_dev = pcidev_on_root(devn, 0); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for (fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = pcidev_on_root(devn, 0); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + add_more_links(cdb_dev, 4); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = pcidev_on_root(devn, 3); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 7) {//f16 + cdb_dev = pcidev_on_root(devn, 5); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply APIC enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + + u8 plat_num_io_apics = 3; /* FIXME */ + + if ((node_nums * core_max) + plat_num_io_apics >= 0x10) { + lapicid_start = (plat_num_io_apics - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i / modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } +} + +static void cpu_bus_init(struct device *dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_agesa_family16kb_root_complex_ops = { + CHIP_NAME("AMD FAM16 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/********************************************************************* + * Change the vendor / device IDs to match the generic VBIOS header. * + *********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x10029830: + case 0x10029831: + case 0x10029832: + case 0x10029833: + case 0x10029834: + case 0x10029835: + case 0x10029836: + case 0x10029837: + case 0x10029838: + case 0x10029839: + case 0x1002983A: + case 0x1002983D: + new_vendev = 0x10029830; // This is the default value in AMD-generated VBIOS + break; + default: + break; + } + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h new file mode 100644 index 0000000..f226cd3 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _AMD_FAM16KB_PCI_DEVS_H_ +#define _AMD_FAM16KB_PCI_DEVS_H_ + +#include <device/pci_def.h> + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) + +/* Internal Audio Controller */ +#define ACTL_FUNC 1 +#define ACTL_DEVFN PCI_DEVFN(GFX_DEV, ACTL_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT1_FUNC 0x1 +#define NB_PCIE_PORT2_FUNC 0x2 +#define NB_PCIE_PORT3_FUNC 0x3 +#define NB_PCIE_PORT4_FUNC 0x4 +#define NB_PCIE_PORT5_FUNC 0x5 +#define NB_PCIE_DEV 2 +#define NB_PCIE_PORT_DEVID 0x1439 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT1_FUNC) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT2_FUNC) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT3_FUNC) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT4_FUNC) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_PORT5_FUNC) + +#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */ diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c new file mode 100644 index 0000000..cbf0313 --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/biosram.h> + +#include <Porting.h> +#include <AGESA.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + AGESA_STATUS status; + + Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, + MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; + + if (CONFIG(ENABLE_MRC_CACHE)) { + status = OemInitResume(&Post->MemConfig.MemContext); + if (status == AGESA_SUCCESS) + Post->MemConfig.MemRestoreCtl = 1; + } +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ + OemInitResume(&Resume->S3DataBlock); +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + OemS3LateRestore(&S3Late->S3DataBlock); +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ + OemS3Save(&S3Save->S3DataBlock); +} diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 4bc6a3d..4468cc3 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -159,6 +159,20 @@ default 181 range 1 255 +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + config CUSTOM_SPD_TWTR int "[26]: Min Internal Write to Read Command Delay, tWTR" default 105 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c index 08d7fcb..d3c8303 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c @@ -489,7 +489,10 @@ return TRUE; } } - return FALSE; + if (CONFIG(FORCE_AM1_SOCKET_SUPPORT)) + return TRUE; + else + return FALSE; } /* -----------------------------------------------------------------------------*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/71603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d41a626228baed81b467e284268c9a5cc57aca Gerrit-Change-Number: 71603 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: Revert "vendorcode/amd/agesa/family16: Drop unused platform"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71602 ) Change subject: Revert "vendorcode/amd/agesa/family16: Drop unused platform" ...................................................................... Revert "vendorcode/amd/agesa/family16: Drop unused platform" This reverts commit 7036ded25d3a051902862e2a7bdfe15916f0951d. Change-Id: I1782946f293c866c9a88f2a7824b0fe7dc4e6297 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/agesa/Makefile.inc A src/vendorcode/amd/agesa/f16kb/AGESA.h A src/vendorcode/amd/agesa/f16kb/AMD.h A src/vendorcode/amd/agesa/f16kb/Config/OptionApmInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionC6Install.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCditInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpbInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuCacheFlushOnHaltInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuCoreLevelingInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFamiliesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCpuSpecificServicesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionCratInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionDmiInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionGfxRecoveryInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionHtInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionHtcInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionIdsInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionIoCstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionL3FeaturesInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionLowPwrPstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMmioMapInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMsgBasedC1eInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPrefetchModeInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPreserveMailboxInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPsiInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPstateHpcModeInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionS3ScriptInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionSlitInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionSratInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionTdpLimitingInstall.h A src/vendorcode/amd/agesa/f16kb/Config/OptionWheaInstall.h A src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h A src/vendorcode/amd/agesa/f16kb/Dispatcher.h A src/vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h A src/vendorcode/amd/agesa/f16kb/Include/CommonReturns.h A src/vendorcode/amd/agesa/f16kb/Include/Filecode.h A src/vendorcode/amd/agesa/f16kb/Include/GeneralServices.h A src/vendorcode/amd/agesa/f16kb/Include/GnbInterface.h A src/vendorcode/amd/agesa/f16kb/Include/Ids.h A src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h A src/vendorcode/amd/agesa/f16kb/Include/IdsPerf.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h A src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h A src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h A src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h A src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h A src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h A src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h A src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h A src/vendorcode/amd/agesa/f16kb/Include/OptionPstate.h A src/vendorcode/amd/agesa/f16kb/Include/OptionSlit.h A src/vendorcode/amd/agesa/f16kb/Include/OptionSrat.h A src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h A src/vendorcode/amd/agesa/f16kb/Include/Options.h A src/vendorcode/amd/agesa/f16kb/Include/OptionsHt.h A src/vendorcode/amd/agesa/f16kb/Include/PlatformMemoryConfiguration.h A src/vendorcode/amd/agesa/f16kb/Include/Topology.h A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c A src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c A src/vendorcode/amd/agesa/f16kb/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/PreserveMailbox.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuApm.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuC6State.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheFlushOnHalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCdit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCoreLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCpb.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCrat.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuDmi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatureLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuIoCstate.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuL3Features.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuMsgBasedC1e.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPrefetchMode.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateGather.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateHpcMode.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateLeveling.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPstateTables.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSlit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuSrat.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuTdpLimiting.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuWhea.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuApicUtilities.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuBist.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEnvInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuGeneralServices.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPostInit.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmt.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSingleSocket.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuPowerMgmtSystemTables.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuServices.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuWarmReset.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c A src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h A src/vendorcode/amd/agesa/f16kb/Proc/CPU/mmioMapManager.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdFch.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitPost.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitResume.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdLateRunApTask.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3LateRestore.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdS3Save.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonInits.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/CommonReturns.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h A src/vendorcode/amd/agesa/f16kb/Proc/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c A src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/AzaliaReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Azalia/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/AcpiLib.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchBiosRamUsage.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommon.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/MemLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/FchPlatform.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/HwmLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Hwm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/IdeMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Ide/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/FchEcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchInitS3.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/FchTaskLauncher.h A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/AbReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Family/Yangtze/YangtzeAbService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Pcie/PcieReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/AhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Ide2AhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/RaidMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataEnvLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataIdeMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataLib.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/SataReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/SdMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/LpcReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/SpiReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/EhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeOhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciLateService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciMidService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/OhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/UsbReset.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciLate.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciMid.c A src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/XhciReset.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbF1Table.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfx.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbGfxFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbIommu.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbLibFeatures.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcieFamServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommon.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersCommonV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUra.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbUraToken.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEarly.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtLate.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtMid.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtPost.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtReset.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/GnbInitAtS3Save.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/GnbIoapic.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbIoapic/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV5/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/GnbPcieTrainingV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSSocketLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSbLib/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/GnbSview.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSview/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.h A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c A src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbFam16.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/Fam16/htNbUtilitiesFam16.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htFeat.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterface.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceCoherent.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceGeneral.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htInterfaceNonCoherent.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htMain.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNb.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNbCommonHardware.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.c A src/vendorcode/amd/agesa/f16kb/Proc/HT/htNotify.h A src/vendorcode/amd/agesa/f16kb/Proc/HT/htTopologies.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebugPrint.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpHdtout.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDpSerial.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbNvDef.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/IDS/IdsLib.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsLib.c A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/IdsRegAcc.h A src/vendorcode/amd/agesa/f16kb/Proc/IDS/Library/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ardk/ma.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CRAT/mfCrat.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/CSINTLV/mfcsi.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfecc.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ECC/mfemp.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/IDENDIMM/mfidendimm.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/LVDDR3/mflvddr3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/MEMCLR/mfmemclr.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/PARTRN/mfStandardTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/S3/mfs3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/TABLE/mftds.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/KB/mmflowkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mdef.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/merrhdl.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/minit.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmConditionalPso.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmEcc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmExcludeDimm.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmLvDdr3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemClr.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmNodeInterleave.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmOnlineSpare.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmParallelTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmStandardTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmUmaAlloc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmlvddr3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnS3kb.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mndctkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnflowkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnidendimmkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnmctkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnotkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mn.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnS3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnfeat.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnflow.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnmct.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnreg.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mntrain3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmr0.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpodtpat.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mprtt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mps2d.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpsao.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtlrdimm3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtot3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtrci3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtsdi3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttecc3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mttwl3.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/Makefile.inc A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mthdi.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttdimbt.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttecc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttml.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttoptsrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttsrc.c A src/vendorcode/amd/agesa/f16kb/Proc/Mem/ma.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/merrhdl.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfParallelTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfStandardTraining.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfmemclr.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mfs3.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mftds.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mm.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnpmu.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mnreg.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mp.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mport.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mt.h A src/vendorcode/amd/agesa/f16kb/Proc/Mem/mu.h A src/vendorcode/amd/agesa/f16kb/gcccar.inc 729 files changed, 229,121 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/71602/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1782946f293c866c9a88f2a7824b0fe7dc4e6297 Gerrit-Change-Number: 71602 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: Revert "vendorcode/amd/agesa: Drop unused common code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71601 ) Change subject: Revert "vendorcode/amd/agesa: Drop unused common code" ...................................................................... Revert "vendorcode/amd/agesa: Drop unused common code" This reverts commit 0f12381083fdfc7bb3e6f3b2ac5cd6247506c543. Change-Id: I2726767999b10e1fa3527a67719a4f7c1b93eb5c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/vendorcode/amd/Makefile.inc A src/vendorcode/amd/agesa/Kconfig A src/vendorcode/amd/agesa/Makefile.inc A src/vendorcode/amd/agesa/common/Makefile.inc A src/vendorcode/amd/agesa/common/agesa-entry-cfg.h A src/vendorcode/amd/agesa/common/agesa-entry.c A src/vendorcode/amd/agesa/common/amdlib.c A src/vendorcode/amd/agesa/common/amdlib.h A src/vendorcode/amd/agesa/common/debug_util.c A src/vendorcode/amd/agesa/common/debug_util.h 10 files changed, 2,215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/71601/1 diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc index 9cdbe60..8cce5e6 100644 --- a/src/vendorcode/amd/Makefile.inc +++ b/src/vendorcode/amd/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += pi +subdirs-y += agesa subdirs-y += cimx diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..4bc6a3d --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config IDS_OPTIONS_HOOKED_UP + bool + help + to Kconfig options. + Historically, IDS configuration was defined in a mainboard-specific + `OptionsIds.h` header. Select this on platforms where IDS config is + hooked up to Kconfig options instead. + +if IDS_OPTIONS_HOOKED_UP + +config IDS_ENABLED + bool "Enable AGESA IDS (Integrated Debug Services) support" + default y + help + This is the master switch for the IDS sub-system. Use this option to + enable or remove the entire IDS feature set. This switch must be TRUE + for any of the other options to function. + +comment "Warning: IDS options may not work. Enable at your own risk!" + depends on IDS_ENABLED + +config IDS_CONTROL_ENABLED + bool "Enable IDS User Interface controls" + depends on IDS_ENABLED + help + This is the main switch for the IDS configuration controls. This + switch must be TRUE for any of the configuration controls to function. + + This seems to allow AGESA to retrieve settings from CMOS. + +config IDS_PERF_ANALYSIS + bool "Enable IDS performance analysis" + depends on IDS_ENABLED + help + This is the main switch for the IDS performance analysis controls, + macros and support code needed to enable time data gathering. This + switch must be TRUE for any of the performance analysis features to + function. + +config IDS_TRACING_ENABLED + bool "Enable IDS console" + depends on IDS_ENABLED + help + This is the main switch for the IDS console controls, macros and + support code needed to enable tracing of algorithms. This switch + must be TRUE for any of the tracing features to function. + +config IDS_TRACING_CONSOLE_SERIAL + bool "Use serial port as IDS console" + depends on IDS_TRACING_ENABLED + default DRIVERS_UART_8250IO && CONSOLE_SERIAL + help + Use an I/O-mapped serial port to output IDS messages. + +endif # IDS_OPTIONS_HOOKED_UP + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, e.g. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +endchoice + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc new file mode 100644 index 0000000..9d78195 --- /dev/null +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -0,0 +1,41 @@ + +ifeq ($(CONFIG_CPU_AMD_AGESA),y) + +subdirs-y += common + +classes-y += libagesa +libagesa-y = +libagesa-generic-ccopts += -D__LIBAGESA__ +libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +libagesa-generic-ccopts += -Wno-pragma-pack -Wno-unused-but-set-variable +libagesa-generic-ccopts += -Wno-implicit-fallthrough + +romstage-generic-ccopts += -Wno-pragma-pack +ramstage-generic-ccopts += -Wno-pragma-pack + +AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing + +CFLAGS_x86_32 += $(AGESA_CFLAGS) +CFLAGS_x86_64 += $(AGESA_CFLAGS) + +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +$(eval $(call create_class_compiler,libagesa,x86_32)) +else +$(eval $(call create_class_compiler,libagesa,x86_64)) +endif + +$(obj)/libagesa.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + $(AR_libagesa) rcsDT $@ $+ + +romstage-libs += $(obj)/libagesa.a +ramstage-libs += $(obj)/libagesa.a + +# buildOpts should be in libagesa +$(obj)/romstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) +$(obj)/ramstage/mainboard/$(MAINBOARDDIR)/buildOpts.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) + +$(obj)/romstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) +$(obj)/ramstage/vendorcode/amd/agesa/common/agesa-entry.o: CPPFLAGS_x86_32 += $(BUILDOPTS_INCLUDES) + +endif diff --git a/src/vendorcode/amd/agesa/common/Makefile.inc b/src/vendorcode/amd/agesa/common/Makefile.inc new file mode 100644 index 0000000..a7ddc7f --- /dev/null +++ b/src/vendorcode/amd/agesa/common/Makefile.inc @@ -0,0 +1,36 @@ +#***************************************************************************** +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +romstage-y += agesa-entry.c +ramstage-y += agesa-entry.c + +libagesa-y += debug_util.c +libagesa-y += amdlib.c + +# Do not optimise performance-critical low-level IO for size with -Os, +# request -O2 with -falign-functions. + +$(obj)/libagesa/vendorcode/amd/agesa/common/amdlib.o: CFLAGS_libagesa += -O2 diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h new file mode 100644 index 0000000..3302574 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -0,0 +1,82 @@ +#ifndef AGESA_ENTRY_CFG_H +#define AGESA_ENTRY_CFG_H + + +#if ENV_RAMINIT + +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE + +#define AGESA_ENTRY_INIT_RESUME CONFIG(HAVE_ACPI_RESUME) + +#else + +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE CONFIG(HAVE_ACPI_RESUME) + +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE \ + (CONFIG(HAVE_ACPI_RESUME) || \ + CONFIG(ENABLE_MRC_CACHE)) + +#endif + +/* Not required. */ +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +/* Required for any multi-core. */ +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + +/* Deprecated, reference source is removed from the tree. */ +#define AGESA_ENTRY_INIT_RECOVERY FALSE + +/* Defaults below. */ + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#endif + +#endif /* AGESA_ENTRY_CFG_H */ diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c new file mode 100644 index 0000000..42f12b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -0,0 +1,165 @@ +#include <Porting.h> +#include <AMD.h> +#include <AGESA.h> + +#include "CommonReturns.h" + +#include <heapManager.h> +#include <CreateStruct.h> + +#include <Options.h> + +#include <agesa-entry-cfg.h> + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL } +}; + +CONST UINTN InitializerCount = ARRAY_SIZE(FuncParamsInfo); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; diff --git a/src/vendorcode/amd/agesa/common/amdlib.c b/src/vendorcode/amd/agesa/common/amdlib.c new file mode 100644 index 0000000..dbfdce8 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/amdlib.c @@ -0,0 +1,1266 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "amdlib.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE LIB_AMDLIB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +UINT8 +ReadIo8 ( + IN UINT16 Address + ) +{ + return __inbyte (Address); +} +UINT16 +ReadIo16 ( + IN UINT16 Address + ) +{ + return __inword (Address); +} +UINT32 +ReadIo32 ( + IN UINT16 Address + ) +{ + return __indword (Address); +} +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ) +{ + __outbyte (Address, Data); +} +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ) +{ + __outword (Address, Data); +} +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ) +{ + __outdword (Address, Data); +} +STATIC +UINT64 SetFsBase ( + UINT64 address + ) +{ + UINT64 hwcr; + hwcr = __readmsr (0xC0010015); + __writemsr (0xC0010015, hwcr | 1 << 17); + __writemsr (0xC0000100, address); + return hwcr; +} +STATIC +VOID +RestoreHwcr ( + UINT64 + value + ) +{ + __writemsr (0xC0010015, value); +} +UINT8 +Read64Mem8 ( + IN UINT64 Address + ) +{ + UINT8 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT8 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsbyte (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT16 +Read64Mem16 ( + IN UINT64 Address + ) +{ + UINT16 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT16 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsword (0); + RestoreHwcr (hwcrSave); + return dataRead; +} +UINT32 +Read64Mem32 ( + IN UINT64 Address + ) +{ + UINT32 dataRead; + UINT64 hwcrSave; + if ((Address >> 32) == 0) { + return *(volatile UINT32 *) (UINTN) Address; + } + hwcrSave = SetFsBase (Address); + dataRead = __readfsdword (0); + RestoreHwcr (hwcrSave); + return dataRead; + } +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT8 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsbyte (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT16 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ) +{ + if ((Address >> 32) == 0){ + *(volatile UINT32 *) (UINTN) Address = Data; + } + else { + UINT64 hwcrSave; + hwcrSave = SetFsBase (Address); + __writefsdword (0, Data); + RestoreHwcr (hwcrSave); + } +} +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ) +{ + *Value = 0; + switch (RegNum){ + case CR4_REG: + *Value = __readcr4 (); + break; + case DR0_REG: + *Value = __readdr (0); + break; + case DR1_REG: + *Value = __readdr (1); + break; + case DR2_REG: + *Value = __readdr (2); + break; + case DR3_REG: + *Value = __readdr (3); + break; + case DR7_REG: + *Value = __readdr (7); + break; + default: + *Value = -1; + break; + } +} +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ) +{ + switch (RegNum){ + case CR4_REG: + __writecr4 (Value); + break; + case DR0_REG: + __writedr (0, Value); + break; + case DR1_REG: + __writedr (1, Value); + break; + case DR2_REG: + __writedr (2, Value); + break; + case DR3_REG: + __writedr (3, Value); + break; + case DR7_REG: + __writedr (7, Value); + break; + default: + break; + } +} +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ) +{ + __wbinvd (); +} +VOID +LibAmdHDTBreakPoint ( + VOID + ) +{ + __writemsr (0xC001100A, __readmsr (0xC001100A) | 1); + __debugbreak (); // do you really need icebp? If so, go back to asm code +} +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ) +{ + UINTN Index; + for (Index = 0; Index < 32; Index++){ + if (value & (1 << Index)) break; + } + return (UINT8) Index; +} + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value +) +{ + uint8_t bit = 31; + do { + if (value & (1 << 31)) + return bit; + + value <<= 1; + bit--; + + } while (value != 0); + + return 0xFF; /* Error code indicating no bit found */ +} + +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + *Value = __readmsr (MsrAddress); +} +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + CONST IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __writemsr (MsrAddress, *Value); +} +void LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA* Value, + IN OUT AMD_CONFIG_PARAMS *ConfigPtr + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} +UINT64 +ReadTSC ( + VOID + ) +{ + return __rdtsc (); +} +VOID +LibAmdSimNowEnterDebugger ( + VOID + ) +{ + STATIC CONST UINT8 opcode [] = {0x60, // pushad + 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2 + 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B + 0x0F, 0xA2, // cpuid + 0x61, // popad + 0xC3 // ret + }; + ((VOID (*)(VOID)) (size_t) opcode) (); // call the function +} + +#ifdef __SSE3__ +VOID F10RevDProbeFilterCritical ( + IN PCI_ADDR PciAddress, + IN UINT32 PciRegister + ) +{ + UINT64 msrsave; + msrsave = __readmsr (0xC001001F); + __writemsr (0xC001001F, msrsave | 1ULL << 46); // EnableCf8ExtCfg + _mm_mfence (); + __outdword (0xCF8, PciAddress.AddressValue); + _mm_mfence (); + __outdword (0xCFC, PciRegister | 2); + _mm_mfence (); + __writemsr (0xC001001F, msrsave); +} + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ) +{ + UINT64 hwcrSave; + UINT8 *address32; + UINTN Index; + address32 = 0; + hwcrSave = SetFsBase (Address); + for (Index = 0; Index < Count; Index++){ + _mm_mfence (); + _mm_clflush_fs (&address32 [Index * 64]); + } + RestoreHwcr (hwcrSave); +} +#endif //__SSE3__ + +VOID +StopHere ( + VOID + ) +{ + VOLATILE UINTN x = 1; + while (x); +} + +VOID +LibAmdFinit() +{ + /* TODO: finit */ + __asm__ volatile ("finit"); +} +/*---------------------------------------------------------------------------------------*/ +/** + * Read IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to save data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = ReadIo8 (IoAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = ReadIo16 (IoAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = ReadIo32 (IoAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write IO port + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO port address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + WriteIo8 (IoAddress, *(UINT8 *) Value); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + WriteIo16 (IoAddress, *(UINT16 *) Value); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + WriteIo32 (IoAddress, *(UINT32 *) Value); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * IO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value = 0; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll IO register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] IoAddress IO address + * @param[in] Data Data to compare + * @param[in] DataMask And mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *(UINT8 *) Value = Read64Mem8 (MemAddress); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *(UINT16 *) Value = Read64Mem16 (MemAddress); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *(UINT32 *) Value = Read64Mem32 (MemAddress); + break; + default: + ASSERT (FALSE); + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write memory/MMIO + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Write64Mem8 (MemAddress, *((UINT8 *) Value)); + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Write64Mem16 (MemAddress, *((UINT16 *) Value)); + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Write64Mem32 (MemAddress, *((UINT32 *) Value)); + break; + default: + ASSERT (FALSE); + break; + } +} +/*---------------------------------------------------------------------------------------*/ +/** + * Memory/MMIO read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data OR data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll Mmio + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] MemAddress Memory address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000ull; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write PCI config space + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LegacyPciAccess; + UINT32 MMIOSize; + UINT64 RMWrite; + UINT64 RMWritePrevious; + UINT64 MMIOAddress; + + ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + // We need to convert our "portable" PCI address into a "real" PCI access + LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); + if (PciAddress.Address.Register <= 0xFF) { + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + } else { + LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + RMWrite = RMWritePrevious | 0x0000400000000000ull; + LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + } + } else { + // Setup the MMIO address + ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); + MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); + LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * PCI read modify write + * + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data OR Data + * @param[in] DataMask Mask to be used before data write back to register. + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + Value = (Value & (~TempMask)) | TempData; + LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Poll PCI config space register + * + * Poll register until (RegisterValue & DataMask) == Data + * + * @param[in] AccessWidth Access width + * @param[in] PciAddress Pci address + * @param[in] Data Data to compare + * @param[in] DataMask AND mask + * @param[in] Delay Poll for time in 100ns (not supported) + * @param[in] StdHeader Standard configuration header + * + */ +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempData = 0; + UINT32 TempMask = 0; + UINT32 Value; + LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); + do { + LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + } while (TempData != (Value & TempMask)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get MMIO base address for PCI accesses + * + * @param[out] MmioAddress PCI MMIO base address + * @param[out] MmioSize Size of region in bytes + * @param[in] StdHeader Standard configuration header + * + * @retval TRUE MmioAddress/MmioSize are valid + */ +BOOLEAN +STATIC +GetPciMmioAddress ( + OUT UINT64 *MmioAddress, + OUT UINT32 *MmioSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN MmioIsEnabled; + UINT32 EncodedSize; + UINT64 MsrReg; + + ASSERT (StdHeader != NULL); + + MmioIsEnabled = FALSE; + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); + if ((MsrReg & BIT0) != 0) { + *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull; + EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2); + *MmioSize = ((1 << EncodedSize) * 0x100000); + MmioIsEnabled = TRUE; + } + return MmioIsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Read field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[out] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + LibAmdPciRead (AccessWidth32, Address, Value, StdHeader); + *Value >>= Lowbit; // Shift + + // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Write field of PCI config register. + * + * + * + * @param[in] Address Pci address (register must be DWORD aligned) + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[in] Value Pointer to data + * @param[in] StdHeader Standard configuration header + */ +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Temp; + UINT32 Mask; + + ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); + + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32) 0xFFFFFFFF; + } + + LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader); + Temp &= ~(Mask << Lowbit); + Temp |= (*Value & Mask) << Lowbit; + LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Locate next capability pointer + * + * Given a SBDFO this routine will find the next PCI capabilities list entry. + * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is + * returned. + * To start a new search from the head of the list, specify a SBDFO with an offset of zero. + * + * @param[in,out] Address Pci address + * @param[in] StdHeader Standard configuration header + */ + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR Base; + UINT32 Offset; + UINT32 Temp; + PCI_ADDR TempAddress; + + ASSERT (Address != NULL); + ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO); + + Base.AddressValue = Address->AddressValue; + Offset = Base.Address.Register; + Base.Address.Register = 0; + + Address->AddressValue = (UINT32) ILLEGAL_SBDFO; + + // Verify that the SBDFO points to a valid PCI device SANITY CHECK + LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader); + if (Temp == 0xFFFFFFFF) { + ASSERT (FALSE); + return; // There is no device at this address + } + + // Verify that the device supports a capability list + TempAddress.AddressValue = Base.AddressValue + 0x04; + LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader); + if (Temp == 0) { + return; // This PCI device does not support capability lists + } + + if (Offset != 0) { + // If we are continuing on an existing list + TempAddress.AddressValue = Base.AddressValue + Offset; + LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader); + } else { + // We are starting on a new list + TempAddress.AddressValue = Base.AddressValue + 0x34; + LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader); + } + + if (Temp == 0) { + return; // We have reached the end of the capabilities list + } + + // Error detection and recovery- The statement below protects against + // PCI devices with broken PCI capabilities lists. Detect a pointer + // that is not uint32 aligned, points into the first 64 reserved DWORDs + // or points back to itself. + if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) { + ASSERT (FALSE); + return; + } + + Address->AddressValue = Base.AddressValue + Temp; + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set memory with value + * + * + * @param[in,out] Destination Pointer to memory range + * @param[in] Value Value to set memory with + * @param[in] FillLength Size of the memory range + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + ASSERT (StdHeader != NULL); + Dest = Destination; + while ((FillLength--) != 0) { + *Dest++ = Value; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Copy memory + * + * + * @param[in,out] Destination Pointer to destination buffer + * @param[in] Source Pointer to source buffer + * @param[in] CopyLength buffer length + * @param[in] StdHeader Standard configuration header (Optional) + */ +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 *Dest; + CONST UINT8 *SourcePtr; + ASSERT (StdHeader != NULL); + Dest = Destination; + SourcePtr = Source; + while ((CopyLength--) != 0) { + *Dest++ = *SourcePtr++; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] StdHeader Standard configuration header (Optional) + */ + +// Returns the package type mask for the processor +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProcessorPackageType; + CPUID_DATA CpuId; + + LibAmdCpuidRead (0x80000001, &CpuId, StdHeader); + ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + return (UINT32) (1 << ProcessorPackageType); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @param[in] Data data + * @param[in] DataMask data + * @param[out] TemData typecast data + * @param[out] TempDataMask typecast data + */ + + +VOID +STATIC +LibAmdGetDataFromPtr ( + IN ACCESS_WIDTH AccessWidth, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + OUT UINT32 *TemData, + OUT UINT32 *TempDataMask + ) +{ + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + *TemData = (UINT32)*(UINT8 *) Data; + *TempDataMask = (UINT32)*(UINT8 *) DataMask; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + *TemData = (UINT32)*(UINT16 *) Data; + *TempDataMask = (UINT32)*(UINT16 *) DataMask; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + *TemData = *(UINT32 *) Data; + *TempDataMask = *(UINT32 *) DataMask; + break; + default: + IDS_ERROR_TRAP; + break; + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the package type mask for the processor + * + * + * @param[in] AccessWidth Access width + * @retval Width in number of bytes + */ + + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ) +{ + UINT8 Width; + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Width = 1; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Width = 2; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Width = 4; + break; + case AccessWidth64: + case AccessS3SaveWidth64: + Width = 8; + break; + default: + Width = 0; + IDS_ERROR_TRAP; + break; + } + return Width; +} + +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ) +{ + __cpuid ((int *)Value, CpuidFcnAddress); +} + +UINT8 +ReadNumberOfCpuCores( + VOID + ) +{ + CPUID_DATA Value; + CpuidRead (0x80000008, &Value); + return Value.ECX_Reg & 0xff; +} diff --git a/src/vendorcode/amd/agesa/common/amdlib.h b/src/vendorcode/amd/agesa/common/amdlib.h new file mode 100644 index 0000000..5ba3952 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/amdlib.h @@ -0,0 +1,398 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Library + * + * Contains interface to the AMD AGESA library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Lib + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _AMD_LIB_H_ +#define _AMD_LIB_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define IOCF8 0xCF8 +#define IOCFC 0xCFC + +// Reg Values for ReadCpuReg and WriteCpuReg +#define CR0_REG 0x00 +#define CR4_REG 0x04 +#define DR0_REG 0x10 +#define DR1_REG 0x11 +#define DR2_REG 0x12 +#define DR3_REG 0x13 +#define DR7_REG 0x17 + +UINT8 +ReadIo8 ( + IN UINT16 Address + ); + +UINT16 +ReadIo16 ( + IN UINT16 Address + ); + +UINT32 +ReadIo32 ( + IN UINT16 Address + ); + +VOID +WriteIo8 ( + IN UINT16 Address, + IN UINT8 Data + ); + +VOID +WriteIo16 ( + IN UINT16 Address, + IN UINT16 Data + ); + +VOID +WriteIo32 ( + IN UINT16 Address, + IN UINT32 Data + ); + +UINT8 +Read64Mem8 ( + IN UINT64 Address + ); + +UINT16 +Read64Mem16 ( + IN UINT64 Address + ); + +UINT32 +Read64Mem32 ( + IN UINT64 Address + ); + +VOID +Write64Mem8 ( + IN UINT64 Address, + IN UINT8 Data + ); + +VOID +Write64Mem16 ( + IN UINT64 Address, + IN UINT16 Data + ); + +VOID +Write64Mem32 ( + IN UINT64 Address, + IN UINT32 Data + ); + +UINT64 +ReadTSC ( + VOID + ); + +// MSR +VOID +LibAmdMsrRead ( + IN UINT32 MsrAddress, + OUT UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMsrWrite ( + IN UINT32 MsrAddress, + CONST IN UINT64 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// IO +VOID +LibAmdIoRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdIoPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT16 IoAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Memory or MMIO +VOID +LibAmdMemRead ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemWrite ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemRMW ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemPoll ( + IN ACCESS_WIDTH AccessWidth, + IN UINT64 MemAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// PCI +VOID +LibAmdPciRead ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + OUT VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWrite ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciRMW ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciPoll ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR PciAddress, + IN CONST VOID *Data, + IN CONST VOID *DataMask, + IN UINT64 Delay, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciReadBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + OUT UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciWriteBits ( + IN PCI_ADDR Address, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN CONST UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdPciFindNextCap ( + IN OUT PCI_ADDR *Address, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// CPUID +VOID +LibAmdCpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +// Utility Functions +VOID +LibAmdMemFill ( + IN VOID *Destination, + IN UINT8 Value, + IN UINTN FillLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +LibAmdMemCopy ( + IN VOID *Destination, + IN CONST VOID *Source, + IN UINTN CopyLength, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +LibAmdGetPackageType ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +LibAmdBitScanReverse ( + IN UINT32 value + ); +UINT8 +LibAmdBitScanForward ( + IN UINT32 value + ); + +VOID +LibAmdReadCpuReg ( + IN UINT8 RegNum, + OUT UINT32 *Value + ); +VOID +LibAmdWriteCpuReg ( + IN UINT8 RegNum, + IN UINT32 Value + ); + +VOID +LibAmdWriteBackInvalidateCache ( + IN VOID + ); + +VOID +LibAmdSimNowEnterDebugger (VOID); + +VOID +LibAmdHDTBreakPoint (VOID); + +UINT8 +LibAmdAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ); + +VOID +LibAmdCLFlush ( + IN UINT64 Address, + IN UINT8 Count + ); + +VOID F10RevDProbeFilterCritical ( + IN PCI_ADDR PciAddress, + IN UINT32 PciRegister + ); + +VOID +LibAmdFinit ( + VOID + ); + +VOID +StopHere ( + VOID + ); + +/* For f14 or older. */ +VOID +CpuidRead ( + IN UINT32 CpuidFcnAddress, + OUT CPUID_DATA *Value + ); + +UINT8 +ReadNumberOfCpuCores( + VOID + ); + +/* From 16kb, no implementation supplied. */ +VOID +LibAmdFnclex ( + VOID); + +VOID +LibAmdReadMxcsr ( + OUT UINT32 *Value + ); +VOID +LibAmdWriteMxcsr ( + IN UINT32 *Value + ); + + +#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/agesa/common/debug_util.c b/src/vendorcode/amd/agesa/common/debug_util.c new file mode 100644 index 0000000..29d0841 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.c @@ -0,0 +1,24 @@ + +#include <AGESA.h> +#include <AMD.h> +#include <heapManager.h> + +#include "debug_util.h" + +static const char undefined[] = "undefined"; + +static const char *HeapStatusStr[] = { + "DoNotExistYet", "LocalCache", "TempMem", "SystemMem", "DoNotExistAnymore","S3Resume" +}; + +/* This function has to match with enumeration of XXXX defined + * inside heapManager.h header file. + */ +const char *heap_status_name(UINT8 HeapStatus) +{ + if ((HeapStatus < HEAP_DO_NOT_EXIST_YET) || (HeapStatus > HEAP_S3_RESUME)) + return undefined; + + int index = HeapStatus - HEAP_DO_NOT_EXIST_YET; + return HeapStatusStr[index]; +} diff --git a/src/vendorcode/amd/agesa/common/debug_util.h b/src/vendorcode/amd/agesa/common/debug_util.h new file mode 100644 index 0000000..a8d9a33 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/debug_util.h @@ -0,0 +1,8 @@ +#ifndef __AGESA_DEBUG_UTIL_H__ +#define __AGESA_DEBUG_UTIL_H__ + +#include "AMD.h" + +const char *heap_status_name(UINT8 HeapStatus); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/71601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2726767999b10e1fa3527a67719a4f7c1b93eb5c Gerrit-Change-Number: 71601 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: Revert "cpu/amd/agesa: Remove leftover code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71600 ) Change subject: Revert "cpu/amd/agesa: Remove leftover code" ...................................................................... Revert "cpu/amd/agesa: Remove leftover code" This reverts commit 81a4fefce223ba358310aec2d988484202c176e2. Change-Id: Icf2b15a158fc4a22e07d0051e4f23dd804a4a148 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/arch/x86/include/arch/cpu.h M src/cpu/amd/Kconfig M src/cpu/amd/Makefile.inc A src/cpu/amd/agesa/Kconfig A src/cpu/amd/agesa/Makefile.inc A src/cpu/amd/smm/Makefile.inc A src/cpu/amd/smm/smm_init.c M src/drivers/amd/agesa/Makefile.inc M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/state_machine.c M src/northbridge/amd/agesa/Kconfig M src/vendorcode/amd/Kconfig M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 14 files changed, 191 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/71600/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 18bc961..7f99137 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -101,7 +101,7 @@ static inline bool cpu_is_amd(void) { - return CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON); + return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON); } static inline bool cpu_is_intel(void) diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 0369ebd..db8989d 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -1 +1,2 @@ +source "src/cpu/amd/agesa/Kconfig" source "src/cpu/amd/pi/Kconfig" diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 94089bd..5c07a66 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -1 +1,2 @@ +subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa subdirs-$(CONFIG_CPU_AMD_PI) += pi diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig new file mode 100644 index 0000000..d46d2ed --- /dev/null +++ b/src/cpu/amd/agesa/Kconfig @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CPU_AMD_AGESA + bool + default n + select ARCH_X86 + select DRIVERS_AMD_PI + select TSC_SYNC_LFENCE + select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER + select SPI_FLASH if HAVE_ACPI_RESUME + select SSE2 + select CACHE_MRC_SETTINGS + +if CPU_AMD_AGESA + +config UDELAY_LAPIC_FIXED_FSB + int + default 200 + +# TODO: Sync these with definitions in AGESA vendorcode. +# DCACHE_RAM_BASE must equal BSP_STACK_BASE_ADDR. +# DCACHE_RAM_SIZE must equal BSP_STACK_SIZE. + +config DCACHE_RAM_BASE + hex + default 0x30000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config ENABLE_MRC_CACHE + bool "Use cached memory configuration" + default n + select SPI_FLASH + help + Try to restore memory training results + from non-volatile memory. + +endif # CPU_AMD_AGESA diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc new file mode 100644 index 0000000..4cacc51 --- /dev/null +++ b/src/cpu/amd/agesa/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +postcar-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c +ramstage-y += ../../../soc/amd/common/block/cpu/smm/smm_helper.c diff --git a/src/cpu/amd/smm/Makefile.inc b/src/cpu/amd/smm/Makefile.inc new file mode 100644 index 0000000..97a6694 --- /dev/null +++ b/src/cpu/amd/smm/Makefile.inc @@ -0,0 +1,2 @@ + +ramstage-y += smm_init.c diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c new file mode 100644 index 0000000..75dd4506 --- /dev/null +++ b/src/cpu/amd/smm/smm_init.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <cpu/x86/smi_deprecated.h> +#include <string.h> + +void smm_init(void) +{ + msr_t msr, syscfg_orig, mtrr_aseg_orig; + + /* Back up MSRs for later restore */ + syscfg_orig = rdmsr(SYSCFG_MSR); + mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); + + /* MTRR changes don't like an enabled cache */ + disable_cache(); + + msr = syscfg_orig; + + /* Allow changes to MTRR extended attributes */ + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + /* turn the extended attributes off until we fix + * them so A0000 is routed to memory + */ + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* set DRAM access to 0xa0000 */ + msr.lo = 0x18181818; + msr.hi = 0x18181818; + wrmsr(MTRR_FIX_16K_A0000, msr); + + /* enable the extended features */ + msr = syscfg_orig; + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + enable_cache(); + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start); + wbinvd(); + disable_cache(); + + /* Restore SYSCFG and MTRR */ + wrmsr(SYSCFG_MSR, syscfg_orig); + wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); + enable_cache(); + + /* CPU MSR are set in CPU init */ +} + +void smm_init_completion(void) +{ +} diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index fbbf044..6d80c4c 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -21,4 +21,7 @@ ramstage-y += heapmanager.c ramstage-y += acpi_tables.c +romstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c +ramstage-$(CONFIG_CPU_AMD_AGESA) += oem_s3.c s3_mtrr.c + endif diff --git a/src/drivers/amd/agesa/acpi_tables.c b/src/drivers/amd/agesa/acpi_tables.c index c4a4e18..1c09d3f 100644 --- a/src/drivers/amd/agesa/acpi_tables.c +++ b/src/drivers/amd/agesa/acpi_tables.c @@ -8,7 +8,8 @@ /* Fields were removed from the structure and we cannot add them back * without new builds of the binaryPI blobs. */ -#if CONFIG(NORTHBRIDGE_AMD_PI_00730F01) +#if !CONFIG(CPU_AMD_AGESA_BINARY_PI) || \ + CONFIG(NORTHBRIDGE_AMD_PI_00730F01) #define HAS_ACPI_SRAT TRUE #define HAS_ACPI_SLIT TRUE diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index b819dff..2ff4d44 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -14,6 +14,10 @@ #include <AMD.h> +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) +#include "Dispatcher.h" +#endif + #if ENV_RAMINIT #include <PlatformMemoryConfiguration.h> CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; @@ -21,6 +25,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader) { +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) const char ModuleIdentifier[] = AGESA_ID; const void *agesa, *image; size_t file_size; @@ -32,6 +37,7 @@ image = LibAmdLocateImage(agesa, agesa + file_size, 4096, ModuleIdentifier); StdHeader->ImageBasePtr = (void *)image; +#endif } void agesa_set_interface(struct sysinfo *cb) @@ -40,13 +46,15 @@ cb->StdHeader.CalloutPtr = GetBiosCallout; - agesa_locate_image(&cb->StdHeader); - AMD_IMAGE_HEADER *image = - (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; - ASSERT(image); - AMD_MODULE_HEADER *module = - (void *)(uintptr_t)image->ModuleInfoOffset; - ASSERT(module && module->ModuleDispatcher); + if (CONFIG(CPU_AMD_AGESA_BINARY_PI)) { + agesa_locate_image(&cb->StdHeader); + AMD_IMAGE_HEADER *image = + (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; + ASSERT(image); + AMD_MODULE_HEADER *module = + (void *)(uintptr_t)image->ModuleInfoOffset; + ASSERT(module && module->ModuleDispatcher); + } } AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, @@ -54,9 +62,14 @@ { MODULE_ENTRY dispatcher; +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE) + dispatcher = AmdAgesaDispatcher; +#endif +#if CONFIG(CPU_AMD_AGESA_BINARY_PI) AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr; AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset; dispatcher = module->ModuleDispatcher; +#endif StdHeader->Func = func; return dispatcher(StdHeader); diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ccfbbf..6f6e3d63 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA bool + default CPU_AMD_AGESA if NORTHBRIDGE_AMD_AGESA diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index b095916..2378616 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -1,10 +1,42 @@ # SPDX-License-Identifier: GPL-2.0-only -if CPU_AMD_PI || SOC_AMD_PI +if CPU_AMD_AGESA || CPU_AMD_PI || SOC_AMD_PI menu "AMD Platform Initialization" +choice + prompt "AGESA source" + default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI + default CPU_AMD_AGESA_BINARY_PI if SOC_AMD_PI + default CPU_AMD_AGESA_OPENSOURCE if CPU_AMD_AGESA + help + Select the method for including the AMD Platform Initialization + code into coreboot. Platform Initialization code is required for + all AMD processors. + +config CPU_AMD_AGESA_BINARY_PI + bool "binary PI" + help + Use a binary PI package. Generally, these will be stored in the + "3rdparty/blobs" directory. For some processors, these must be obtained + directly from AMD Embedded Processors Group + (http://www.amd.com/embedded). + +config CPU_AMD_AGESA_OPENSOURCE + bool "open-source AGESA" + help + Build the PI package ("AGESA") from source code in the "vendorcode" + directory. + +endchoice + +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + +if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" +endif config AGESA_EXTRA_TIMESTAMPS bool "Add instrumentation for AGESA calls" diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 96c3ea9..71898a3 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -85,7 +85,7 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS]) -classes-y += libagesa +classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) @@ -136,7 +136,7 @@ $(AGESA_POST_MEM_ELF_RMOD): $(AGESA_POST_MEM_ELF) -cbfs-files-y += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME) $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE) $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip @@ -144,7 +144,7 @@ # 64 byte alignment. $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096 -cbfs-files-y += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(AGESA_POST_MEM_ELF_RMOD) $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-compression := $(CBFS_COMPRESS_FLAG) @@ -158,7 +158,7 @@ files_added:: warn_no_agesa else -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) $(CONFIG_AGESA_CBFS_NAME)-file := $(AGESA_BINARYPI_INPUT_FILE) ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index d36671a..9b4659e 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -108,7 +108,7 @@ agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c) endif -classes-y += libagesa +classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) @@ -135,7 +135,7 @@ ####################################################################### -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) $(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) -- To view, visit https://review.coreboot.org/c/coreboot/+/71600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf2b15a158fc4a22e07d0051e4f23dd804a4a148 Gerrit-Change-Number: 71600 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "nb/amd/agesa: Remove leftover code"
by Damien Zammit (Code Review) 01 Jan '23

01 Jan '23

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71599 ) Change subject: Revert "nb/amd/agesa: Remove leftover code" ...................................................................... Revert "nb/amd/agesa: Remove leftover code" This reverts commit 1a010236cf922fc28cfb36b604bdf17a9ea3cb82. Change-Id: If26ce3136f809d5b0714fc344ddff1f8df3789bc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/northbridge/amd/agesa/Kconfig 1 file changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/71599/1 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig new file mode 100644 index 0000000..2ccfbbf --- /dev/null +++ b/src/northbridge/amd/agesa/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_AMD_AGESA + bool + +if NORTHBRIDGE_AMD_AGESA + +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0x80000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present, for example, graphic cards. + +config CONSOLE_VGA_MULTI + bool + default n + +config S3_VGA_ROM_RUN + bool + default n + +source "src/northbridge/amd/agesa/*/Kconfig" + +# TODO: Reservation for heap seems excessive +config HEAP_SIZE + hex + default 0xc0000 + +endif # NORTHBRIDGE_AMD_AGESA -- To view, visit https://review.coreboot.org/c/coreboot/+/71599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If26ce3136f809d5b0714fc344ddff1f8df3789bc Gerrit-Change-Number: 71599 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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