coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel: Create common function to check PCH slot
by Kapil Porwal (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71236 ) Change subject: soc/intel: Create common function to check PCH slot ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/include/intelblocks/irq.h: https://review.coreboot.org/c/coreboot/+/71236/comment/4f3365d2_9775832b PS4, Line 69: /* Check if given slot is a PCH slot. */ > consider adding more meaningful comment to explain how a PCH less SoC platform like MTL will still b […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/71236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Gerrit-Change-Number: 71236 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:44:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (1 comment) Patchset: PS23: @Paul, Please do help with the review of this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/pc80/vga: Add API to write multi-line video message
by Kapil Porwal (Code Review) 02 Jan '23

02 Jan '23

Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71265 ) Change subject: drivers/pc80/vga: Add API to write multi-line video message ...................................................................... Patch Set 8: (1 comment) File src/drivers/pc80/vga/vga.c: https://review.coreboot.org/c/coreboot/+/71265/comment/fa9d2497_47d2388c PS3, Line 303: memcpy(str, string, strlen(string)); > > I dont think we should attempt to handle line wrapping and leave it to the creation of the string […] Yes, I agree. I suggested this because of the below observations - 1. Characters post VGA_COLUMNS are suppressed (i.e. not printed). 2. We expect user of vga_write_text() to be aware of VGA_COLUMNS. -- To view, visit https://review.coreboot.org/c/coreboot/+/71265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Gerrit-Change-Number: 71265 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd.h: Move enum ddr2_module_type to ddr2.h
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Reka Norman, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71546 ) Change subject: spd.h: Move enum ddr2_module_type to ddr2.h ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Gerrit-Change-Number: 71546 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:07:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd.h: Move enum ddr3_module_type to ddr3.h
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jakub Czapiga, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71547 ) Change subject: spd.h: Move enum ddr3_module_type to ddr3.h ...................................................................... Patch Set 2: Code-Review+1 (2 comments) File src/device/dram/ddr3.c: https://review.coreboot.org/c/coreboot/+/71547/comment/c1e99edc_f2edbb11 PS2, Line 537: switch (info->dimm_type) { : case SPD_DDR3_DIMM_TYPE_SO_DIMM: : dimm->mod_type = DDR3_SPD_SODIMM; : break; : case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: : dimm->mod_type = DDR3_SPD_72B_SO_CDIMM; : break; : case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: : dimm->mod_type = DDR3_SPD_72B_SO_RDIMM; : break; : case SPD_DDR3_DIMM_TYPE_UDIMM: : dimm->mod_type = DDR3_SPD_UDIMM; : break; : case SPD_DDR3_DIMM_TYPE_RDIMM: : dimm->mod_type = DDR3_SPD_RDIMM; : break; : case SPD_DDR3_DIMM_TYPE_UNDEFINED: : default: : dimm->mod_type = SPD_UNDEFINED; : break; : } This catches invalid SPD types and replaces them with an "undefined" value. The new approach is simpler but doesn't do this. It doesn't seem to be a big deal anyway. The bus width being hardcoded to 64 is more of a problem, actually. File src/northbridge/intel/haswell/haswell_mrc/raminit.c: https://review.coreboot.org/c/coreboot/+/71547/comment/fe58466c_e81d0b61 PS2, Line 264: dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; Reminds us that this shouldn't be hardcoded -- To view, visit https://review.coreboot.org/c/coreboot/+/71547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Gerrit-Change-Number: 71547 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:06:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/topology: Add code to fill in topology on struct path
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Shuming Chu (Shuming), Arthur Heymans, Kyösti Mälkki, TangYiwei. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69222 ) Change subject: cpu/x86/topology: Add code to fill in topology on struct path ...................................................................... Patch Set 15: (1 comment) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/69222/comment/8a3b8a22_94f2ecd6 PS15, Line 8: #define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b : #define LEVEL_TYPE_CORE 2 : #define LEVEL_TYPE_SMT 1 Isn't this already defined elsewhere? Why not define this in a header? -- To view, visit https://review.coreboot.org/c/coreboot/+/69222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Gerrit-Change-Number: 69222 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Mon, 02 Jan 2023 12:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/haswell: Specify supported memory type
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71583 ) Change subject: nb/intel/haswell: Specify supported memory type ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71583/comment/18af60b5_1ad9b593 PS4, Line 12: Note: DDR4 is not supported in coreboot yet for current northbridge. It will never be. Haswell-EP and Haswell-EX would have a separate northbridge folder, so this note is inaccurate. It'd be better to not say anything about DDR4. However, if you want to write something, how about: > Haswell "client" (as opposed to Haswell "server", e.g. Haswell-EP and Haswell-EX) only supports DDR3 and, only on ULT, LPDDR3. Given that coreboot uses a DDR3-compatible format for LPDDR3 SPDs, Haswell only needs `USE_DDR3`. File src/northbridge/intel/haswell/Kconfig: https://review.coreboot.org/c/coreboot/+/71583/comment/d65cb26a_c8cc2c77 PS2, Line 6: if NORTHBRIDGE_INTEL_HASWELL : : config NORTHBRIDGE_SPECIFIC_OPTIONS : def_bool y > Done Sorry for being unclear. Could you please change this in a separate follow-up change? Actually, we'd prefer to not introduce dummy Kconfig symbols if there's no need. If you want consistency, it would make more sense to drop `NORTHBRIDGE_SPECIFIC_OPTIONS` instead. It should be possible to do so for all Intel northbridges. -- To view, visit https://review.coreboot.org/c/coreboot/+/71583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5 Gerrit-Change-Number: 71583 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 12:00:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/ironlake: Specify supported memory type
by Angel Pons (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71584 ) Change subject: nb/intel/ironlake: Specify supported memory type ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/ironlake/Kconfig: https://review.coreboot.org/c/coreboot/+/71584/comment/29b0f812_33bdf213 PS1, Line 6: if NORTHBRIDGE_INTEL_IRONLAKE : : config NORTHBRIDGE_SPECIFIC_OPTIONS : def_bool y > Done Sorry for being unclear. Could you please change this in a separate follow-up change? -- To view, visit https://review.coreboot.org/c/coreboot/+/71584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2 Gerrit-Change-Number: 71584 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:52:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd.h: Move enum ddr3_module_type to ddr3.h
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jakub Czapiga, Angel Pons, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71547 ) Change subject: spd.h: Move enum ddr3_module_type to ddr3.h ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71547/comment/a9683982_52c7ed8b PS2, Line 9: pecific specific -- To view, visit https://review.coreboot.org/c/coreboot/+/71547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Gerrit-Change-Number: 71547 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: spd.h: Move enum ddr2_module_type to ddr2.h
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Reka Norman, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71546 ) Change subject: spd.h: Move enum ddr2_module_type to ddr2.h ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71546/comment/f8c83d3f_15d556ab PS2, Line 9: pecific specific -- To view, visit https://review.coreboot.org/c/coreboot/+/71546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I748658f9b349bff9b1ebe2c0a6acf71bf2a221ce Gerrit-Change-Number: 71546 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 02 Jan 2023 11:46:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023