coreboot-gerrit January 2023

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[S] Change in coreboot[master]: mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGE
by Martin L Roth (Code Review) 02 Jan '23

02 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71192 ) Change subject: mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGE ...................................................................... mb/google/drallion: Set touchpad/screen IRQs to LEVEL vs EDGE The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index a9de097..6001a86 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -378,7 +378,7 @@ chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "10" @@ -397,14 +397,14 @@ chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 2c on end end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "detect" = "1" device i2c 15 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/71192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2 Gerrit-Change-Number: 71192 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/drallion: Implement touchscreen power sequencing
by Martin L Roth (Code Review) 02 Jan '23

02 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71191 ) Change subject: mb/google/drallion: Implement touchscreen power sequencing ...................................................................... mb/google/drallion: Implement touchscreen power sequencing For touchscreens on drallion, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 32 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index b008427..2acb35b 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -65,7 +65,7 @@ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -111,7 +111,7 @@ /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -249,10 +249,16 @@ return early_gpio_table; } +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +}; + const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/71191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875 Gerrit-Change-Number: 71191 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/drallion: Add method to set GPIOs in romstage
by Martin L Roth (Code Review) 02 Jan '23

02 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71190 ) Change subject: mb/google/drallion: Add method to set GPIOs in romstage ...................................................................... mb/google/drallion: Add method to set GPIOs in romstage Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h 3 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 15f9c8d..bea4fee 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -4,14 +4,20 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <baseboard/variants.h> +#include <variant/gpio.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg board_memcfg; + const struct pad_config *pads; + size_t pads_num; variant_mainboard_post_init_params(memupd); wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, get_variant_memory_cfg(&board_memcfg)); + + pads = variant_romstage_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); } diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 6220bf2..b008427 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -249,6 +249,12 @@ return early_gpio_table; } +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index db0b3a9..ee48fec 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -28,5 +28,6 @@ const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/71190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700 Gerrit-Change-Number: 71190 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i440bx: Specify supported memory type
by Martin L Roth (Code Review) 02 Jan '23

02 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70575 ) Change subject: nb/intel/i440bx: Specify supported memory type ...................................................................... nb/intel/i440bx: Specify supported memory type Change-Id: If94037f2b010527440795e6920dd7a533c52f606 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70575 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i440bx/Kconfig 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 7b41f05..8908cea 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -5,6 +5,11 @@ select NO_ECAM_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE + select NO_DDR5 + select NO_LPDDR4 + select NO_DDR4 + select NO_DDR3 + select NO_DDR2 config SDRAMPWR_4DIMM bool -- To view, visit https://review.coreboot.org/c/coreboot/+/70575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If94037f2b010527440795e6920dd7a533c52f606 Gerrit-Change-Number: 70575 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: Add minimal GNAT run time system (RTS)
by Reto Buerki (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Nico Huber. Reto Buerki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11836 ) Change subject: Add minimal GNAT run time system (RTS) ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > What is there to do? If this is added via the Makefile, guard it depending on the GCC version? We al […] We hit the same problem in Muen: https://git.codelabs.ch/?p=muen.git;a=commit;h=456631ade6e3babefe245d46cd20… Compiler_Unit[_Warning] pragmas are no longer recognized by newer GNAT toolchains. -- To view, visit https://review.coreboot.org/c/coreboot/+/11836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6522abf093f0a516b9ae18ddc69131bd721dc0c Gerrit-Change-Number: 11836 Gerrit-PatchSet: 15 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 02 Jan 2023 17:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSID
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71275 ) Change subject: soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSID ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/71275/comment/c049aac9_7cda97ee PS1, Line 545: .ops_pci = &pci_dev_ops_pci, > Yes but here we are using a different variable than `default_pci_ops_dev` i.e. […] Thank you for the explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/71275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2 Gerrit-Change-Number: 71275 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 17:05:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/amdfwtool: Add option to indicate uncompressed BIOS binary
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Bao Zheng, Raul Rangel, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71210 ) Change subject: util/amdfwtool: Add option to indicate uncompressed BIOS binary ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Gerrit-Change-Number: 71210 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 Jan 2023 17:03:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Pass option about compression status of BIOS
by Paul Menzel (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71211 ) Change subject: soc/amd/mendocino: Pass option about compression status of BIOS ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71211/comment/d17e7b56_34277b47 PS2, Line 9: When CBFS verification is enabled and verified boot starts in bootblock, : PSP BIOS binary is uncompressed. Sorry, “is uncompressed” is ambiguous to me. Is it getting uncompressed or already in uncompressed form? -- To view, visit https://review.coreboot.org/c/coreboot/+/71211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2e935c7e137a305f6ed4bede91d3d0ba4ca6c7 Gerrit-Change-Number: 71211 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 02 Jan 2023 17:02:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelp2m/patform/sunrise: Add unit tests
by Christian Walter (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Martin L Roth, Maxim Polyakov, David Hendricks. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67132 ) Change subject: intelp2m/patform/sunrise: Add unit tests ...................................................................... Patch Set 14: Code-Review+1 (1 comment) Patchset: PS14: I'm in favor of Ron's nits ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/67132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15c7483f120a330849d4bad036427be205b0911c Gerrit-Change-Number: 67132 Gerrit-PatchSet: 14 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 16:09:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Create markarth variant
by Chao Gui (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Jason Nien, Paul Menzel, Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71610 ) Change subject: mb/google/skyrim: Create markarth variant ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71610/comment/5a23aaec_dc21a4e1 PS1, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). > Please move the dot/period before the ). […] Thanks for noting, will update the script. -- To view, visit https://review.coreboot.org/c/coreboot/+/71610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82 Gerrit-Change-Number: 71610 Gerrit-PatchSet: 2 Gerrit-Owner: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 15:39:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2023