coreboot-gerrit January 2023

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... Patch Set 23: (1 comment) File src/mainboard/intel/mtlrvp/romstage.c: https://review.coreboot.org/c/coreboot/+/66190/comment/dd0ac676_af2f73d3 PS22, Line 45: > This is seen only during the review of the file. […] @Paul, do you still see issue here? -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 23 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 03 Jan 2023 03:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] soc/amd: Change CPU ASL for p-states
by Kyösti Mälkki (Code Review) 03 Jan '23

03 Jan '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71614 ) Change subject: [WIP] soc/amd: Change CPU ASL for p-states ...................................................................... [WIP] soc/amd: Change CPU ASL for p-states CB:20910 and CB:19723 identify these as copy-pasted work. I tracked this back to CB:53 and CB:54 where a literal constant 0x810 matched with a block of 6 bytes at offset 0x10 from (SB900_)ACPI_IO_BASE named ACPI_CPU_CONTROL. Change-Id: I886a40ea9d58da102fe21f5f0018ac22b562e1f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/acpi.c M src/soc/amd/morgana/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c 8 files changed, 24 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/71614/1 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 802476e..aeed8ca 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -297,7 +297,7 @@ if (cpu == 0) { /* BSP values for \_SB.Pxxx */ proc_blk_len = 6; - proc_blk_addr = ACPI_GPE0_BLK; + proc_blk_addr = ACPI_CPU_CONTROL; } else { /* AP values for \_SB.Pxxx */ proc_blk_addr = 0; diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 3dd8418..2d2d806 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -14,6 +14,7 @@ #define MMIO_ACPI_PM1_CNT_BLK 0x04 /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) + #define MMIO_ACPI_PM_TMR_BLK 0x08 #define MMIO_ACPI_CPU_CONTROL 0x0c #define MMIO_ACPI_GPE0_BLK 0x14 diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 0c95494..3eb4cde 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -300,7 +300,7 @@ if (cpu == 0) { /* BSP values for \_SB.Pxxx */ proc_blk_len = 6; - proc_blk_addr = ACPI_GPE0_BLK; + proc_blk_addr = ACPI_CPU_CONTROL; } else { /* AP values for \_SB.Pxxx */ proc_blk_addr = 0; diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index bb8588c..b4a3d05 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -49,6 +49,7 @@ #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) + #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) #define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index d30fb85..7863641 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -299,7 +299,7 @@ if (cpu == 0) { /* BSP values for \_SB.Pxxx */ proc_blk_len = 6; - proc_blk_addr = ACPI_GPE0_BLK; + proc_blk_addr = ACPI_CPU_CONTROL; } else { /* AP values for \_SB.Pxxx */ proc_blk_addr = 0; diff --git a/src/soc/amd/morgana/acpi.c b/src/soc/amd/morgana/acpi.c index 15b64c5..ab37cbb 100644 --- a/src/soc/amd/morgana/acpi.c +++ b/src/soc/amd/morgana/acpi.c @@ -300,7 +300,7 @@ if (cpu == 0) { /* BSP values for \_SB.Pxxx */ proc_blk_len = 6; - proc_blk_addr = ACPI_GPE0_BLK; + proc_blk_addr = ACPI_CPU_CONTROL; } else { /* AP values for \_SB.Pxxx */ proc_blk_addr = 0; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 6d46698..db359cb 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -292,7 +292,7 @@ if (cpu == 0) { /* BSP values for \_SB.Pxxx */ proc_blk_len = 6; - proc_blk_addr = ACPI_GPE0_BLK; + proc_blk_addr = ACPI_CPU_CONTROL; } else { /* AP values for \_SB.Pxxx */ proc_blk_addr = 0; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index cc0194b..0586950 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -108,7 +108,7 @@ printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); /* Generate BSP \_SB.P000 */ - acpigen_write_processor(0, ACPI_GPE0_BLK, 6); + acpigen_write_processor(0, ACPI_CPU_CONTROL, 6); acpigen_pop_len(); /* Generate AP \_SB.Pxxx */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I886a40ea9d58da102fe21f5f0018ac22b562e1f5 Gerrit-Change-Number: 71614 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Ren Kuo (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Martin L Roth, Reka Norman, Eric Lai. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71170 ) Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71170/comment/327ce636_33642f51 PS7, Line 9: EVT build. > Please don't mention project phases in public commits. fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 8 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 02:26:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify GPIOs for NVMe
by Ren Kuo (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: David Wu, Tarun Tuli, Ren Kuo, Reka Norman, Eric Lai. Hello build bot (Jenkins), David Wu, Tarun Tuli, Martin L Roth, Kangheui Won, Reka Norman, Tyler Wang, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71170 to look at the new patch set (#8). Change subject: mb/google/nissa/var/craask: Modify GPIOs for NVMe ...................................................................... mb/google/nissa/var/craask: Modify GPIOs for NVMe Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up frome NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 22 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/71170/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/71170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Gerrit-Change-Number: 71170 Gerrit-PatchSet: 8 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya: Create omnigul variant
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71626 ) Change subject: mb/google/brya: Create omnigul variant ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167512): https://review.coreboot.org/c/coreboot/+/71626/comment/90d2c4d5_39b18875 PS1, Line 9: # See util/spd_tools/README.md for more details and instructions. 'README' may be misspelled - perhaps 'README'? -- To view, visit https://review.coreboot.org/c/coreboot/+/71626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf6a5cc2dd187374b9347ab9dae71f37481eef4 Gerrit-Change-Number: 71626 Gerrit-PatchSet: 1 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 01:48:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya: Create omnigul variant
by AlanKY Lee (Code Review) 03 Jan '23

03 Jan '23

AlanKY Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71626 ) Change subject: mb/google/brya: Create omnigul variant ...................................................................... mb/google/brya: Create omnigul variant Create the omnigul variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:181325655 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OMNIGUL Change-Id: Iccf6a5cc2dd187374b9347ab9dae71f37481eef4 Signed-off-by: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/omnigul/include/variant/ec.h A src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h A src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc A src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/omnigul/overridetree.cb 8 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/71626/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1fb78c0..7865ad9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -222,6 +222,7 @@ default "Zydron" if BOARD_GOOGLE_ZYDRON default "Gladios" if BOARD_GOOGLE_GLADIOS default "Marasov" if BOARD_GOOGLE_MARASOV + default "Omnigul" if BOARD_GOOGLE_OMNIGUL config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -263,6 +264,7 @@ default "zydron" if BOARD_GOOGLE_ZYDRON default "gladios" if BOARD_GOOGLE_GLADIOS default "marasov" if BOARD_GOOGLE_MARASOV + default "omnigul" if BOARD_GOOGLE_OMNIGUL config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8e38735..06159cf 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -316,3 +316,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select SOC_INTEL_RAPTORLAKE select DRIVERS_INTEL_ISH + +config BOARD_GOOGLE_OMNIGUL + bool "-> Omnigul" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h b/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h b/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/71626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf6a5cc2dd187374b9347ab9dae71f37481eef4 Gerrit-Change-Number: 71626 Gerrit-PatchSet: 1 Gerrit-Owner: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: sb,soc/intel/common: Add common get_pmbase()
by Kyösti Mälkki (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Tim Chu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70048 ) Change subject: sb,soc/intel/common: Add common get_pmbase() ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/braswell/pmutil.c: https://review.coreboot.org/c/coreboot/+/70048/comment/c00e45eb_d6da7cc2 PS4, Line 14: include <security/vboot/vbnv.h> > Once you start sorting the includes in this patch you could move console/console.h, too. Done File src/soc/intel/broadwell/pch/pmutil.c: https://review.coreboot.org/c/coreboot/+/70048/comment/fe301906_397e7b66 PS4, Line 15: #include <console/console.h> > Move this line in the right order as well? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/70048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Gerrit-Change-Number: 70048 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 01:10:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: sb,soc/intel/common: Add common get_pmbase()
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70048 ) Change subject: sb,soc/intel/common: Add common get_pmbase() ...................................................................... Patch Set 7: (1 comment) File src/southbridge/intel/common/pmbase.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167509): https://review.coreboot.org/c/coreboot/+/70048/comment/02f24f31_466f4536 PS7, Line 17: !CONFIG(SOC_INTEL_BRASWELL) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/70048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Gerrit-Change-Number: 70048 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 00:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70049 ) Change subject: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX() ...................................................................... Patch Set 5: (1 comment) File src/southbridge/intel/common/pmbase.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167511): https://review.coreboot.org/c/coreboot/+/70049/comment/0e7a0ec7_4614e9b1 PS5, Line 11: CONFIG(SOC_INTEL_BROADWELL) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/70049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2 Gerrit-Change-Number: 70049 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 00:52:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()
by Kyösti Mälkki (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70049 to look at the new patch set (#5). Change subject: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX() ...................................................................... [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX() Renames {read,write}_pmbaseX to pm_{read,write}X. Inlining allows for static, compile-time assertions and possibility to easily add register tracing for debugging. Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h 2 files changed, 120 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/70049/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2 Gerrit-Change-Number: 70049 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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