coreboot-gerrit January 2023

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[S] Change in coreboot[master]: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW
by Eric Lai (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71631 ) Change subject: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Who will set it high if there is no driver to control it? IIUC, there is no audio drier will control GPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/71631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Gerrit-Change-Number: 71631 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/mainboard/brya/: Clear EC AP_IDLE flag after shutdown
by Eric Lai (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Derek Huang, Caveh Jalali, Nick Vaccaro, Daisuke Nojiri, Boris Mittelberg. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70773 ) Change subject: src/mainboard/brya/: Clear EC AP_IDLE flag after shutdown ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/brya/mainboard.c: https://review.coreboot.org/c/coreboot/+/70773/comment/b7d25b98_0acdd41e PS11, Line 219: if (CONFIG(CR50_RESET_CLEAR_EC_AP_IDLE_FLAG)) { > It is required for all Chromebox/base if POWER_OFF_ON_CR50_UPDATE is enabled, so I prefer to add it […] it's fine. if there is no particular order. -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 11 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82371eb: Implement SMBus Control Method Interface support
by Keith Hui (Code Review) 03 Jan '23

03 Jan '23

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41735 ) Change subject: sb/intel/i82371eb: Implement SMBus Control Method Interface support ...................................................................... sb/intel/i82371eb: Implement SMBus Control Method Interface support Upcoming ACPI support for asus/p3b-f mainboard contains ASL code to manipulate its AS99127F chip over SMBus before and after suspend, to blink front panel lights, turn off fans, among other things. This code caused an ACPI/PCI resource conflict that disabled access to the entire SMBus, rendering its hardware monitor inoperative, and all resolution attempts so far have not worked. This is an attempt to expand the ASL SMBus routines into a complete SMBus Control Method Interface (SCMI), that Linux kernel can use via the i2c-scmi driver, sidestepping this conflict. Because SCMI methods begin with an underscore, which iasl considers "unknown reserved name", on which our build process errors out, it must also be told to ignore this particular warning, at least for asus/p3b-f. Change-Id: I97deb2d292af25e42068474f48e11c94a7480be6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Makefile.inc M src/southbridge/intel/i82371eb/acpi/i82371eb.asl 2 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41735/1 diff --git a/Makefile.inc b/Makefile.inc index 210e9cf..d1aebd3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -253,11 +253,17 @@ # "Multiple types (Device object requires either a _HID or _ADR, but not both)" MULTIPLE_TYPES_WARNING = 3073 +UNKNOWN_RESERVED_NAME = 3133 + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) else +ifeq ($(CONFIG_BOARD_ASUS_P3B_F),y) +IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(UNKNOWN_RESERVED_NAME) +else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) endif +endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl index b64036e..27c2a3c 100644 --- a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -2,6 +2,8 @@ #include "southbridge/intel/i82371eb/i82371eb.h" +#define SCMI_MUTEX SBX0 + /* Declares assorted devices that falls under this southbridge. */ Device (PX40) { @@ -135,4 +137,179 @@ }) Return (BUF1) } +/* Begin SCMI implementation */ + Mutex(SCMI_MUTEX, 1) + + Device (SMB0) + { + OperationRegion (SM00, SystemIO, SMBUS_IO_BASE, 7) + /* Should have been SMBUS01, but Intel iasl won't accept */ + Name (_HID, "SMB0001") + + Field (SM00, ByteAcc, NoLock, Preserve) + { + HSTS, 8, + Offset (0x02), + CTLR, 8, + CMDR, 8, + ADDR, 8, + DAT0, 8, + DAT1, 8 + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + /* SMBus register ports */ + IO (Decode16, SMBUS_IO_BASE, SMBUS_IO_BASE, 0x01, 0x10, ) + }) + Return (BUF1) + } + /** + * SCMI: SMBus Information + * + * @return SMBus information buffer + */ + Method (_SBI, 0) + { + Local0 = Package(2) {0x10, Buffer() + { + 0x10, 0x10, /* SCMI and SMBus versions, both 1.0 */ + 0, 0, + 3, /* Device count */ + 0x2d, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x48, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x49, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 + } + }; + return (Local0) + } + /** + * Read from a SMBus device. + * + * @param Arg0 Protocol + * @param Arg1 Slave address + * @param Arg2 Command (register index in our case) + * @return Package (status code, data length, data) + */ + Method (_SBR, 3) { + Local2 = Package(3) {0, 0, 0} + if (Arg0 == 0x07) + { + Local0 = 0x48 /* Start a byte data R/W access */ + Local3 = 1; /* 1 byte */ + } + elseif (Arg0 == 0x09) + { + Local0 = 0x4c /* Start a word data R/W access */ + } + else + { + Index(Local2, 0) = 0x19 // Protocol not supported + return (Local2) + } + if (HSTS & 0x01) + { + Index(Local2, 0) = 0x1a // Bus busy + return (Local2) + } + if (Acquire(SCMI_MUTEX, 100)) + { + Index(Local2, 0) = 0x18 // Timeout + } else { + ADDR = (Arg1 << 1) | 0x01 /* Set bit 0, this is a read */ + CMDR = Arg2 + HSTS = 0xFF + CTLR = Local0 + + while (HSTS & 0x01) + { + Stall(1) + } + if (HSTS & 0x06) + { + Index(Local2, 0) = 0x11 /* Device error */ + } + else + { + Local1 = DAT0 + /* Get high byte of word read */ + if (Arg0 == 0x09) + { + Local1 |= (DAT1 << 8) + Local3 = 2 /* 2 bytes */ + } + Index(Local2, 1) = Local3 + Index(Local2, 2) = Local1 + } + Release(SCMI_MUTEX); + } + return (Local2); + } + /** + * Write to a SMBus device. + * + * @param Arg0 Protocol + * @param Arg1 Slave address + * @param Arg2 Command (register index in our case) + * @param Arg3 Data length + * @param Arg4 Data + * @return Status code + */ + Method (_SBW, 5) { + if (Arg0 == 0x06) + { + Local0 = 0x48 /* Start a byte data R/W access */ + } + elseif (Arg0 == 0x08) + { + Local0 = 0x4c /* Start a word data R/W access */ + } + else + { + Return (0x19) //* Protocol not supported */ + } + if (HSTS & 0x01) + { + Return (0x1a) /* Bus busy */ + } + if (Acquire(SCMI_MUTEX, 100)) + { + Local1 = 0x18 /* Timeout */ + } + else + { + Local1 = 0 + ADDR = Arg1 << 1 + CMDR = Arg2 + DAT0 = Arg4 + if (Arg0 == 0x08) { + DAT1 = Arg4 >> 8 + } + HSTS = 0xFF + CTLR = Local0 + while (HSTS & 0x01) + { + Stall(1) + } + if (HSTS & 0x06) + { + Local1 = 0x11 /* Device error */ + } + Release(SCMI_MUTEX) + } + return (Local1); + } + /* _SBT, _SBA not implemented */ + } +/* End SCMI implementation */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/41735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97deb2d292af25e42068474f48e11c94a7480be6 Gerrit-Change-Number: 41735 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Angel Pons (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61540 ) Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c: https://review.coreboot.org/c/coreboot/+/61540/comment/38ef897c_f4ecdaa3 PS2, Line 5: #include <northbridge/intel/sandybridge/sandybridge.h> > > > I need it for the prototype of mainboard_should_reset_usb(), a MRC raminit hook that native rami […] Sounds good, thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:47:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/asus/p8x7x-series: Refactor mainboard_get_spd()
by Angel Pons (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Arthur Heymans, Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61540 ) Change subject: mb/asus/p8x7x-series: Refactor mainboard_get_spd() ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/mainboard/asus/p8x7x-series/early_init.c: https://review.coreboot.org/c/coreboot/+/61540/comment/282879cb_a249da9e PS3, Line 5: void __weak nit: We usually put `__weak` at the start -- To view, visit https://review.coreboot.org/c/coreboot/+/61540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b9c616a6c722e1f0fc124ced225efdcadb46b25 Gerrit-Change-Number: 61540 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add Asus P8Z77-M
by Angel Pons (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61539 ) Change subject: Documentation: Add Asus P8Z77-M ...................................................................... Patch Set 3: Code-Review+1 (4 comments) File Documentation/mainboard/asus/p8z77-m.md: https://review.coreboot.org/c/coreboot/+/61539/comment/9f02b9a1_e2099d11 PS3, Line 35: use kernel parameter ``iomem=relaxed`` Unloading the `lpc_ich` kernel module should also work, and it's much more convenient. `iomem=relaxed` needs a reboot and can make the system less secure. https://review.coreboot.org/c/coreboot/+/61539/comment/a5d3245b_c569c4f8 PS3, Line 64: trailing whitespace While at it, also add "and VBT" because Windows drivers require the VBT. https://review.coreboot.org/c/coreboot/+/61539/comment/6a4bf903_43806d45 PS3, Line 74: - PCI POST card is not functional because the PCI bridge early init is not yet done. coreboot also needs to be configured to send POST cycles to PCI (default is LPC) https://review.coreboot.org/c/coreboot/+/61539/comment/5aa9022a_3c2627aa PS3, Line 95: - OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600. : : - GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but highly unstable : with obvious pattern of bit errors during memtest86+ runs. Does this still happen? Is it with native raminit or MRC? For the GSkill modules, it would be wise to try loosening the timings a bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/61539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f990408c4552b69c04e849e7faaf9f51f24a51 Gerrit-Change-Number: 61539 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:46:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim/var/markarth: Generate RAM IDs for new memory parts
by John Su (Code Review) 03 Jan '23

03 Jan '23

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71632 ) Change subject: mb/google/skyrim/var/markarth: Generate RAM IDs for new memory parts ...................................................................... mb/google/skyrim/var/markarth: Generate RAM IDs for new memory parts Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) BUG=b:263296326, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82 --- A src/mainboard/google/skyrim/variants/markarth/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt A src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/71632/1 diff --git a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc new file mode 100644 index 0000000..88e75bd --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./memory diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc new file mode 100644 index 0000000..258a35b --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/markarth/memory src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-1/spd-8.hex # ID = 1(0b0001) Parts = K3KL9L90CM-MGCT, H58G66BK7BX067, MT62F2G32D4DS-026 WT:B diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt new file mode 100644 index 0000000..c2ca506 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MDN lp5 src/mainboard/google/skyrim/variants/markarth/memory src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +K3KL8L80CM-MGCT 0 (0000) +H58G56BK7BX068 0 (0000) +K3KL9L90CM-MGCT 1 (0001) +H58G66BK7BX067 1 (0001) +MT62F2G32D4DS-026 WT:B 1 (0001) diff --git a/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt new file mode 100644 index 0000000..cded20f --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt @@ -0,0 +1,5 @@ +K3KL8L80CM-MGCT, +H58G56BK7BX068, +K3KL9L90CM-MGCT, +H58G66BK7BX067, +MT62F2G32D4DS-026 WT:B, -- To view, visit https://review.coreboot.org/c/coreboot/+/71632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82 Gerrit-Change-Number: 71632 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: Documentation: Add Asus P2B-LS
by Angel Pons (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61537 ) Change subject: Documentation: Add Asus P2B-LS ...................................................................... Patch Set 2: Code-Review+1 (7 comments) File Documentation/mainboard/asus/p2b-ls.md: https://review.coreboot.org/c/coreboot/+/61537/comment/8a512988_31202091 PS2, Line 9: ethernet The model names probably refer to this as "LAN". No need to change anything. https://review.coreboot.org/c/coreboot/+/61537/comment/2bf95563_0cd7e6ee PS2, Line 19: SST 39SF020A (or similar) It would be good to specify the flash protocol https://review.coreboot.org/c/coreboot/+/61537/comment/74fdfdee_d9145eae PS2, Line 42: This board by default Nit: > By default, this board ... https://review.coreboot.org/c/coreboot/+/61537/comment/2ff1edb6_504b30bc PS2, Line 45: If you start to run out of flash space, you may have : to build a custom microcode update file by manually concatenating files in : 3rdparty/intel-microcode/intel-ucode for CPU models that you actually have : on hand. You could add Kconfig options to control which microcode updates are added. The default should be to add all of them, for build-testing purposes. This would be handled in a separate change. https://review.coreboot.org/c/coreboot/+/61537/comment/e09d17a6_eea0006d PS2, Line 69: nit: trailing whitespace https://review.coreboot.org/c/coreboot/+/61537/comment/962465d9_ad60f546 PS2, Line 91: S3 suspend to RAM Out of curiosity, got any details on what goes wrong? https://review.coreboot.org/c/coreboot/+/61537/comment/e97a4296_0e5f207b PS2, Line 101: model_6xx Would be nice to indicate the actual models and CPU socket (slot 1?) -- To view, visit https://review.coreboot.org/c/coreboot/+/61537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib885c4dd8472ed2b0a61c548f6ef652979a33153 Gerrit-Change-Number: 61537 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:39:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW
by Subrata Banik (Code Review) 03 Jan '23

03 Jan '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71631 ) Change subject: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW ...................................................................... mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 --- M src/mainboard/google/rex/variants/rex0/gpio.c 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/71631/1 diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 7e04869..01fa95d 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -317,8 +317,8 @@ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* GPP_H14 : [] ==> SLP_S0_GATE_R */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), - /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, NONE), + /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ + PAD_CFG_GPO(GPP_H15, 0, PLTRST), /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Gerrit-Change-Number: 71631 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: src/mainboard/brya/: Clear EC AP_IDLE flag after shutdown
by Derek Huang (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Caveh Jalali, Nick Vaccaro, Daisuke Nojiri, Eric Lai, Boris Mittelberg. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70773 ) Change subject: src/mainboard/brya/: Clear EC AP_IDLE flag after shutdown ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/brya/mainboard.c: https://review.coreboot.org/c/coreboot/+/70773/comment/d692ecc5_e236bf36 PS11, Line 219: if (CONFIG(CR50_RESET_CLEAR_EC_AP_IDLE_FLAG)) { > I think you can add in here https://source.chromium. […] It is required for all Chromebox/base if POWER_OFF_ON_CR50_UPDATE is enabled, so I prefer to add it in https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 11 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 06:36:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit January 2023