Attention is currently required from: Jamie Ryu.
Hello Jamie Ryu,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/71638
to review the following change.
Change subject: mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
......................................................................
mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVP
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required
to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig
option, CSE reboots the system into CSE_RW FW region on cold reboot.
BUG=b:224325352
TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe
CSE boot to RW FW region as part of coreboot console log,
localhost ~ # cbmem -c | grep cse
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
Signed-off-by: Harsha B R <harsha.b.r(a)intel.com>
Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/71638/1
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 349e9de..9d8982d 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -4,6 +4,7 @@
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE
config BOARD_INTEL_MTLRVP_P
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Attention is currently required from: Tarun Tuli.
Hello Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71634
to look at the new patch set (#3).
Change subject: mb/google/brya/var/marasov: Update DPTF parameters
......................................................................
mb/google/brya/var/marasov: Update DPTF parameters
Add the first version DPTF parameters.
BUG=b:264217345
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com>
Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5
---
M src/mainboard/google/brya/variants/marasov/overridetree.cb
1 file changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/71634/3
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
Patch Set 15: Code-Review+1
(3 comments)
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/1d9d18a3_1fc758ef
PS12, Line 171: poweroff();
> original is this: […]
fix now.
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/fe81b85f_d673256c
PS15, Line 79: printk(BIOS_INFO,
nit:no need warp line. we can have 96 char inline
https://review.coreboot.org/c/coreboot/+/70773/comment/9f3329f3_f3beac16
PS15, Line 82: printk(BIOS_ERR,
nit:no need warp line. we can have 96 char inline
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Hello Tarun Tuli, Subrata Banik, Caveh Jalali, Christian Walter, Nick Vaccaro, Daisuke Nojiri, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/70773
to look at the new patch set (#15).
Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang(a)google.com>
---
M src/ec/google/chromeec/ec_commands.h
M src/mainboard/google/brya/Kconfig
M src/security/tpm/tss/vendor/cr50/Kconfig
M src/vendorcode/google/chromeos/cr50_enable_update.c
4 files changed, 56 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/70773/15
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
Patch Set 14:
(1 comment)
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/10d4591d_0c436b12
PS12, Line 171: poweroff();
> > the powerofff should stay in if (CONFIG(POWER_OFF_ON_CR50_UPDATE))? […]
original is this:
if (CONFIG(POWER_OFF_ON_CR50_UPDATE))
poweroff();
now, poweroff is out of guard.
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
Patch Set 14:
(1 comment)
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/7959c2ea_2ff66423
PS12, Line 171: poweroff();
> the powerofff should stay in if (CONFIG(POWER_OFF_ON_CR50_UPDATE))?
IMO, the seq has to be performed before `poweroff()`
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
Patch Set 14:
(1 comment)
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/c7c94e5a_47e9977b
PS12, Line 171: poweroff();
the powerofff should stay in if (CONFIG(POWER_OFF_ON_CR50_UPDATE))?
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71229 )
Change subject: soc/intel/elkhartlake: Make SATA speed limit configurable
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/elkhartlake/chip.h:
https://review.coreboot.org/c/coreboot/+/71229/comment/99f3378c_8b350cd6
PS2, Line 108: SATA_DEFAULT = 0,
: SATA_GEN1,
: SATA_GEN2
Should you also list 'SATA_GEN3' for the completeness?
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