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Change subject: soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent directories
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent directories
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Change subject: soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent directory
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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/64561/comment/a920fa0d_f33bf16e
PS7, Line 164: #if CONFIG(CHROMEOS)
> Like PS8?
I like this CL. thanks for taking care of it
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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
Patchset:
PS8:
what about MTL ? https://github.com/coreboot/coreboot/blob/master/src/soc/intel/meteorlake/a…
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Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/64561/comment/c81ad413_231ba43b
PS7, Line 164: #if CONFIG(CHROMEOS)
> > Talking to MattD, it sounds like we don't want to use CONFIG(CHROMEOS) as the way to choose it. […]
Like PS8?
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, John Zhao, Tim Wawrzynczak, Angel Pons, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64561
to look at the new patch set (#8).
Change subject: soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
......................................................................
soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM
Software Connection Manager doesn't work with Linux 5.13 or later,
resulting in TBT ports timing out. Not advertising this results
in Firmware Connection Manager being used and TBT works
correctly.
Add Kconfig options to chose between SCM (Software Connection
Manager) and FCM (Firmware Connection Manager). FCM is primary, as
it's more compatible save for ChromeOS devices as ChromeOS uses
SCM.
Linux patch:
torvalds/linux@c6da62a
c6da62a219d028de10f2e22e93a34c7ee2b88d03
Tested with StarBook Mk VI (i7-1260P).
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8
---
M src/device/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/acpi/tcss.asl
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/acpi/tcss.asl
5 files changed, 64 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/64561/8
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Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71641 )
Change subject: mb/google/brya/var/skolas: Set tcc_offset value to 3
......................................................................
mb/google/brya/var/skolas: Set tcc_offset value to 3
Thermal team has determined that the TCC circuit trip temperature
should be set to 97C, because the offset is subtracted from 100C,
set the `tcc_offset` register in the devicetree to 3.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
Change-Id: Ic9b2b171390de16e4a8e73b4271e2531244ad169
---
M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
1 file changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/71641/1
diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
index 6ca0c9e..139fd71 100644
--- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb
@@ -17,7 +17,7 @@
# DPTF enable
register "dptf_enable" = "1"
- register "tcc_offset" = "10" # TCC of 90
+ register "tcc_offset" = "3" # TCC of 97
# Enable CNVi BT
register "cnvi_bt_core" = "true"
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70853 )
Change subject: Documentation/getting_started: Add information about ost2
......................................................................
Patch Set 2:
(3 comments)
File Documentation/getting_started/OST2.md:
https://review.coreboot.org/c/coreboot/+/70853/comment/3090688c_35e484be
PS2, Line 7: There are various ways to learn firmware, some are more efficient than others,
Please add a blank line above, or do not wrap the line.
https://review.coreboot.org/c/coreboot/+/70853/comment/72a06f3c_2cfd4322
PS2, Line 13: cc BY-SA
Which version? https://creativecommons.org/licenses/by-sa/1.0/
CC BY-SA
https://review.coreboot.org/c/coreboot/+/70853/comment/fe67ac40_2214c6e0
PS2, Line 27: more courses
Make *more courses* the link. (Maybe add *available*.)
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