coreboot-gerrit January 2023

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[S] Change in coreboot[master]: soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existen...
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71587 ) Change subject: soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent directories ...................................................................... soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/picasso/psp_verstage/Makefile.inc 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 82d8efa..bf1a694 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/soc/amd/picasso/psp_verstage/include verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-y += svc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/71587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Gerrit-Change-Number: 71587 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-exist...
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71586 ) Change subject: soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent directory ...................................................................... soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/mendocino/psp_verstage/Makefile.inc 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.inc b/src/soc/amd/mendocino/psp_verstage/Makefile.inc index b185ffd..19dd8a7 100644 --- a/src/soc/amd/mendocino/psp_verstage/Makefile.inc +++ b/src/soc/amd/mendocino/psp_verstage/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/soc/amd/mendocino/psp_verstage/include verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -- To view, visit https://review.coreboot.org/c/coreboot/+/71586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Gerrit-Change-Number: 71586 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Looks good, just waiting on the commit message update. -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:03:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add API to check Key Locker support
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Subrata Banik, Paul Menzel, Pratikkumar V Prajapati. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71117 ) Change subject: soc/intel/common: Add API to check Key Locker support ...................................................................... Patch Set 7: (3 comments) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/71117/comment/515e2ff6_469c0e55 PS7, Line 39: #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 Use this macro? https://review.coreboot.org/c/coreboot/+/71117/comment/d0739c3a_bc5d3f88 PS7, Line 200: cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0); similar to here. https://review.coreboot.org/c/coreboot/+/71117/comment/622e4808_62530c6f PS7, Line 542: 0x7 Could you update this to use the CPUID_STRUCT_EXTENDED_FEATURE_FLAGS definition? Maybe do this in a follow-on patch, since the same code is used in several places above. Maybe create an inline function to get the feature flags and use it across all of the functions? -- To view, visit https://review.coreboot.org/c/coreboot/+/71117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Gerrit-Change-Number: 71117 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 17:58:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization
by Fred Reitberger (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71562/comment/ce4a86ca_c074b150 PS2, Line 14: BRACHN=none nit: BRANCH -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 17:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/baytrail: add _HRV to GPIO ACPI devices
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71200 ) Change subject: soc/intel/baytrail: add _HRV to GPIO ACPI devices ...................................................................... soc/intel/baytrail: add _HRV to GPIO ACPI devices For some reason, the Windows LPEA drivers won't attach without _HRV (hardware version) defined for the GPIO controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load properly. Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/acpi/gpio.asl 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index e6dc536..d97b85c 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -26,6 +26,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { Return (0xF) @@ -55,6 +57,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { Return (0xF) @@ -84,6 +88,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { Return (0xF) -- To view, visit https://review.coreboot.org/c/coreboot/+/71200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Gerrit-Change-Number: 71200 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/baytrail: add _HRV to I2C ACPI devices
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71199 ) Change subject: soc/intel/baytrail: add _HRV to I2C ACPI devices ...................................................................... soc/intel/baytrail: add _HRV to I2C ACPI devices For some reason, the Windows i2c drivers won't attach without _HRV (hardware version) defined for the i2c controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load properly. Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/acpi/lpss.asl 1 file changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index 113d5c0..b8e2d96 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -94,6 +94,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S1EN == 1) { @@ -153,6 +155,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S2EN == 1) { @@ -205,6 +209,8 @@ FixedDMA (0x15, 0x5, Width32Bit, ) }) + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) @@ -271,6 +277,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S4EN == 1) { @@ -330,6 +338,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S5EN == 1) { @@ -389,6 +399,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S6EN == 1) { @@ -448,6 +460,8 @@ Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (\S7EN == 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/71199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d Gerrit-Change-Number: 71199 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/samus: Set hidden flag for RT5677AA ACPI device
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71198 ) Change subject: mb/google/samus: Set hidden flag for RT5677AA ACPI device ...................................................................... mb/google/samus: Set hidden flag for RT5677AA ACPI device Coolstar's Windows drivers don't utilize it, and the Linux drivers don't care about _STA, so hide it from Windows to tidy up Device Manager. Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl index 9ca592f..6fc650d 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -230,5 +230,10 @@ ResourceConsumer, // ResourceUsage ) }) + + Method (_STA) + { + Return (0xB) //hidden from Windows + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/71198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb Gerrit-Change-Number: 71198 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/slippy/peppy: Set cypress TP IRQ to Level vs Edge
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71197 ) Change subject: mb/google/slippy/peppy: Set cypress TP IRQ to Level vs Edge ...................................................................... mb/google/slippy/peppy: Set cypress TP IRQ to Level vs Edge Change the IRQ triggering from edge to level for cypress touchpad on peppy variant for compatibility with Windows drivers. TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad functional. Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index e149901..a96ec19 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -60,7 +60,7 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow, Shared) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } -- To view, visit https://review.coreboot.org/c/coreboot/+/71197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed Gerrit-Change-Number: 71197 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/cezanne: Set up SoC-specific XHCI definitions
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67939 ) Change subject: soc/amd/cezanne: Set up SoC-specific XHCI definitions ...................................................................... Patch Set 14: Verified-1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167555): https://review.coreboot.org/c/coreboot/+/67939/comment/63d1c555_0e2a58c8 PS14, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/67939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Gerrit-Change-Number: 67939 Gerrit-PatchSet: 14 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 17:28:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2023