coreboot-gerrit January 2023

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[S] Change in coreboot[master]: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Paul Menzel, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71562/comment/fbba4d2c_4172fbde PS2, Line 10: It will impact the PCIe signal integrity, need to double-confirm > Please add a blank line between paragraphs or do not wrap lines too early. Please add this rule to the style guide if you want it to be followed. Otherwise, let's not worry about minor infringements. Sure if it were a serious problem like having one word per line, that's reasonable, but this seems fine to me. File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/71562/comment/0700fdb2_1e764c44 PS2, Line 167: w/a > Why workaround? Because it's a workaround of an issue we were seeing. It's not a fix. https://review.coreboot.org/c/coreboot/+/71562/comment/ecd06010_100f99e4 PS2, Line 168: dxio_tx_vboost_enable > Does *enable* need to be in the name? If yes, it’d put it in the front: `enable_dxio_tx_vboost`. This is pretty pedantic. Let's not worry about it. -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:24:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Enable RTD3 for Winterhold NVMe to eMMC bridge
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/71559 ) Change subject: mb/google/skyrim: Enable RTD3 for Winterhold NVMe to eMMC bridge ...................................................................... Abandoned Abandoned in favor of cb:71277 -- To view, visit https://review.coreboot.org/c/coreboot/+/71559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a0a03aa7899566a9b6c642965b0a709704873eb Gerrit-Change-Number: 71559 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization
by Paul Menzel (Code Review) 03 Jan '23

03 Jan '23

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[S] Change in coreboot[master]: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization
by Paul Menzel (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization ...................................................................... Patch Set 2: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71562/comment/6988b2f6_ab5bf0e2 PS2, Line 7: soc/amd/mendocino: add dxio_tx_vboost_enable for pcie optimization Reading this, I thought it’s getting enabled. Maybe: > Hook up UPD dxio_tx_vboost_enable for PCIe optimization https://review.coreboot.org/c/coreboot/+/71562/comment/3a10ad62_6ab0e4df PS2, Line 10: It will impact the PCIe signal integrity, need to double-confirm Please add a blank line between paragraphs or do not wrap lines too early. https://review.coreboot.org/c/coreboot/+/71562/comment/9f158282_f353517a PS2, Line 10: need to double-confirm : the SI result after enabling this setting Can this be done before submitting this? File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/71562/comment/c34c28f2_89773e1b PS2, Line 167: w/a Why workaround? https://review.coreboot.org/c/coreboot/+/71562/comment/56d7ec72_7bc09a08 PS2, Line 167: need to check PCIe signal integrity before enabling. 1. Please start sentences with capital letter. 2. Maybe rephrase: > You should check the PCIe signal integrity before enabling this. 3. How can the integrity be checked? 4. If possible, please describe in more detail, what this option does. https://review.coreboot.org/c/coreboot/+/71562/comment/f73d89c3_7efaa466 PS2, Line 167: set Set https://review.coreboot.org/c/coreboot/+/71562/comment/26fcbc93_4ae575df PS2, Line 168: dxio_tx_vboost_enable Does *enable* need to be in the name? If yes, it’d put it in the front: `enable_dxio_tx_vboost`. -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe
by Martin Roth (Code Review) 03 Jan '23

03 Jan '23

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71277 ) Change subject: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe ...................................................................... mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe winterhold/whiterun has different H/W topology to skyrim that the eMMC device is on a different GPP: skyrim: GPP1 -> SD winterhold : GPP1 -> eMMC BUG=b:263763288 BRANCH=none TEST=s0i3 stress over 2500 cycles. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, but someone else must approve Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 9d226f1..1d50bd5 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -99,6 +99,21 @@ register "stt_skin_temp_apu_F" = "0x3200" device domain 0 on + device ref gpp_bridge_1 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # eMMC + device ref gpp_bridge_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/71277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Gerrit-Change-Number: 71277 Gerrit-PatchSet: 2 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe
by Martin Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Raul Rangel, Jason Nien, Chris Wang, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71277 ) Change subject: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/skyrim/variants/winterhold/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71277/comment/a73537a1_2fb2d956 PS1, Line 105: NVME > Should this be changed to EMMC? We can do that in a follow-on patch if desired. Since this was boot tested, I have no objections to leaving it the way it is for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/71277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Gerrit-Change-Number: 71277 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:15:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe
by Martin Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Raul Rangel, Jason Nien, Chris Wang, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71277 ) Change subject: mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/variants/winterhold/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71277/comment/ab6985cc_013db206 PS1, Line 105: NVME Should this be changed to EMMC? -- To view, visit https://review.coreboot.org/c/coreboot/+/71277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29 Gerrit-Change-Number: 71277 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71597 ) Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory ...................................................................... vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc 1 file changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 96c3ea9..2ac4987 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -32,7 +32,6 @@ BINARY_PI_INC = -I$(AGESA_ROOT) BINARY_PI_INC += -I$(AGESA_ROOT)/binaryPI BINARY_PI_INC += -I$(AGESA_ROOT)/Include -BINARY_PI_INC += -I$(AGESA_ROOT)/Lib BINARY_PI_INC += -I$(AGESA_ROOT)/Proc BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Common BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU -- To view, visit https://review.coreboot.org/c/coreboot/+/71597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Gerrit-Change-Number: 71597 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Elyes Haouas. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71597 ) Change subject: vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directory ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Gerrit-Change-Number: 71597 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 03 Jan 2023 18:09:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existen...
by Martin L Roth (Code Review) 03 Jan '23

03 Jan '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71588 ) Change subject: soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent directories ...................................................................... soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/psp_verstage/Makefile.inc 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.inc b/src/soc/amd/cezanne/psp_verstage/Makefile.inc index 547650d..2cb1345 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.inc +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.inc @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -verstage-generic-ccopts += -I$(src)/soc/amd/cezanne/psp_verstage/include verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/cezanne/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include -- To view, visit https://review.coreboot.org/c/coreboot/+/71588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Gerrit-Change-Number: 71588 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2023