coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

[M] Change in coreboot[master]: src/drivers/spi: add HID over SPI ACPI driver - WIP
by Eran Mitrani (Code Review) 04 Jan '23

04 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71645 ) Change subject: src/drivers/spi: add HID over SPI ACPI driver - WIP ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/71645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ided6c20da7e5489b9fa32c622f1424e3aba14dd3 Gerrit-Change-Number: 71645 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 04 Jan 2023 00:22:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: src/drivers/spi: add HID over SPI ACPI driver - WIP
by Eran Mitrani (Code Review) 03 Jan '23

03 Jan '23

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71645 ) Change subject: src/drivers/spi: add HID over SPI ACPI driver - WIP ...................................................................... src/drivers/spi: add HID over SPI ACPI driver - WIP Add driver to support ELAN touchscreen using SPI Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: Ided6c20da7e5489b9fa32c622f1424e3aba14dd3 --- A src/drivers/spi/hid/elan/elan7b18uh.asl 1 file changed, 114 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/71645/1 diff --git a/src/drivers/spi/hid/elan/elan7b18uh.asl b/src/drivers/spi/hid/elan/elan7b18uh.asl new file mode 100644 index 0000000..d91f7c3 --- /dev/null +++ b/src/drivers/spi/hid/elan/elan7b18uh.asl @@ -0,0 +1,102 @@ +// ELAN7B18UH - HID over SPI +// - see "HID Over SPI Protocol Specification" section 5.2 - ACPI enum +// https://www.microsoft.com/en-us/download/details.aspx?id=103325 + +// FIXME - WIP - most fields need to be updated based on ENAN spec +Scope (\_SB) { + Device(TCSC) { + Name (_HID, "ELAN7B18UH”) // FIXME VendorID + DeviceID - <VVVVdddd> + Name (_CID, "PNP0C51") // Compatible ID - PNP0C50 or PNP0C51 ? + Name (_SUB, "???") // SubVendorID + SubSystemID - <VVVVssss> + Name (_HRV, 0x0000) // Hardware Revision Number - 2 bytes + + Name (_CRS, ResourceTemplate () { + SpiSerialBusV2 ( + 0, // DeviceSelection + PolarityLow, // DeviceSelectionPolarity + FourWireMode, // WireMode + 8, // DataBitLength + ControllerInitiated, // SlaveMode + 1000000, // ConnectionSpeed (1MHz) + ClockPolarityLow, // ClockPolarity + ClockPhaseFirst, // ClockPhase + "\\_SB.PCI0.SPI0", // ResourceSource + 0, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + GpioInt ( + Level, // InterruptType + ActiveLow, // InterruptLevel + Exclusive, // ShareType + PullUp, // PinConfig + 0x0000, // DeBounceTime + "\\_SB.GPO0", // ResourceSource + 0x00, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + { + 00 // Which INT#? + } + } + // _DSM - Device-Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision ID – Will be 3 for HidSpi V1 + // Arg2: Integer Function Index (0 = Return Supported Functions) + // Arg3: Package Parameters + // + Function(_DSM,{BuffObj, IntObj},{BuffObj, IntObj, IntObj, PkgObj}){ + // HIDSPI UUID + If(LEqual(Arg0,ToUUID("6E2AC436-0FCF-41AF-A265-B32A220DCFAB"))) { + + // Switch on the function index + switch(Arg2) { + case(0) { + // Switch on the revision level + switch(ToInteger(Arg1)) { + case (3) { + // HidSpi v1 : Functions 0-6 inclusive are supported (0b01111111) + Return(Buffer(One) { 0x7F }) + } + default { + // Unsupported revision + Return(Buffer(One) { 0x00 }) + } + } + } + case(1) { + // Input Report Header address + Return (0x1000) + } + case(2) { + // Input Report Body address + Return (0x1004) + } + case(3) { + // Output Report Header address + Return (0x2000) + } + case(4) { + // Read opcode + Return (Buffer(1) {0x0B}) + } + case(5) { + // Write opcode + Return (Buffer(1) {0x02}) + } + case(6) { + // Flags + Return (0x0000) + } + default { + // Unsupported function index + } + } + } + else { + // No functions are supported for this UUID. + return (Buffer() {0}) + } + } + Function(_RST) {} // Placeholder for function-level device reset +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ided6c20da7e5489b9fa32c622f1424e3aba14dd3 Gerrit-Change-Number: 71645 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: device/xhci: Add functions to work with resource pointers
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Add functions to work with resource pointers ...................................................................... Patch Set 7: Verified+1 (2 comments) File src/device/xhci_resource.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167566): https://review.coreboot.org/c/coreboot/+/69914/comment/80e000d1_d5bf6288 PS7, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167566): https://review.coreboot.org/c/coreboot/+/69914/comment/d9e47ff7_a735ab1b PS7, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 23:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/cezanne: Set up SoC-specific XHCI definitions
by Robert Zieba (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67939 to look at the new patch set (#15). Change subject: soc/amd/cezanne: Set up SoC-specific XHCI definitions ...................................................................... soc/amd/cezanne: Set up SoC-specific XHCI definitions Set up SoC-specific XHCI definitions and enable SOC_AMD_COMMON_BLOCK_XHCI. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/xhci.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/67939/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/67939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Gerrit-Change-Number: 67939 Gerrit-PatchSet: 15 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: cpu/x86/smm: Add PCI resource store functionality
by Robert Zieba (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Arthur Heymans, Robert Zieba, Raul Rangel, Nico Huber, Angel Pons, Karthik Ramasubramanian, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Martin Roth, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67931 to look at the new patch set (#14). Change subject: cpu/x86/smm: Add PCI resource store functionality ...................................................................... cpu/x86/smm: Add PCI resource store functionality In certain cases data within protected memmory areas like SMRAM could be leaked or modified if an attacker remaps PCI BARs to point within that area. Add support to the existing SMM runtime to allow storing PCI resources in SMRAM and then later retrieving them. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 --- M src/cpu/x86/Kconfig M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/pci_resource_store.c M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/cpu/x86/smm.h 6 files changed, 143 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/67931/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 14 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/intel/meteorlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71644 ) Change subject: soc/intel/meteorlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 1: (1 comment) This change is ready for review. File src/soc/intel/meteorlake/acpi.c: https://review.coreboot.org/c/coreboot/+/71644/comment/635382a0_9c70ed4f PS1, Line 172: // { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, : { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, : // { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, : // { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, : { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, : { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, : { PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, : // { PCH_DEVFN_I2C6, ACPI_DEVICE_SLEEP_D3 }, : // { PCH_DEVFN_I2C7, ACPI_DEVICE_SLEEP_D3 }, Tarun, Regarding the commented out entries - I wasn't sure where you got these from in the original CL (https://review.coreboot.org/c/coreboot/+/63969) I couldn't find them on the 595644 doc mentioned in that CL. Can you please help with clarifying that? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/71644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 Gerrit-Change-Number: 71644 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:39:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/meteorlake: provide a list of D-states to enter LPM
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71644 ) Change subject: soc/intel/meteorlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167564): https://review.coreboot.org/c/coreboot/+/71644/comment/d7256a1c_e52823d6 PS1, Line 10: 'coresponding' may be misspelled - perhaps 'corresponding'? -- To view, visit https://review.coreboot.org/c/coreboot/+/71644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 Gerrit-Change-Number: 71644 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:33:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/meteorlake: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 03 Jan '23

03 Jan '23

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71644 ) Change subject: soc/intel/meteorlake: provide a list of D-states to enter LPM ...................................................................... soc/intel/meteorlake: provide a list of D-states to enter LPM Provide D-states to enter LPM (S0ix) for MTL Values were copied over from coresponding ADL file (as MTL data sheet is not yet available). TEST=Built and tested on Rex by verifying SSDT contents Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 --- M src/soc/intel/meteorlake/acpi.c 1 file changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/71644/1 diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index c049d07..aef2e23 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -167,6 +167,70 @@ fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } +static struct min_sleep_state min_pci_sleep_states[] = { + { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, +// { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, +// { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, +// { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 }, +// { PCH_DEVFN_I2C6, ACPI_DEVICE_SLEEP_D3 }, +// { PCH_DEVFN_I2C7, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, + { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, + { PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, +}; + +struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) +{ + *size = ARRAY_SIZE(min_pci_sleep_states); + return min_pci_sleep_states; +} + uint32_t soc_read_sci_irq_select(void) { return read32p(soc_read_pmc_base() + IRQ_REG); -- To view, visit https://review.coreboot.org/c/coreboot/+/71644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8 Gerrit-Change-Number: 71644 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/intel/common: Untie PRMRR from SGX
by Pratikkumar V Prajapati (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70819 ) Change subject: soc/intel/common: Untie PRMRR from SGX ...................................................................... Patch Set 18: (1 comment) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/70819/comment/a68340bb_146a842f PS17, Line 408: if (CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE == 0) > ``` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/70819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Gerrit-Change-Number: 70819 Gerrit-PatchSet: 18 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Will Kim <norwayforest92(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:08:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/common: Untie PRMRR from SGX
by Pratikkumar V Prajapati (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Sridhar Siricilla, Pratikkumar V Prajapati. Hello Will Kim, build bot (Jenkins), Tarun Tuli, Subrata Banik, Wonkyu Kim, Kapil Porwal, Sridhar Siricilla, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70819 to look at the new patch set (#18). Change subject: soc/intel/common: Untie PRMRR from SGX ...................................................................... soc/intel/common: Untie PRMRR from SGX PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. Finally check if features that need PRMRR are configured and supproted before returning PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/sgx/Kconfig 3 files changed, 90 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/70819/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/70819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Gerrit-Change-Number: 70819 Gerrit-PatchSet: 18 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Will Kim <norwayforest92(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2023