coreboot-gerrit January 2023

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

[S] Change in coreboot[master]: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
by Pratikkumar V Prajapati (Code Review) 03 Jan '23

03 Jan '23

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71569 ) Change subject: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Thanks for the +2 but this patch wont build standalone. Let me know what do you recommend for my previous comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/71569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Gerrit-Change-Number: 71569 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:03:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/baytrail: add _HRV to GPIO ACPI devices
by 9elements QA (Code Review) 03 Jan '23

03 Jan '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71200 ) Change subject: soc/intel/baytrail: add _HRV to GPIO ACPI devices ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 2 / 14 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/143099 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/143098 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/143097 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/143096 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/143095 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/143094 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/143093 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/143092 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/143091 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/143090 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/143089 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/143088 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/143087 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/143086 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/71200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Gerrit-Change-Number: 71200 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/common: Add API to check Key Locker support
by Pratikkumar V Prajapati (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Martin L Roth, Subrata Banik, Paul Menzel. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71117 ) Change subject: soc/intel/common: Add API to check Key Locker support ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/c/coreboot/+/71117/comment/33c8ae17_4ea3e9a4 PS7, Line 39: #define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7 > Use this macro? Done https://review.coreboot.org/c/coreboot/+/71117/comment/6b17ba7e_f61adaf8 PS7, Line 542: 0x7 > Could you update this to use the CPUID_STRUCT_EXTENDED_FEATURE_FLAGS definition? […] I will push separate patch to address this and apply to all function. For now marking these comments DONE. -- To view, visit https://review.coreboot.org/c/coreboot/+/71117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Gerrit-Change-Number: 71117 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 03 Jan 2023 22:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
by Jon Murphy (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68942 ) Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Should this change be abandoned? It looks like everything above it is merged and this CL was combined into one of them? -- To view, visit https://review.coreboot.org/c/coreboot/+/68942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3 Gerrit-Change-Number: 68942 Gerrit-PatchSet: 9 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 03 Jan 2023 21:42:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
by Caveh Jalali (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Derek Huang, Christian Walter, Nick Vaccaro, Daisuke Nojiri, Eric Lai, Boris Mittelberg. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70773 ) Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag ...................................................................... Patch Set 16: (1 comment) File src/ec/google/chromeec/ec_commands.h: PS16: we should really have a separate patch to refresh ec_commands.h from the EC repo. ideally, a bulk update (copy) to keep things in sync rather than selecting a few lines that seem relevant. -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 16 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 21:28:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimiz...
by Jason Glenesk (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 19:47:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Pass option about compression status of BIOS
by Paul Menzel (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71211 ) Change subject: soc/amd/mendocino: Pass option about compression status of BIOS ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71211/comment/581fa97f_a604a703 PS2, Line 9: When CBFS verification is enabled and verified boot starts in bootblock, : PSP BIOS binary is uncompressed. > It's not really ambiguous. This says "is uncompressed" not "is being uncompressed". […] Thank you for the clarification. -- To view, visit https://review.coreboot.org/c/coreboot/+/71211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2e935c7e137a305f6ed4bede91d3d0ba4ca6c7 Gerrit-Change-Number: 71211 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 19:44:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimiz...
by Paul Menzel (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Chris Wang, Martin Roth, Karthik Ramasubramanian, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71562 ) Change subject: soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/mendocino/chip.h: https://review.coreboot.org/c/coreboot/+/71562/comment/f7965ca2_fda4d953 PS2, Line 167: w/a > Because it's a workaround of an issue we were seeing. It's not a fix. Then please summarize the problem in the comment or commit message. https://review.coreboot.org/c/coreboot/+/71562/comment/5ec47fa7_b8287c32 PS2, Line 168: dxio_tx_vboost_enable > coreboot/src% grep -ir "_enable" | grep -v vendorcode | wc -l […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/71562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Gerrit-Change-Number: 71562 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 03 Jan 2023 19:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/meteorlake: Fill PCI SSID parameters
by Kapil Porwal (Code Review) 03 Jan '23

03 Jan '23

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71643 ) Change subject: soc/intel/meteorlake: Fill PCI SSID parameters ...................................................................... soc/intel/meteorlake: Fill PCI SSID parameters BUG=none TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in OS: 00:00.0 Host bridge [0600]: Intel Corporation Device [8086:7d01] Subsystem: Intel Corporation Device [8086:7d01] 00:02.0 VGA compatible controller [0300]: Intel Corporation Device [8086:7d55] (prog-if 00 [VGA controller]) Subsystem: Intel Corporation Device [8086:7d55] 00:04.0 Signal processing controller [1180]: Intel Corporation Device [8086:7d03] Subsystem: Intel Corporation Device [8086:7d03] 00:05.0 Multimedia controller [0480]: Intel Corporation Device [8086:7d19] Subsystem: Intel Corporation Device [8086:7d19] 00:06.0 PCI bridge [0604]: Intel Corporation Device [8086:7e4d] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e4d] 00:07.0 PCI bridge [0604]: Intel Corporation Device [8086:7ec4] (prog-if 00 [Normal decode]) Capabilities: [90] Subsystem: Intel Corporation Device [8086:7ec4] 00:07.2 PCI bridge [0604]: Intel Corporation Device [8086:7ec6] (prog-if 00 [Normal decode]) Capabilities: [90] Subsystem: Intel Corporation Device [8086:7ec6] 00:0a.0 Signal processing controller [1180]: Intel Corporation Device [8086:7d0d] (rev 01) Subsystem: Intel Corporation Device [8086:7d0d] 00:0d.0 USB controller [0c03]: Intel Corporation Device [8086:7ec0] (prog-if 30 [XHCI]) Subsystem: Intel Corporation Device [8086:7ec0] 00:0d.2 USB controller [0c03]: Intel Corporation Device [8086:7ec2] (prog-if 40 [USB4 Host Interface]) Subsystem: Intel Corporation Device [8086:7ec2] 00:0d.3 USB controller [0c03]: Intel Corporation Device [8086:7ec3] (prog-if 40 [USB4 Host Interface]) Subsystem: Intel Corporation Device [8086:7ec3] 00:14.0 USB controller [0c03]: Intel Corporation Device [8086:7e7d] (prog-if 30 [XHCI]) Subsystem: Intel Corporation Device [8086:7e7d] 00:14.2 RAM memory [0500]: Intel Corporation Device [8086:7e7f] Subsystem: Intel Corporation Device [8086:7e7f] 00:14.3 Network controller [0280]: Intel Corporation Device [8086:7e40] Subsystem: Intel Corporation Device [8086:0094] 00:15.0 Serial bus controller [0c80]: Intel Corporation Device [8086:7e78] Subsystem: Intel Corporation Device [8086:7e78] 00:15.1 Serial bus controller [0c80]: Intel Corporation Device [8086:7e79] Subsystem: Intel Corporation Device [8086:7e79] 00:15.3 Serial bus controller [0c80]: Intel Corporation Device [8086:7e7b] Subsystem: Intel Corporation Device [8086:7e7b] 00:16.0 Communication controller [0780]: Intel Corporation Device [8086:7e70] Subsystem: Intel Corporation Device [8086:7e70] 00:19.0 Serial bus controller [0c80]: Intel Corporation Device [8086:7e50] Subsystem: Intel Corporation Device [8086:7e50] 00:19.1 Serial bus controller [0c80]: Intel Corporation Device [8086:7e51] Subsystem: Intel Corporation Device [8086:7e51] 00:1c.0 PCI bridge [0604]: Intel Corporation Device [8086:7e3c] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3c] 00:1c.5 PCI bridge [0604]: Intel Corporation Device [8086:7e3d] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3d] 00:1c.6 PCI bridge [0604]: Intel Corporation Device [8086:7e3e] (prog-if 00 [Normal decode]) Capabilities: [98] Subsystem: Intel Corporation Device [8086:7e3e] 00:1e.0 Communication controller [0780]: Intel Corporation Device [8086:7e25] Subsystem: Intel Corporation Device [8086:7e25] 00:1e.3 Serial bus controller [0c80]: Intel Corporation Device [8086:7e30] Subsystem: Intel Corporation Device [8086:7e30] 00:1f.0 ISA bridge [0601]: Intel Corporation Device [8086:7e01] Subsystem: Intel Corporation Device [8086:7e01] 00:1f.3 Multimedia audio controller [0401]: Intel Corporation Device [8086:7e28] 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23] Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 141 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/71643/1 diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index d40779a..2e1baa5 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -456,6 +456,75 @@ fsp_debug_event_handler; } +static void evaluate_ssid(const struct device *dev, uint16_t *svid, uint16_t *ssid) +{ + if(dev && svid && ssid) { + if (CONFIG_SUBSYSTEM_VENDOR_ID) + *svid = CONFIG_SUBSYSTEM_VENDOR_ID; + else + *svid = dev->subsystem_vendor ? : 0x8086; + if (CONFIG_SUBSYSTEM_DEVICE_ID) + *ssid = CONFIG_SUBSYSTEM_DEVICE_ID; + else + *ssid = dev->subsystem_device ? : 0xFFFE; + } +} + +static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + /* + * Prevent FSP from programming write-once subsystem IDs by providing + * a custom SSID table. Must have at least one entry for the FSP to + * use the table. + */ + struct svid_ssid_init_entry { + union { + struct { + uint64_t reg:12; /* Register offset */ + uint64_t function:3; + uint64_t device:5; + uint64_t bus:8; + uint64_t :4; + uint64_t segment:16; + uint64_t :16; + }; + uint64_t segbusdevfuncregister; + }; + struct { + uint16_t svid; + uint16_t ssid; + }; + uint32_t reserved; + }; + + static struct svid_ssid_init_entry ssid_table[256]; + const struct device *dev; + int i = 0; + + for (dev = all_devices; dev; dev = dev->next) { + if (!(is_dev_enabled(dev) && + dev->path.type == DEVICE_PATH_PCI && + dev->bus->secondary == 0)) + continue; + if(dev->path.pci.devfn == PCI_DEVFN_ROOT) { + evaluate_ssid(dev, &s_cfg->SiCustomizedSvid, &s_cfg->SiCustomizedSsid); + } else { + ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; + ssid_table[i].device = PCI_SLOT(dev->path.pci.devfn); + ssid_table[i].function = PCI_FUNC(dev->path.pci.devfn); + evaluate_ssid(dev, &ssid_table[i].svid, &ssid_table[i].ssid); + i++; + } + } + + s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; + s_cfg->SiNumberOfSsidTableEntry = i; + + /* Ensure FSP will program the registers */ + s_cfg->SiSkipSsidProgramming = 0; +} + static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, struct soc_intel_meteorlake_config *config) { @@ -484,6 +553,7 @@ fill_fsps_misc_power_params, fill_fsps_ufs_params, fill_fsps_ai_params, + fill_fsps_pci_ssid_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/71643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Gerrit-Change-Number: 71643 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/intel/common: Fix cpu index calculation
by Sridhar Siricilla (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, Sukumar Ghorai, Raj Astekar. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70751 ) Change subject: soc/intel/common: Fix cpu index calculation ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/70751/comment/79942fda_a4d93ce5 PS7, Line 34: g_cpu_bus > dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER) would also work. Hmm, I had tested this, but this is not working. -- To view, visit https://review.coreboot.org/c/coreboot/+/70751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Gerrit-Change-Number: 70751 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 19:28:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2023