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Change subject: soc/intel/: Rename small and big cores references
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> wondering if we can create a custom data structure and use it ?
The patch purpose is only renaming. I will try to address the suggestions in the separate CL.
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Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
......................................................................
Patch Set 16: Code-Review+2
(1 comment)
File src/vendorcode/google/chromeos/cr50_enable_update.c:
https://review.coreboot.org/c/coreboot/+/70773/comment/9765af92_7a46cdcf
PS16, Line 79: printk(BIOS_INFO, "Successfully clear AP_IDLE flag");
do we need success msg always or just able to catch the failure case is fine?
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Change subject: mb/google/brya: Create omnigul variant
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167540):
https://review.coreboot.org/c/coreboot/+/71640/comment/0ee43ee9_6970ecc6
PS1, Line 9: # See util/spd_tools/README.md for more details and instructions.
'README' may be misspelled - perhaps 'README'?
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Change subject: Documentation/getting_started: Add information about ost2
......................................................................
Patch Set 2:
(1 comment)
File Documentation/getting_started/OST2.md:
https://review.coreboot.org/c/coreboot/+/70853/comment/ddaa5152_68d5be22
PS2, Line 27: There are more courses, which can be found [here](https://p.ost2.fyi/courses).
Please add the missing new line at the end of file.
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Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71640 )
Change subject: mb/google/brya: Create omnigul variant
......................................................................
mb/google/brya: Create omnigul variant
Create the omnigul variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:263060849
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OMNIGUL
Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d
Signed-off-by: jamie_chen <jamie_chen(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/omnigul/include/variant/ec.h
A src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h
A src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
A src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/omnigul/overridetree.cb
8 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/71640/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 1fb78c0..7865ad9 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -222,6 +222,7 @@
default "Zydron" if BOARD_GOOGLE_ZYDRON
default "Gladios" if BOARD_GOOGLE_GLADIOS
default "Marasov" if BOARD_GOOGLE_MARASOV
+ default "Omnigul" if BOARD_GOOGLE_OMNIGUL
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -263,6 +264,7 @@
default "zydron" if BOARD_GOOGLE_ZYDRON
default "gladios" if BOARD_GOOGLE_GLADIOS
default "marasov" if BOARD_GOOGLE_MARASOV
+ default "omnigul" if BOARD_GOOGLE_OMNIGUL
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 8e38735..06159cf 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -316,3 +316,7 @@
select BOARD_GOOGLE_BASEBOARD_BRYA
select SOC_INTEL_RAPTORLAKE
select DRIVERS_INTEL_ISH
+
+config BOARD_GOOGLE_OMNIGUL
+ bool "-> Omnigul"
+ select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h b/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h b/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
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Change subject: vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure State
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/mendocino/psp_verstage/svc.h:
https://review.coreboot.org/c/coreboot/+/71207/comment/db2ba4af_13280c3c
PS1, Line 102: unsigned int *ptr_hsp_secure_state;
In the PSP release, this is an unsigned int hsp_secure_state instead of a pointer to it.
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Hello Tarun Tuli, Subrata Banik, Kapil Porwal, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71639
to look at the new patch set (#2).
Change subject: soc/intel/: Rename small and big cores references
......................................................................
soc/intel/: Rename small and big cores references
The patch addresses Intel heterogeneous cores as `Efficient` and
`Performance` cores instead of `small` and `big` cores. It is to ensure
coreboot code has uniform reference to the heterogeneous cores. So, the
patch renames all `small` and `big` core references to `efficient` (eff)
and `performance` (perf) cores respectively.
TEST=Build the code for Brya and Rex boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f
---
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/common/block/acpi/cpu_hybrid.c
M src/soc/intel/common/block/include/intelblocks/acpi.h
M src/soc/intel/meteorlake/cpu.c
4 files changed, 43 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/71639/2
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