coreboot-gerrit January 2023

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[M] Change in coreboot[master]: soc/intel: Create common function to check PCH slot
by Subrata Banik (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71236 ) Change subject: soc/intel: Create common function to check PCH slot ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Gerrit-Change-Number: 71236 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:58:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
by build bot (Jenkins) (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Caveh Jalali, Christian Walter, Nick Vaccaro, Daisuke Nojiri, Eric Lai, Boris Mittelberg. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70773 ) Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag ...................................................................... Patch Set 14: (1 comment) File src/vendorcode/google/chromeos/cr50_enable_update.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-167531): https://review.coreboot.org/c/coreboot/+/70773/comment/c74a32de_907a8ac0 PS14, Line 158: if (CONFIG(POWER_OFF_ON_CR50_UPDATE)) { suspicious code indentation after conditional statements -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 14 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:58:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
by Derek Huang (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Derek Huang, Caveh Jalali, Nick Vaccaro, Daisuke Nojiri, Eric Lai, Boris Mittelberg. Hello Tarun Tuli, Subrata Banik, Caveh Jalali, Nick Vaccaro, Daisuke Nojiri, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70773 to look at the new patch set (#14). Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag ...................................................................... chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang(a)google.com> --- M src/ec/google/chromeec/ec_commands.h M src/mainboard/google/brya/Kconfig M src/security/tpm/tss/vendor/cr50/Kconfig M src/vendorcode/google/chromeos/cr50_enable_update.c 4 files changed, 50 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/70773/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 14 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Create common function to check PCH slot
by Kapil Porwal (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71236 ) Change subject: soc/intel: Create common function to check PCH slot ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/include/intelblocks/irq.h: https://review.coreboot.org/c/coreboot/+/71236/comment/f952142d_fda43eb8 PS5, Line 71: a slot belongs to PCH IP of SoC die or is a root : * port from IOE die. > nit: a slot belongs to the SoC or IOE die. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/71236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Gerrit-Change-Number: 71236 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update GPIO settings
by John Su (Code Review) 03 Jan '23

03 Jan '23

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71635 ) Change subject: mb/google/skyrim/var/markarth: Update GPIO settings ...................................................................... mb/google/skyrim/var/markarth: Update GPIO settings Configure GPIOs based on b/263534907#comment4 from EE. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 --- M src/mainboard/google/skyrim/variants/markarth/Makefile.inc A src/mainboard/google/skyrim/variants/markarth/gpio.c 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/71635/1 diff --git a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc index 88e75bd..83f7700 100644 --- a/src/mainboard/google/skyrim/variants/markarth/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/markarth/Makefile.inc @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./memory +ramstage-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c new file mode 100644 index 0000000..0a7c17a --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <gpio.h> + +/* GPIO configuration in ramstage */ +static const struct soc_amd_gpio override_gpio_table[] = { + + /* SOC_PEN_DETECT_ODL => Unused */ + PAD_NC(GPIO_3), + /* EN_PWR_FP => Unused */ + PAD_NC(GPIO_4), + /* EN_PWR_WWAN_X => Unused */ + PAD_NC(GPIO_8), + /* SOC_FP_INT_L => Unused */ + PAD_NC(GPIO_24), + /* SD_AUX_RST_SOC_L => Unused */ + PAD_NC(GPIO_27), + /* WWAN_RST_L => Unused */ + PAD_NC(GPIO_42), +}; + +void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(override_gpio_table); + *gpio = override_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021 Gerrit-Change-Number: 71635 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya/var/marasov: Update DPTF parameters
by Frank Chu (Code Review) 03 Jan '23

03 Jan '23

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71634 ) Change subject: mb/google/brya/var/marasov: Update DPTF parameters ...................................................................... mb/google/brya/var/marasov: Update DPTF parameters Update the first version DPTF parameters received from the thermal team. BUG=b:264217345 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5 --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/71634/1 diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index bf9d5e0..079a821 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -104,7 +104,91 @@ register "tcss_ports[1]" = "TCSS_PORT_EMPTY" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" + register "tcss_aux_ori" = "1" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""Charge"" + register "options.tsr[1].desc" = ""5V"" + register "options.tsr[2].desc" = ""AMB"" + register "options.tsr[3].desc" = ""CPU Power"" + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(90, 100), + TEMP_PCT(58, 70), + TEMP_PCT(55, 65), + TEMP_PCT(53, 60), + TEMP_PCT(50, 58), + TEMP_PCT(48, 54), + TEMP_PCT(43, 47), + TEMP_PCT(38, 42), + TEMP_PCT(35, 37), + TEMP_PCT(33, 0), + } + }, + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 70, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 65, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 90, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 36, 2300 }, + [1] = { 31, 2000 }, + [2] = { 26, 1700 }, + [3] = { 20, 1300 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/71634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5 Gerrit-Change-Number: 71634 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values...
by Jincheng Li (Code Review) 03 Jan '23

03 Jan '23

Jincheng Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71633 ) Change subject: arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros ...................................................................... arch/x86/smbios: Replace SMBIOS type4 processor upgrade fields values by macros Macro definitions are from DMTF System Management BIOS (SMBIOS) Reference Specification (DSP0134) Chapter 7.5.5. Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 95 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/71633/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8d9de7c..76d26dc 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -401,15 +401,15 @@ static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) - return 0x08; + return PROCESSOR_UPGRADE_SLOT_1; if (CONFIG(CPU_INTEL_SOCKET_MPGA604)) - return 0x13; + return PROCESSOR_UPGRADE_SOCKET_MPGA604; if (CONFIG(CPU_INTEL_SOCKET_LGA775)) - return 0x15; + return PROCESSOR_UPGRADE_SOCKET_LGA775; if (CONFIG(XEON_SP_COMMON_BASE)) - return 0x36; + return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; if (CONFIG(SOC_INTEL_ALDERLAKE)) - return 0x40; + return PROCESSOR_UPGRADE_SOCKET_LGA1700; return 0x02; /* Unknown */ } diff --git a/src/include/smbios.h b/src/include/smbios.h index 9217f5e..446652c 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -486,6 +486,82 @@ #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) +/* enum for socket type */ +enum smbios_processor_upgrade_field { + PROCESSOR_UPGRADE_OTHER = 0x01, + PROCESSOR_UPGRADE_UNKNOWN = 0x02, + PROCESSOR_UPGRADE_DAUGHTER_BOARD = 0x03, + PROCESSOR_UPGRADE_ZIF_SOCKET = 0x04, + PROCESSOR_UPGRADE_REPLACEABLE_PIGGY_BACK = 0x05, + PROCESSOR_UPGRADE_NONE = 0x06, + PROCESSOR_UPGRADE_LIF_SOCKET = 0x07, + PROCESSOR_UPGRADE_SLOT_1 = 0x08, + PROCESSOR_UPGRADE_SLOT_2 = 0x09, + PROCESSOR_UPGRADE_370_PIN_SOCKET = 0x0a, + PROCESSOR_UPGRADE_SLOT_A = 0x0b, + PROCESSOR_UPGRADE_SLOT_M = 0x0c, + PROCESSOR_UPGRADE_SOCKET_423 = 0x0d, + PROCESSOR_UPGRADE_SOCKET_A = 0x0e, + PROCESSOR_UPGRADE_SOCKET_478 = 0x0f, + PROCESSOR_UPGRADE_SOCKET_754 = 0x10, + PROCESSOR_UPGRADE_SOCKET_940 = 0x11, + PROCESSOR_UPGRADE_SOCKET_939 = 0x12, + PROCESSOR_UPGRADE_SOCKET_MPGA604 = 0x13, + PROCESSOR_UPGRADE_SOCKET_LGA771 = 0x14, + PROCESSOR_UPGRADE_SOCKET_LGA775 = 0x15, + PROCESSOR_UPGRADE_SOCKET_S1 = 0x16, + PROCESSOR_UPGRADE_SOCKET_AM2 = 0x17, + PROCESSOR_UPGRADE_SOCKET_F = 0x18, + PROCESSOR_UPGRADE_SOCKET_LGA1366 = 0x19, + PROCESSOR_UPGRADE_SOCKET_G34 = 0x1a, + PROCESSOR_UPGRADE_SOCKET_AM3 = 0x1b, + PROCESSOR_UPGRADE_SOCKET_C32 = 0x1c, + PROCESSOR_UPGRADE_SOCKET_LGA1156 = 0x1d, + PROCESSOR_UPGRADE_SOCKET_LGA1567 = 0x1e, + PROCESSOR_UPGRADE_SOCKET_PGA988A = 0x1f, + PROCESSOR_UPGRADE_SOCKET_BGA1288 = 0x20, + PROCESSOR_UPGRADE_SOCKET_RPGA988B = 0x21, + PROCESSOR_UPGRADE_SOCKET_BGA1023 = 0x22, + PROCESSOR_UPGRADE_SOCKET_BGA1224 = 0x23, + PROCESSOR_UPGRADE_SOCKET_LGA1155 = 0x24, + PROCESSOR_UPGRADE_SOCKET_LGA1356 = 0x25, + PROCESSOR_UPGRADE_SOCKET_LGA2011 = 0x26, + PROCESSOR_UPGRADE_SOCKET_FS1 = 0x27, + PROCESSOR_UPGRADE_SOCKET_FS2 = 0x28, + PROCESSOR_UPGRADE_SOCKET_FM1 = 0x29, + PROCESSOR_UPGRADE_SOCKET_FM2 = 0x2a, + PROCESSOR_UPGRADE_SOCKET_LGA2011_3 = 0x2b, + PROCESSOR_UPGRADE_SOCKET_LGA1356_3 = 0x2c, + PROCESSOR_UPGRADE_SOCKET_LGA1150 = 0x2d, + PROCESSOR_UPGRADE_SOCKET_BGA1168 = 0x2e, + PROCESSOR_UPGRADE_SOCKET_BGA1234 = 0x2f, + PROCESSOR_UPGRADE_SOCKET_BGA1364 = 0x30, + PROCESSOR_UPGRADE_SOCKET_AM4 = 0x31, + PROCESSOR_UPGRADE_SOCKET_LGA1151 = 0x32, + PROCESSOR_UPGRADE_SOCKET_BGA1356 = 0x33, + PROCESSOR_UPGRADE_SOCKET_BGA1440 = 0x34, + PROCESSOR_UPGRADE_SOCKET_BGA1515 = 0x35, + PROCESSOR_UPGRADE_SOCKET_LGA3647_1 = 0x36, + PROCESSOR_UPGRADE_SOCKET_SP3 = 0x37, + PROCESSOR_UPGRADE_SOCKET_SP3R2 = 0x38, + PROCESSOR_UPGRADE_SOCKET_LGA2066 = 0x39, + PROCESSOR_UPGRADE_SOCKET_BGA1392 = 0x3a, + PROCESSOR_UPGRADE_SOCKET_BGA1510 = 0x3b, + PROCESSOR_UPGRADE_SOCKET_BGA1528 = 0x3c, + PROCESSOR_UPGRADE_SOCKET_LGA4189 = 0x3d, + PROCESSOR_UPGRADE_SOCKET_LGA1200 = 0x3e, + PROCESSOR_UPGRADE_SOCKET_LGA4677 = 0x3f, + PROCESSOR_UPGRADE_SOCKET_LGA1700 = 0x40, + PROCESSOR_UPGRADE_SOCKET_BGA1744 = 0x41, + PROCESSOR_UPGRADE_SOCKET_BGA1781 = 0x42, + PROCESSOR_UPGRADE_SOCKET_BGA1211 = 0x43, + PROCESSOR_UPGRADE_SOCKET_BGA2422 = 0x44, + PROCESSOR_UPGRADE_SOCKET_LGA1211 = 0x45, + PROCESSOR_UPGRADE_SOCKET_LGA2422 = 0x46, + PROCESSOR_UPGRADE_SOCKET_LGA5773 = 0x47, + PROCESSOR_UPGRADE_SOCKET_BGA5773 = 0x48, +}; + /* defines for processor family */ #define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 #define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 -- To view, visit https://review.coreboot.org/c/coreboot/+/71633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed1d773b0b349f878648b8172fd770a397e9686 Gerrit-Change-Number: 71633 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW
by Ivy Jian (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71631 ) Change subject: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Gerrit-Change-Number: 71631 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:38:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW
by Eric Lai (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71631 ) Change subject: mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOW ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > > Who will set it high if there is no driver to control it? IIUC, there is no audio drier will contr […] yes, Ivy explain to me. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/71631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Gerrit-Change-Number: 71631 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:07:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag
by Subrata Banik (Code Review) 03 Jan '23

03 Jan '23

Attention is currently required from: Tarun Tuli, Derek Huang, Caveh Jalali, Nick Vaccaro, Daisuke Nojiri, Eric Lai, Boris Mittelberg. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70773 ) Change subject: chromeos/cr50_enable_update.c: Clear EC AP_IDLE flag ...................................................................... Patch Set 13: (2 comments) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/70773/comment/f336b023_e8078796 PS12, Line 336: config CR50_RESET_CLEAR_EC_AP_IDLE_FLAG > this should move to common code. +2 File src/vendorcode/google/chromeos/cr50_enable_update.c: https://review.coreboot.org/c/coreboot/+/70773/comment/ff63aaf9_7030e132 PS13, Line 159: if (CONFIG(CR50_RESET_CLEAR_EC_AP_IDLE_FLAG)) { : /* Send EC command to clear AP_IDLE flag */ : if (!google_chromeec_reboot(0, EC_REBOOT_NO_OP, : EC_REBOOT_FLAG_CLEAR_AP_IDLE | : EC_REBOOT_FLAG_ON_AP_SHUTDOWN)) : printk(BIOS_INFO, : "Successfully clear AP_IDLE flag"); : else : printk(BIOS_ERR, : "Failed to clear EC AP_IDLE flag"); : } suggestion: please create a helper function -- To view, visit https://review.coreboot.org/c/coreboot/+/70773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Gerrit-Change-Number: 70773 Gerrit-PatchSet: 13 Gerrit-Owner: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 03 Jan 2023 07:06:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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