coreboot-gerrit January 2023

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[S] Change in coreboot[master]: drivers/intel/i210/Makefile.inc: Remove a link path to itself
by Elyes Haouas (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Angel Pons, Werner Zeh. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70468 ) Change subject: drivers/intel/i210/Makefile.inc: Remove a link path to itself ...................................................................... Patch Set 13: (1 comment) Patchset: PS8: > sure! Please let make some progress. Is this ok for you?: ``` diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc index 218b1b45f9..e599798f9b 100644 --- a/src/drivers/intel/i210/Makefile.inc +++ b/src/drivers/intel/i210/Makefile.inc @@ -1,7 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_DRIVER_INTEL_I210)+= i210.c - -ifeq ($(CONFIG_DRIVER_INTEL_I210),y) -CFLAGS_x86_32 += -Isrc/drivers/intel/i210 -endif diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc index fa7aea9049..84675e45c1 100644 --- a/src/mainboard/siemens/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -10,4 +10,8 @@ ramstage-y += mainboard.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +ifeq ($(CONFIG_DRIVER_INTEL_I210),y) +CPPFLAGS_common += -I$(src)/drivers/intel/i210 +endif + subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/mc_ehl/Makefile.inc b/src/mainboard/siemens/mc_ehl/Makefile.inc index e34eddb9f1..525961e72e 100644 --- a/src/mainboard/siemens/mc_ehl/Makefile.inc +++ b/src/mainboard/siemens/mc_ehl/Makefile.inc @@ -11,4 +11,8 @@ ramstage-y += mainboard.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +ifeq ($(CONFIG_DRIVER_INTEL_I210),y) +CPPFLAGS_common += -I$(src)/drivers/intel/i210 +endif + subdirs-y += variants/$(VARIANT_DIR) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/70468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b0f99353ed3a582ea590cbc6b12dec6294c75d Gerrit-Change-Number: 70468 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 06:22:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/pc80/vga: Add API to write multi-line video message
by 9elements QA (Code Review) 02 Jan '23

02 Jan '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71265 ) Change subject: drivers/pc80/vga: Add API to write multi-line video message ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 13 / 1 / 14 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/142933 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/142932 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/142931 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142930 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/142929 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/142928 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/142927 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/142926 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/142925 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/142924 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/142923 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/142922 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/142921 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/142920 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/71265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Gerrit-Change-Number: 71265 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 06:17:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: contributing/coding_style.md: Add and clarify includes rules
by Elyes Haouas (Code Review) 02 Jan '23

02 Jan '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71612 ) Change subject: contributing/coding_style.md: Add and clarify includes rules ...................................................................... contributing/coding_style.md: Add and clarify includes rules Change-Id: I3af2c3b15dda7e8b095767084dae8ee24d478256 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Documentation/contributing/coding_style.md 1 file changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/71612/1 diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index 5b2919e3..e1199d8 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -921,9 +921,29 @@ "file.h"`. Local "file.h" includes should always come separately after all <file.h> includes. Headers that can be included from both assembly files and .c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks, -including includes to other headers that don't follow that provision. Where a -specific include order is required for technical reasons, it should be clearly -documented with comments. +including includes to other headers that don't follow that provision. +The includes should be ordered alphabetically. Where a specific include order is +required for technical reasons, it should be clearly documented with comments. +Don't use UNIX directory '.' or '..' shortcuts and put conditional includes +after the other includes. + +Example: +```c +#include <related_headers.h> +#ifdef CONDITION +#include <conditional_headers.h> +#endif +One blank line +#include "local_headers.h" +#ifdef LOCAL_CONDITION +#include "local_conditional_headers.h" +#endif +One blank line +#include <vendorcode/headers.h> +#ifdef VENDOR_CONDITION +#include <vendor_conditional_headers.h> +#endif +``` Files should generally include every header they need a definition from directly (and not include any unnecessary extra headers). Excepted from -- To view, visit https://review.coreboot.org/c/coreboot/+/71612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3af2c3b15dda7e8b095767084dae8ee24d478256 Gerrit-Change-Number: 71612 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/pc80/vga: Add API to write multi-line video message
by Subrata Banik (Code Review) 02 Jan '23

02 Jan '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71265 ) Change subject: drivers/pc80/vga: Add API to write multi-line video message ...................................................................... drivers/pc80/vga: Add API to write multi-line video message This patch provides an API to allow users to output multi-line messages using VGA framebuffer. The current limitation with multiline message is that, vga_line_write() function is unable to understand newline character hence, eventually output multiple lines separated with a newline character with a single line statement. This patch ensures to parse the entire string and split it into multiple lines based on the newline character and print each line separately to the VFG framebuffer. User can choose to align the output video message as per given choice between left/center/right of the screen (i.e. enum VGA_TEXT_ALIGNMENT ). Additionally, added macros to define the horizontal screen alignment as well. Ideally if user would like to print the video message at the middle of the screen then the vertical alignment would be `VGA_TEXT_CENTER` and horizontal alignment would be `VGA_TEXT_HORIZONTAL_MIDDLE`. TEST=Able to build and boot Google/Taeko. While output a video message such as : "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device." Without this patch: Your device is finishing an update. This may take 1-2 minutes. nPlease do not turn off your device. With this patch: (in Left Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Right Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Center Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/drivers/pc80/vga/vga.c M src/include/pc80/vga.h 2 files changed, 117 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved diff --git a/src/drivers/pc80/vga/vga.c b/src/drivers/pc80/vga/vga.c index 3471c94..a52ba6d 100644 --- a/src/drivers/pc80/vga/vga.c +++ b/src/drivers/pc80/vga/vga.c @@ -256,23 +256,55 @@ vga_cr_write(0x0D, offset & 0xFF); } +static void +vga_write_at_offset(unsigned int line, unsigned int offset, const char *string) +{ + if (!string) + return; + + unsigned short *p = (unsigned short *)VGA_FB + (VGA_COLUMNS * line) + offset; + size_t i, len = strlen(string); + + for (i = 0; i < (VGA_COLUMNS - offset); i++) { + if (i < len) + p[i] = 0x0F00 | string[i]; + else + p[i] = 0x0F00; + } +} + /* * simply fills a line with the given string. */ void vga_line_write(unsigned int line, const char *string) { - if (!string) - return; + vga_write_at_offset(line, 0, string); +} - unsigned short *p = (unsigned short *)VGA_FB + (VGA_COLUMNS * line); - size_t i, len = strlen(string); +void +vga_write_text(enum VGA_TEXT_ALIGNMENT alignment, unsigned int line, const char *string) +{ + char str[VGA_COLUMNS * VGA_LINES] = {0}; + memcpy(str, string, strnlen(string, sizeof(str) - 1)); - for (i = 0; i < VGA_COLUMNS; i++) { - if (i < len) - p[i] = 0x0F00 | string[i]; - else - p[i] = 0x0F00; + char *token = strtok(str, "\n"); + + while (token != NULL) { + size_t offset = VGA_COLUMNS - strnlen(token, VGA_COLUMNS); + switch (alignment) { + case VGA_TEXT_CENTER: + vga_write_at_offset(line++, offset/2, token); + break; + case VGA_TEXT_RIGHT: + vga_write_at_offset(line++, offset, token); + break; + case VGA_TEXT_LEFT: + default: + vga_write_at_offset(line++, 0, token); + break; + } + token = strtok(NULL, "\n"); } } diff --git a/src/include/pc80/vga.h b/src/include/pc80/vga.h index 4b7b26c..ec012f5 100644 --- a/src/include/pc80/vga.h +++ b/src/include/pc80/vga.h @@ -8,6 +8,15 @@ #define VGA_COLUMNS 80 #define VGA_LINES 25 +#define VGA_TEXT_HORIZONTAL_TOP 0 +#define VGA_TEXT_HORIZONTAL_MIDDLE (VGA_LINES / 2) + +enum VGA_TEXT_ALIGNMENT { + VGA_TEXT_LEFT, + VGA_TEXT_CENTER, + VGA_TEXT_RIGHT, +}; + void vga_io_init(void); void vga_textmode_init(void); @@ -20,4 +29,10 @@ void vga_line_write(unsigned int line, const char *string); +/* + * vga_write_text() writes a line of text aligned left/center/right + * horizontally on the screen (i.e. enum VGA_TEXT_ALIGNMENT) + */ +void vga_write_text(enum VGA_TEXT_ALIGNMENT alignment, unsigned int line, const char *string); + #endif /* VGA_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/71265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Gerrit-Change-Number: 71265 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: src/drivers/usb: Add support for Bluetooth PPAG
by Meera Ravindranath (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Subrata Banik, Eric Lai. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69431 ) Change subject: src/drivers/usb: Add support for Bluetooth PPAG ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > What is the PPAG? Could you elaborate here? PPAG is per platform antenna gain. This is a feature used for performance improvement in BT. please refer to the crosbug for a detailed explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/69431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie264edf188532fe6c260275edaa694cf3b3605d3 Gerrit-Change-Number: 69431 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 05:39:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
by Jeff Daly (Code Review) 02 Jan '23

02 Jan '23

Jeff Daly has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60992 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code ...................................................................... Abandoned starting new patch stream rebased to current master branch -- To view, visit https://review.coreboot.org/c/coreboot/+/60992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505b3a7761cb3719697626e1f272d0928fdd29f1 Gerrit-Change-Number: 60992 Gerrit-PatchSet: 12 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
by Jeff Daly (Code Review) 02 Jan '23

02 Jan '23

Jeff Daly has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71611 ) Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code ...................................................................... soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code Use Intel common SoC XHCI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: I24ecd6b1bd0bdf1c3c1e32978a9048a22b294b15 --- M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/xhci.c 3 files changed, 29 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/71611/1 diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 9931fb6..3ae757e 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -148,6 +148,7 @@ PCI_DID_INTEL_ADP_P_XHCI, PCI_DID_INTEL_ADP_S_XHCI, PCI_DID_INTEL_ADP_M_XHCI, + PCI_DID_INTEL_DNV_XHCI, 0 }; diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index dcf9a5f..9e169bb 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -43,6 +43,7 @@ select SOC_INTEL_COMMON_BLOCK_SMBUS select SUPPORT_CPU_UCODE_IN_CBFS select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOC_INTEL_COMMON_BLOCK_XHCI select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c index 2760120..30bb479 100644 --- a/src/soc/intel/denverton_ns/xhci.c +++ b/src/soc/intel/denverton_ns/xhci.c @@ -1,36 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> +#include <device/pci_type.h> +#include <intelblocks/xhci.h> -#include <soc/pci_devs.h> -#include <soc/ramstage.h> +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x4C0 +#define XHCI_USB2_PORT_NUM 4 +#define XHCI_USB3_PORT_NUM 4 -static void usb_xhci_init(struct device *dev) +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev) { - /* USB XHCI configuration is handled by the FSP */ - - printk(BIOS_NOTICE, "pch: %s\n", __func__); - - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + return &usb_info; } - -static struct device_operations usb_xhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_xhci_init, - .enable = pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VID_INTEL, - .device = PCI_DID_INTEL_DNV_XHCI, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/71611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ecd6b1bd0bdf1c3c1e32978a9048a22b294b15 Gerrit-Change-Number: 71611 Gerrit-PatchSet: 1 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM
by Sridhar Siricilla (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Pratikkumar V Prajapati. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71569 ) Change subject: soc/intel/common: Add helper functions for SGX, Key Locker, and PRM ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Gerrit-Change-Number: 71569 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 04:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add API to check Key Locker support
by Sridhar Siricilla (Code Review) 02 Jan '23

02 Jan '23

Attention is currently required from: Subrata Banik, Paul Menzel, Pratikkumar V Prajapati. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71117 ) Change subject: soc/intel/common: Add API to check Key Locker support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Gerrit-Change-Number: 71117 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 02 Jan 2023 03:58:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Move SGX supported API to cpulib
by Sridhar Siricilla (Code Review) 02 Jan '23

02 Jan '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71116 ) Change subject: soc/intel/common: Move SGX supported API to cpulib ...................................................................... soc/intel/common: Move SGX supported API to cpulib Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/sgx.c 4 files changed, 34 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 5332d01..0e78344 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -523,3 +523,13 @@ { return cpu_get_max_turbo_ratio() * CONFIG_CPU_BCLK_MHZ; } + +bool is_sgx_supported(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */ + msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ + return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 7878bf4..6c3aa56 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -211,4 +211,10 @@ */ void set_tme_core_activate(void); +/* + * This function checks if the CPU supports SGX feature. + * Returns true if SGX feature is supported otherwise false. + */ +bool is_sgx_supported(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 3099faf..ac056f7 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -6,11 +6,6 @@ #include <soc/nvs.h> /* - * Check if SGX is supported - */ -int is_sgx_supported(void); - -/* * Configure core PRMRR. * PRMRR needs to configured first on all cores and then * call sgx_configure() for all cores to init SGX. diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 88fe174..31447f9 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -12,16 +12,6 @@ #include <soc/cpu.h> #include <soc/pci_devs.h> -int is_sgx_supported(void) -{ - struct cpuid_result cpuid_regs; - msr_t msr; - - cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */ - msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ - return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); -} - void prmrr_core_configure(void) { msr_t prmrr_base, prmrr_mask; -- To view, visit https://review.coreboot.org/c/coreboot/+/71116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Gerrit-Change-Number: 71116 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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