coreboot-gerrit September 2022

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[M] Change in coreboot[master]: soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Ronak Kanabar, Eric Lai, Werner Zeh. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66706 ) Change subject: soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/66706/comment/b1831631_338a2ec2 PS5, Line 14: nit: change to spaces as the indentation above and below. https://review.coreboot.org/c/coreboot/+/66706/comment/5bc83ed1_1958ea29 PS5, Line 26: https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/CpuMpPei/CpuMpPei.… Please make sure this is captured in archive.org and use the archive.org url in the commit. Especially because you're linking to the master branch this is likely to change in the future. Alternatively, consider whether the URL is really needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/66706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c Gerrit-Change-Number: 66706 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 17:01:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/spd_tools: Rebuild utils when source changes
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67266 ) Change subject: util/spd_tools: Rebuild utils when source changes ...................................................................... util/spd_tools: Rebuild utils when source changes This adds source file dependencies to utilities so that they are rebuilt when the source is changed. Previously, binaries were only built if they did not already exist and never rebuilt to reflect source file changes. BUG=none TEST=verified binaries are rebuilt when source files are touched. Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M util/spd_tools/Makefile 1 file changed, 26 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Reka Norman: Looks good to me, approved Robert Zieba: Looks good to me, but someone else must approve diff --git a/util/spd_tools/Makefile b/util/spd_tools/Makefile index d880672..3aad91c 100644 --- a/util/spd_tools/Makefile +++ b/util/spd_tools/Makefile @@ -3,11 +3,11 @@ all: $(SPD_GEN) $(PART_ID_GEN) -$(SPD_GEN): - go build -o $(SPD_GEN) src/spd_gen/*.go +$(SPD_GEN): src/spd_gen/*.go + go build -o $@ $^ -$(PART_ID_GEN): - go build -o $(PART_ID_GEN) src/part_id_gen/*.go +$(PART_ID_GEN): src/part_id_gen/*.go + go build -o $@ $^ clean: rm -rf bin/ -- To view, visit https://review.coreboot.org/c/coreboot/+/67266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Gerrit-Change-Number: 67266 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/spd_tools: Rebuild utils when source changes
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Caveh Jalali. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67266 ) Change subject: util/spd_tools: Rebuild utils when source changes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69 Gerrit-Change-Number: 67266 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:57:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/spd_tools: Update LP5X support for ADL/RPL/MTL
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Robert Zieba, Caveh Jalali, Selma Bensaid. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67265 ) Change subject: util/spd_tools: Update LP5X support for ADL/RPL/MTL ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > While rex may be the only board currently using these, let's verify that it doesn't matter to AMD ei […] Marking as 'unresolved' so it doesn't accidentally get merged while we check on the AMD side. -- To view, visit https://review.coreboot.org/c/coreboot/+/67265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Gerrit-Change-Number: 67265 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:56:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/spd_tools: Update LP5X support for ADL/RPL/MTL
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Robert Zieba, Caveh Jalali, Selma Bensaid. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67265 ) Change subject: util/spd_tools: Update LP5X support for ADL/RPL/MTL ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: While rex may be the only board currently using these, let's verify that it doesn't matter to AMD either. I know we're looking at mixing lpddr5 & lpddr5x platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/67265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83 Gerrit-Change-Number: 67265 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:52:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/intel/dptf: Add multiple fan support under dptf
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65611 ) Change subject: drivers/intel/dptf: Add multiple fan support under dptf ...................................................................... drivers/intel/dptf: Add multiple fan support under dptf Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/ec/google/chromeec/acpi/emem.asl M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/ec/google/chromeec/ec_dptf_helpers.c M src/ec/google/common/dptf.h M src/include/acpi/acpigen_dptf.h 9 files changed, 226 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index a4b3b09..9ed8d49 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -62,6 +62,8 @@ return "TCHG"; case DPTF_FAN: return "TFN1"; + case DPTF_FAN_2: + return "TFN2"; case DPTF_TEMP_SENSOR_0: return "TSR0"; case DPTF_TEMP_SENSOR_1: @@ -123,7 +125,7 @@ * are used to increase the speed of the fan in order to speed up cooling. */ static void write_active_relationship_table(const struct dptf_active_policy *policies, - int max_count) + int max_count, bool dptf_multifan_support) { char *pkg_count; int i, j; @@ -154,7 +156,11 @@ /* Source, Target, Percent, Fan % for each of _AC0 ... _AC9 */ acpigen_write_package(13); - acpigen_emit_namestring(path_of(DPTF_FAN)); + if (dptf_multifan_support) + acpigen_emit_namestring(path_of(policies[i].source)); + else + acpigen_emit_namestring(path_of(DPTF_FAN)); + acpigen_emit_namestring(path_of(policies[i].target)); acpigen_write_integer(DEFAULT_IF_0(policies[i].weight, DEFAULT_WEIGHT)); @@ -205,9 +211,10 @@ } } -void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count) +void dptf_write_active_policies(const struct dptf_active_policy *policies, + int max_count, bool dptf_multifan_support) { - write_active_relationship_table(policies, max_count); + write_active_relationship_table(policies, max_count, dptf_multifan_support); write_active_cooling_methods(policies, max_count); } @@ -352,7 +359,29 @@ acpigen_pop_len(); /* Scope */ } -void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count) +int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed, + uint16_t noise_level) +{ + /* + * Some _FPS tables do include a last entry where Percent is 0, but Power is + * called out, so this table is finished when both are zero. + */ + if (!percent && !power) + return 1; + + acpigen_write_package(5); + acpigen_write_integer(percent); + acpigen_write_integer(DEFAULT_TRIP_POINT); + acpigen_write_integer(speed); + acpigen_write_integer(noise_level); + acpigen_write_integer(power); + acpigen_pop_len(); /* inner Package */ + + return 0; +} + +void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count, + enum dptf_participant participant) { char *pkg_count; int i; @@ -360,29 +389,48 @@ if (!max_count || !states[0].percent) return; - dptf_write_scope(DPTF_FAN); + dptf_write_scope(participant); /* _FPS - Fan Performance States */ acpigen_write_name("_FPS"); + pkg_count = acpigen_write_package(1); /* 1 for Revision */ acpigen_write_integer(FPS_REVISION); /* revision */ for (i = 0; i < max_count; ++i) { - /* - * Some _FPS tables do include a last entry where Percent is 0, but Power is - * called out, so this table is finished when both are zero. - */ - if (!states[i].percent && !states[i].power) - break; - (*pkg_count)++; - acpigen_write_package(5); - acpigen_write_integer(states[i].percent); - acpigen_write_integer(DEFAULT_TRIP_POINT); - acpigen_write_integer(states[i].speed); - acpigen_write_integer(states[i].noise_level); - acpigen_write_integer(states[i].power); - acpigen_pop_len(); /* inner Package */ + if (dptf_write_fan_perf_fps(states[i].percent, states[i].power, + states[i].speed, states[i].noise_level)) + break; + } + + acpigen_pop_len(); /* Package */ + acpigen_pop_len(); /* Scope */ +} + +void dptf_write_multifan_perf( + const struct dptf_multifan_perf (*states)[DPTF_MAX_FAN_PERF_STATES], + int max_count, enum dptf_participant participant, int fan_num) +{ + char *pkg_count; + int i; + + if (!max_count || !states[fan_num][0].percent) + return; + + dptf_write_scope(participant); + + /* _FPS - Fan Performance States */ + acpigen_write_name("_FPS"); + + pkg_count = acpigen_write_package(1); /* 1 for Revision */ + acpigen_write_integer(FPS_REVISION); /* revision */ + + for (i = 0; i < max_count; ++i) { + (*pkg_count)++; + if (dptf_write_fan_perf_fps(states[fan_num][i].percent, states[fan_num][i].power, + states[fan_num][i].speed, states[fan_num][i].noise_level)) + break; } acpigen_pop_len(); /* Package */ diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 060f196..9bbf11f 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -25,6 +25,8 @@ struct { struct dptf_charger_perf charger_perf[DPTF_MAX_CHARGER_PERF_STATES]; struct dptf_fan_perf fan_perf[DPTF_MAX_FAN_PERF_STATES]; + struct dptf_multifan_perf + multifan_perf[DPTF_MAX_FAN_PARTICIPANTS][DPTF_MAX_FAN_PERF_STATES]; struct dptf_power_limits power_limits; } controls; @@ -44,6 +46,14 @@ */ bool low_speed_notify; } fan; + + /* For multiple TFN fan options */ + struct { + bool fine_grained_control; + uint8_t step_size; + bool low_speed_notify; + } multifan_options[DPTF_MAX_FAN_PARTICIPANTS]; + struct { /* * The amount of hysteresis implemented in circuitry or in the platform @@ -62,6 +72,8 @@ /* Rest of platform Power */ uint32_t prop; + + bool dptf_multifan_support; }; #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */ diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 4504510..0a1fdc3 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -12,6 +12,7 @@ /* Generic DPTF participants have a PTYP field to distinguish them */ enum dptf_generic_participant_type { DPTF_GENERIC_PARTICIPANT_TYPE_TSR = 0x3, + DPTF_GENERIC_PARTICIPANT_TYPE_FAN = 0x4, DPTF_GENERIC_PARTICIPANT_TYPE_TPCH = 0x5, DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER = 0xB, DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY = 0xC, @@ -22,6 +23,7 @@ #define DEFAULT_TPCH_STR "Intel PCH FIVR Participant" #define DEFAULT_POWER_STR "Power Participant" #define DEFAULT_BATTERY_STR "Battery Participant" +#define DEFAULT_FAN_STR "Fan Participant" #define PMC_IPC_COMMAND_FIVR_SIZE 0x8 @@ -51,12 +53,26 @@ return true; /* Check fan as well (its use is implicit in the Active policy) */ - if (participant == DPTF_FAN && config->policies.active[0].target != DPTF_NONE) + if ((participant == DPTF_FAN || participant == DPTF_FAN_2) && + config->policies.active[0].target != DPTF_NONE) return true; return false; } +/* Return the assigned namestring of the FAN participant */ +static const char *fan_namestring_of(enum dptf_participant participant) +{ + switch (participant) { + case DPTF_FAN: + return "TFN1"; + case DPTF_FAN_2: + return "TFN2"; + default: + return ""; + } +} + static const char *dptf_acpi_name(const struct device *dev) { return "DPTF"; @@ -115,15 +131,20 @@ acpigen_pop_len(); /* TCPU Scope */ } -/* \_SB.DPTF.TFN1 */ +/* \_SB.DPTF.TFNx */ static void write_fan(const struct drivers_intel_dptf_config *config, - const struct dptf_platform_info *platform_info) + const struct dptf_platform_info *platform_info, + enum dptf_participant participant) { - acpigen_write_device("TFN1"); + static int fan_uid = 0; + + acpigen_write_device(fan_namestring_of(participant)); acpigen_write_name("_HID"); dptf_write_hid(platform_info->use_eisa_hids, platform_info->fan_hid); - acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(get_STA_value(config, DPTF_FAN)); + acpigen_write_name_integer("_UID", fan_uid++); + acpigen_write_name_string("_STR", DEFAULT_FAN_STR); + acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_FAN); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); acpigen_pop_len(); /* Device */ } @@ -438,6 +459,7 @@ const struct dptf_platform_info *platform_info = get_dptf_platform_info(); const struct drivers_intel_dptf_config *config; struct device *parent; + enum dptf_participant p; /* The CPU device gets an _ADR that matches the ACPI PCI address for 00:04.00 */ parent = dev && dev->bus ? dev->bus->dev : NULL; @@ -450,7 +472,13 @@ config = config_of(dev); write_tcpu(parent, config); write_open_dptf_device(dev, platform_info); - write_fan(config, platform_info); + + if (config->dptf_multifan_support) { + for (p = DPTF_FAN; p <= DPTF_FAN_2; ++p) + write_fan(config, platform_info, p); + } else + write_fan(config, platform_info, DPTF_FAN); + write_oem_variables(config); write_imok(); write_generic_devices(config, platform_info); @@ -476,7 +504,7 @@ config->policies.critical, DPTF_MAX_CRITICAL_POLICIES); dptf_write_active_policies(config->policies.active, - DPTF_MAX_ACTIVE_POLICIES); + DPTF_MAX_ACTIVE_POLICIES, config->dptf_multifan_support); dptf_write_passive_policies(config->policies.passive, DPTF_MAX_PASSIVE_POLICIES); @@ -488,8 +516,20 @@ /* Writes other static tables that are used by DPTF */ static void write_controls(const struct drivers_intel_dptf_config *config) { + enum dptf_participant p; + int fan_num; + dptf_write_charger_perf(config->controls.charger_perf, DPTF_MAX_CHARGER_PERF_STATES); - dptf_write_fan_perf(config->controls.fan_perf, DPTF_MAX_FAN_PERF_STATES); + + /* Write TFN perf states based on the number of fans on the platform */ + if (config->dptf_multifan_support) { + for (p = DPTF_FAN, fan_num = 0; p <= DPTF_FAN_2; ++p, ++fan_num) + dptf_write_multifan_perf(config->controls.multifan_perf, + DPTF_MAX_FAN_PERF_STATES, p, fan_num); + } else + dptf_write_fan_perf(config->controls.fan_perf, DPTF_MAX_FAN_PERF_STATES, + DPTF_FAN); + dptf_write_power_limits(&config->controls.power_limits); } @@ -497,14 +537,25 @@ static void write_options(const struct drivers_intel_dptf_config *config) { enum dptf_participant p; - int i; + int i, fan_num; - /* Fan options */ - dptf_write_scope(DPTF_FAN); - dptf_write_fan_options(config->options.fan.fine_grained_control, - config->options.fan.step_size, - config->options.fan.low_speed_notify); - acpigen_pop_len(); /* Scope */ + /* Configure Fan options based on the number of fans on the platform */ + if (config->dptf_multifan_support) { + for (p = DPTF_FAN, fan_num = 0; p <= DPTF_FAN_2; ++p, ++fan_num) { + dptf_write_scope(p); + dptf_write_fan_options( + config->options.multifan_options[fan_num].fine_grained_control, + config->options.multifan_options[fan_num].step_size, + config->options.multifan_options[fan_num].low_speed_notify); + acpigen_pop_len(); /* Scope */ + } + } else { + dptf_write_scope(DPTF_FAN); + dptf_write_fan_options(config->options.fan.fine_grained_control, + config->options.fan.step_size, + config->options.fan.low_speed_notify); + acpigen_pop_len(); /* Scope */ + } /* TSR options */ for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) { diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 3f9a457..59395f3 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -16,6 +16,7 @@ TIN9, 8, // Temperature 9 Offset (0x10), FAN0, 16, // Fan Speed 0 +FAN1, 16, // Fan Speed 1 Offset (0x24), BTVR, 8, // Battery structure version Offset (0x30), diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index bb03e57..77851d1 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -12,6 +12,7 @@ /* Pointer to PMC Mux connector for each Type-C port */ DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; DEVTREE_CONST struct device *retimer_conn[MAX_TYPEC_PORTS]; + bool ec_multifan_support; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 69b1078..2f69d04 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -276,7 +276,7 @@ ec->ops = &ec_ops; if (CONFIG(DRIVERS_INTEL_DPTF)) - ec_fill_dptf_helpers(ec); + ec_fill_dptf_helpers(ec, dev); fill_ssdt_typec_device(dev); fill_ssdt_ps2_keyboard(dev); diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 1238bcf..c44138f 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -3,7 +3,9 @@ #include <acpi/acpigen.h> #include <acpi/acpigen_dptf.h> #include <ec/google/common/dptf.h> +#include <drivers/intel/dptf/chip.h> +#include "chip.h" /* * The Chrome EC is typically in charge of many system functions, including battery charging and * fan PWM control. This places it in the middle of a DPTF implementation and therefore, many of @@ -22,6 +24,19 @@ EC_FAN_DUTY_AUTO = 0xFF, }; +/* Return the fan number as a string for the FAN participant */ +static const char *fan_num_namestring_of(enum dptf_participant participant) +{ + switch (participant) { + case DPTF_FAN: + return "FAN0"; + case DPTF_FAN_2: + return "FAN1"; + default: + return ""; + } +} + static void write_charger_PPPC(const struct device *ec) { acpigen_write_method_serialized("PPPC", 0); @@ -91,7 +106,7 @@ acpigen_pop_len(); /* Method */ } -static void write_fan_fst(const struct device *ec) +static void write_fan_fst(const struct device *ec, int participant) { /* TFST is a package that is used to store data from FAND */ acpigen_write_name("TFST"); @@ -110,7 +125,7 @@ acpigen_write_integer(1); acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */ acpigen_write_store(); - acpigen_emit_namestring(acpi_device_path_join(ec, "FAN0")); + acpigen_emit_namestring(acpi_device_path_join(ec, fan_num_namestring_of(participant))); acpigen_emit_byte(INDEX_OP); acpigen_emit_namestring("TFST"); acpigen_write_integer(2); @@ -300,11 +315,11 @@ acpigen_pop_len(); /* Scope */ } -static void write_fan_methods(const struct device *ec) +static void write_fan_methods(const struct device *ec, int participant) { - dptf_write_scope(DPTF_FAN); + dptf_write_scope(participant); write_fan_fsl(ec); - write_fan_fst(ec); + write_fan_fst(ec, participant); acpigen_pop_len(); /* Scope */ } @@ -352,14 +367,20 @@ acpigen_pop_len(); /* Scope */ } -void ec_fill_dptf_helpers(const struct device *ec) +void ec_fill_dptf_helpers(const struct device *ec, const struct device *fan_dev) { enum dptf_participant p; int i; + struct ec_google_chromeec_config *config = fan_dev->chip_info; write_dppm_methods(ec); write_charger_methods(ec); - write_fan_methods(ec); + + if (config->ec_multifan_support) { + for (p = DPTF_FAN; p <= DPTF_FAN_2; ++p) + write_fan_methods(ec, p); + } else + write_fan_methods(ec, DPTF_FAN); for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_4; ++p, ++i) write_thermal_methods(ec, p, i); diff --git a/src/ec/google/common/dptf.h b/src/ec/google/common/dptf.h index a59ee0b..b752a83 100644 --- a/src/ec/google/common/dptf.h +++ b/src/ec/google/common/dptf.h @@ -6,6 +6,6 @@ #include <device/device.h> /* Called by google_chromeec_fill_ssdt_generator */ -void ec_fill_dptf_helpers(const struct device *dev); +void ec_fill_dptf_helpers(const struct device *dev, const struct device *fan_dev); #endif /* EC_GOOGLE_COMMON_DPTF_H */ diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 893256e..d9bd5e2 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -14,12 +14,15 @@ #define DPTF_DEVICE_PATH "\\_SB.DPTF" #define TCPU_SCOPE "\\_SB.PCI0" +#define DPTF_MAX_FAN_PARTICIPANTS 2 + /* List of available participants (i.e., they can participate in policies) */ enum dptf_participant { DPTF_NONE, DPTF_CPU, DPTF_CHARGER, DPTF_FAN, + DPTF_FAN_2, DPTF_TEMP_SENSOR_0, DPTF_TEMP_SENSOR_1, DPTF_TEMP_SENSOR_2, @@ -52,6 +55,8 @@ /* Active Policy */ struct dptf_active_policy { + /* The device that can be throttled */ + enum dptf_participant source; /* Device capable of being affected by the fan */ enum dptf_participant target; /* Source's contribution to the Target's cooling capability as a percentage */ @@ -115,6 +120,18 @@ uint16_t power; }; +/* Different levels of fan activity, chosen by active policies */ +struct dptf_multifan_perf { + /* Fan percentage level */ + uint8_t percent; + /* Fan speed, in RPM */ + uint16_t speed; + /* Noise level, in 0.1 dBs */ + uint16_t noise_level; + /* Power in mA */ + uint16_t power; +}; + /* Running Average Power Limits (RAPL) */ struct dptf_power_limit_config { /* Minimum level of power limit, in mW */ @@ -151,7 +168,8 @@ * temperature thresholds are met (_AC0 - _AC9), the fan is driven to corresponding percentage * of full speed. */ -void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count); +void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count, + bool dptf_multifan_support); /* * This function uses the definition of the passive policies to write out _PSV Methods on all @@ -183,7 +201,15 @@ * 4) The corresponding active cooling trip point (from _ART) (typically left as * DPTF_FIELD_UNUSED). */ -void dptf_write_fan_perf(const struct dptf_fan_perf *perf, int max_count); +void dptf_write_fan_perf(const struct dptf_fan_perf *perf, int max_count, + enum dptf_participant participant); + +void dptf_write_multifan_perf( + const struct dptf_multifan_perf (*states)[DPTF_MAX_FAN_PERF_STATES], + int max_count, enum dptf_participant participant, int fan_num); + +int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed, + uint16_t noise_level); /* * This function writes out a PPCC table, which indicates power ranges that different Intel -- To view, visit https://review.coreboot.org/c/coreboot/+/65611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Gerrit-Change-Number: 65611 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/google/brya/var/ghost: Delete variant
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67299 ) Change subject: mb/google/brya/var/ghost: Delete variant ...................................................................... mb/google/brya/var/ghost: Delete variant This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth(a)chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/ghost/Makefile.inc D src/mainboard/google/brya/variants/ghost/gpio.c D src/mainboard/google/brya/variants/ghost/include/variant/ec.h D src/mainboard/google/brya/variants/ghost/include/variant/gpio.h D src/mainboard/google/brya/variants/ghost/memory.c D src/mainboard/google/brya/variants/ghost/memory/Makefile.inc D src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt D src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt D src/mainboard/google/brya/variants/ghost/overridetree.cb 11 files changed, 20 insertions(+), 923 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index eebb720..d49be3f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -60,17 +60,6 @@ select SOC_INTEL_ALDERLAKE_PCH_P select TPM_GOOGLE_CR50 -config BOARD_GOOGLE_BASEBOARD_GHOST - def_bool n - select BOARD_GOOGLE_BASEBOARD_BRYA if BOARD_GOOGLE_GHOST4ADL - select BOARD_GOOGLE_BASEBOARD_SKOLAS if !BOARD_GOOGLE_GHOST4ADL - select DRIVERS_I2C_CS42L42 - select DRIVERS_I2C_MAX98396 - select DRIVERS_INTEL_MIPI_CAMERA - select DRIVERS_NXP_UWB_SR1XX - select GBB_FLAG_DISABLE_LID_SHUTDOWN if VBOOT - select SOC_INTEL_COMMON_BLOCK_IPU - config BOARD_GOOGLE_BASEBOARD_NISSA def_bool n select BOARD_GOOGLE_BRYA_COMMON @@ -127,7 +116,6 @@ default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS default 0x3 if BOARD_GOOGLE_PRIMUS4ES - default 0x1 if BOARD_GOOGLE_BASEBOARD_GHOST default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x1 if BOARD_GOOGLE_REDRIX @@ -193,9 +181,6 @@ default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES - default "Ghost" if BOARD_GOOGLE_GHOST - default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL - default "Ghost4ES" if BOARD_GOOGLE_GHOST4ES default "Gimble" if BOARD_GOOGLE_GIMBLE default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX @@ -234,7 +219,6 @@ default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS default "primus4es" if BOARD_GOOGLE_PRIMUS4ES - default "ghost" if BOARD_GOOGLE_BASEBOARD_GHOST default "gimble" if BOARD_GOOGLE_GIMBLE default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 8d64ce8..a85ec80 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -57,19 +57,6 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9755 -config BOARD_GOOGLE_GHOST - bool "-> Ghost" - select BOARD_GOOGLE_BASEBOARD_GHOST - -config BOARD_GOOGLE_GHOST4ADL - bool "-> Ghost4ADL" - select BOARD_GOOGLE_BASEBOARD_GHOST - select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP - -config BOARD_GOOGLE_GHOST4ES - bool "-> Ghost4ES" - select BOARD_GOOGLE_BASEBOARD_GHOST - config BOARD_GOOGLE_GIMBLE bool "-> Gimble" select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/ghost/Makefile.inc b/src/mainboard/google/brya/variants/ghost/Makefile.inc deleted file mode 100644 index 073317f..0000000 --- a/src/mainboard/google/brya/variants/ghost/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -romstage-y += memory.c - -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/ghost/gpio.c b/src/mainboard/google/brya/variants/ghost/gpio.c deleted file mode 100644 index 1240803..0000000 --- a/src/mainboard/google/brya/variants/ghost/gpio.c +++ /dev/null @@ -1,423 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* This header block is used to supply information to arbitrage, a - * google-internal tool. Updating it incorrectly will lead to issues, - * so please don't update it unless a change is specifically required. - * BaseID: EEF9BFAE6CA0D797 - * Overrides: 5e80bcfaea530ebe7e64b520ed0727daeb73a187 - */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> -#include <soc/gpio.h> -#include <vendorcode/google/chromeos/chromeos.h> - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* GPD0 : [NF1: BATLOW#] ==> BATLOW_L */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1 : [NF1: ACPRESENT] ==> ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 : [NF1: LAN_WAKE#] ==> EC_PCH_WAKE_ODL */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3 : [NF1: PWRBTN#] ==> EC_PCH_PWR_BTN_ODL */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4 : [NF1: SLP_S3#] ==> SLP_S3_R_L */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5 : [NF1: SLP_S4#] ==> SLP_S4_L */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6 : [NF1: SLP_A#] ==> SLP_A_L_CAP_SITE */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7 : GPD7_STRAP ==> Component NC */ - PAD_NC(GPD7, NONE), - /* GPD8 : [NF1: SUSCLK] ==> PCH_SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9 : [NF1: SLP_WLAN#] ==> SLP_WLAN_L_CAP_SITE */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10 : [NF1: SLP_S5#] ==> SLP_S5_L */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11 : No heuristic was found useful */ - PAD_NC(GPD11, NONE), - /* GPP_A0 : GPP_A0 ==> ESPI_PCH_D0_EC_R configured on reset, do not touch */ - /* GPP_A1 : GPP_A1 ==> ESPI_PCH_D1_EC_R configured on reset, do not touch */ - /* GPP_A2 : GPP_A2 ==> ESPI_PCH_D2_EC_R configured on reset, do not touch */ - /* GPP_A3 : GPP_A3 ==> ESPI_PCH_D3_EC_R configured on reset, do not touch */ - /* GPP_A4 : GPP_A4 ==> ESPI_PCH_CS_EC_R_L configured on reset, do not touch */ - /* GPP_A5 : GPP_A5 ==> ESPI_ALERT0 configured on reset, do not touch */ - /* GPP_A6 : GPP_A6 ==> ESPI_ALERT1 configured on reset, do not touch */ - /* GPP_A7 : PCH_UWB_WAKE */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), - /* GPP_A8 : HP_RST_ODL */ - PAD_CFG_GPO(GPP_A8, 1, PLTRST), - /* GPP_A9 : GPP_A9 ==> ESPI_PCH_CLK_R configured on reset, do not touch */ - /* GPP_A10 : GPP_A10 ==> ESPI_PCH_RST_EC_L configured on reset, do not touch */ - /* GPP_A11 : [NF6: USB_C_GPP_A11] ==> EN_SPKR_PA */ - PAD_CFG_GPO(GPP_A11, 1, DEEP), - /* GPP_A12 : EN_PP1800_UWB */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), - /* GPP_A13 : [NF6: USB_C_GPP_A13] ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> USB_C1_OC_ODL */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* GPP_A15 : net NC is not present in the given design */ - PAD_NC(GPP_A15, NONE), - /* GPP_A16 : net NC is not present in the given design */ - PAD_NC(GPP_A16, NONE), - /* GPP_A17 : EN_PP16000H */ - PAD_CFG_GPO(GPP_A17, 1, DEEP), - /* GPP_A18 : net NC is not present in the given design */ - PAD_NC(GPP_A18, NONE), - /* GPP_A19 : No heuristic was found useful */ - PAD_NC(GPP_A19, NONE), - /* GPP_A20 : net NC is not present in the given design */ - PAD_NC(GPP_A20, NONE), - /* GPP_A21 : net NC is not present in the given design */ - PAD_NC(GPP_A21, NONE), - /* GPP_A22 : net NC is not present in the given design */ - PAD_NC(GPP_A22, NONE), - /* GPP_A23 : [NF1: ESPI_CS1# NF6: USB_C_GPP_A23] ==> AUD_HP_INT_L */ - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), - /* GPP_B0 : [NF1: CORE_VID0 NF6: USB_C_GPP_B0] ==> SOC_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* GPP_B1 : [NF1: CORE_VID1 NF6: USB_C_GPP_B1] ==> SOC_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> GPP_B2 */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF6), - /* GPP_B3 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), - /* GPP_B4 : [NF1: PROC_GP3 NF4: ISH_GP5B NF6: USB_C_GPP_B4] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), - /* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), - /* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> PCH_I2C_TCHSCR_R_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> PCH_I2C_TCHSCR_R_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> EN_PP3300_WLAN */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ - PAD_NC(GPP_B14, NONE), - /* GPP_B15 : net NC is not present in the given design */ - PAD_NC(GPP_B15, NONE), - /* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> PCH_I2C_TCHPAD_R_SDA */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), - /* GPP_B17 : [NF2: I2C5_SCL NF4: ISH_I2C2_SCL NF6: USB_C_GPP_B17] ==> PCH_I2C_TCHPAD_R_SCL */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), - /* GPP_B18 : GPP_B18_STRAP ==> Component NC */ - PAD_NC(GPP_B18, NONE), - /* GPP_B23 : PCHHOT_ODL_STRAP ==> Component NC */ - PAD_NC(GPP_B23, NONE), - /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> EN_TCHSCR */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - /* GPP_C2 : GPP_C2_STRAP ==> Component NC */ - PAD_NC(GPP_C2, NONE), - /* GPP_C3 : net NC is not present in the given design */ - PAD_NC(GPP_C3, NONE), - /* GPP_C4 : [NF1: SML0DATA NF6: USB_C_GPP_C4] ==> EN_UCAM_PWR */ - PAD_CFG_GPO(GPP_C4, 0, DEEP), - /* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> GPP_C5_BOOT_STRAP0 */ - PAD_CFG_NF(GPP_C5, NONE, DEEP, NF6), - /* GPP_C6 : No heuristic was found useful */ - PAD_NC(GPP_C6, NONE), - /* GPP_C7 : [NF1: SML1DATA NF6: USB_C_GPP_C7] ==> TCHSCR_INT */ - PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), - /* GPP_D0 : PCH_FP_BOOT0 ==> Component NC */ - PAD_NC(GPP_D0, NONE), - /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), - /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), - /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> BT_DISABLE_L */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* GPP_D5 : net NC is not present in the given design */ - PAD_NC(GPP_D5, NONE), - /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - /* GPP_D7 : net NC is not present in the given design */ - PAD_NC(GPP_D7, NONE), - /* GPP_D8 : net NC is not present in the given design */ - PAD_NC(GPP_D8, NONE), - /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> USB_C0_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), - /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C0_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), - /* GPP_D11 : net NC is not present in the given design */ - PAD_NC(GPP_D11, NONE), - /* GPP_D12 : GPP_D12_STRAP ==> Component NC */ - PAD_NC(GPP_D12, NONE), - /* GPP_D13 : No heuristic was found useful */ - PAD_NC(GPP_D13, NONE), - /* GPP_D14 : No heuristic was found useful */ - PAD_NC(GPP_D14, NONE), - /* GPP_D15 : net NC is not present in the given design */ - PAD_NC(GPP_D15, NONE), - /* GPP_D16 : net NC is not present in the given design */ - PAD_NC(GPP_D16, NONE), - /* GPP_D17 : net NC is not present in the given design */ - PAD_NC(GPP_D17, NONE), - /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, NONE), - /* GPP_D19 : No heuristic was found useful */ - PAD_NC(GPP_D19, NONE), - /* GPP_E0 : net NC is not present in the given design */ - PAD_NC(GPP_E0, NONE), - /* GPP_E1 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), - /* GPP_E2 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* GPP_E3 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E3, NONE, DEEP), - /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_E4, 1, DEEP), - /* GPP_E5 : net NC is not present in the given design */ - PAD_NC(GPP_E5, NONE), - /* GPP_E6 : GPP_E6_STRAP ==> Component NC */ - PAD_NC(GPP_E6, NONE), - /* GPP_E7 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), - /* GPP_E8 : [NF6: USB_C_GPP_E8] ==> WIFI_DISABLE_L */ - PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 : [NF2: THC0_SPI1_CS# NF6: USB_C_GPP_E10 NF7: GSPI0_CS0#] ==> PCH_GSPI0_CS_L_UWB */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), - /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> PCH_GSPI0_CLK_UWB_R */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), - /* GPP_E12 : [NF2: THC0_SPI1_IO1 NF5: I2C0A_SDA NF6: USB_C_GPP_E12 NF7: GSPI0_MISO] ==> PCH_GSPI0_DI_UWB_DO */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), - /* GPP_E13 : [NF2: THC0_SPI1_IO0 NF5: I2C0A_SCL NF6: USB_C_GPP_E13 NF7: GSPI0_MOSI] ==> PCH_GSPI0_DO_UWB_DI_R */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), - /* GPP_E14 : [NF1: DDSP_HPDA NF2: DISP_MISCA NF6: USB_C_GPP_E14] ==> SOC_EDP_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* GPP_E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* GPP_E16 : net NC is not present in the given design */ - PAD_NC(GPP_E16, NONE), - /* GPP_E17 : net NC is not present in the given design */ - PAD_NC(GPP_E17, NONE), - /* GPP_E18 : net NC is not present in the given design */ - PAD_NC(GPP_E18, NONE), - /* GPP_E19 : GPP_E19_STRAP ==> Component NC */ - PAD_NC(GPP_E19, NONE), - /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> USB_C1_LSX_TX */ - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), - /* GPP_E21 : [NF1: DDP2_CTRLDATA NF4: TBT_LSX1_RXD NF5: BSSB_LS1_TX NF6: USB_C_GPP_E21] ==> USB_C1_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), - /* GPP_E22 : DNX_STRAP ==> Component NC */ - PAD_NC(GPP_E22, NONE), - /* GPP_E23 : net NC is not present in the given design */ - PAD_NC(GPP_E23, NONE), - /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), - /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ - PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), - /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ - PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), - /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ - PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), - /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* GPP_F5 : [NF2: MODEM_CLKREQ NF3: CRF_XTAL_CLKREQ NF6: USB_C_GPP_F5] ==> CNV_CLKREQ0 */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), - /* GPP_F6 : net NC is not present in the given design */ - PAD_NC(GPP_F6, NONE), - /* GPP_F7 : GPP_F7_STRAP ==> Component NC */ - PAD_NC(GPP_F7, NONE), - /* GPP_F9 : [] ==> SLP_S0_GATE_R */ - PAD_CFG_GPO(GPP_F9, 1, DEEP), - /* GPP_F10 : GPP_F10_STRAP ==> Component NC */ - PAD_NC(GPP_F10, NONE), - /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), - /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), - /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISO NF5: I2C1A_SDA NF6: USB_C_GPP_F13] ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), - /* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> TCHPAD_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), - /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FPMCU_PCH_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PLTRST, LEVEL, INVERT), - /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI_CS0# NF6: USB_C_GPP_F16] ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), - /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* GPP_F19 : [NF1: SRCCLKREQ6# NF6: USB_C_GPP_F19] ==> GPP_F19 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF6), - /* GPP_F20 : [] ==> UCAM_RST_L */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* GPP_F21 : UWB_PCH_INT */ - PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, LEVEL), - /* GPP_F22 : No heuristic was found useful */ - PAD_NC(GPP_F22, NONE), - /* GPP_F23 : No heuristic was found useful */ - PAD_NC(GPP_F23, NONE), - /* GPP_H0 : [NF6: USB_C_GPP_H0] ==> GPP_H0_BOOT_STRAP1 */ - PAD_CFG_NF(GPP_H0, NONE, DEEP, NF6), - /* GPP_H1 : [NF6: USB_C_GPP_H1] ==> GPP_H1_BOOT_STRAP2 */ - PAD_CFG_NF(GPP_H1, NONE, DEEP, NF6), - /* GPP_H2 : [NF6: USB_C_GPP_H2] ==> GPP_H2_BOOT_STRAP3 */ - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF6), - /* GPP_H3 : net NC is not present in the given design */ - PAD_NC(GPP_H3, NONE), - /* GPP_H4 : [NF1: I2C0_SDA NF6: USB_C_GPP_H4] ==> PCH_I2C_AUD_R_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* GPP_H5 : [NF1: I2C0_SCL NF6: USB_C_GPP_H5] ==> PCH_I2C_AUD_R_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* GPP_H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* GPP_H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* GPP_H8 : net NC is not present in the given design */ - PAD_NC(GPP_H8, NONE), - /* GPP_H9 : net NC is not present in the given design */ - PAD_NC(GPP_H9, NONE), - /* GPP_H10 : [NF2: UART0_RXD NF3: M2_SKT2_CFG0 NF6: USB_C_GPP_H10] ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* GPP_H11 : [NF2: UART0_TXD NF3: M2_SKT2_CFG1 NF6: USB_C_GPP_H11] ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* GPP_H12 : net NC is not present in the given design */ - PAD_NC(GPP_H12, NONE), - /* GPP_H13 : net NC is not present in the given design */ - PAD_NC(GPP_H13, NONE), - /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, NONE), - /* GPP_H17 : net NC is not present in the given design */ - PAD_NC(GPP_H17, NONE), - /* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */ - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), - /* GPP_H19 : net NC is not present in the given design */ - PAD_NC(GPP_H19, NONE), - /* GPP_H20 : net NC is not present in the given design */ - PAD_NC(GPP_H20, NONE), - /* GPP_H21 : [NF1: IMGCLKOUT2 NF6: USB_C_GPP_H21] ==> UCAM_MCLK_R */ - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22 : net NC is not present in the given design */ - PAD_NC(GPP_H22, NONE), - /* GPP_H23 : net NC is not present in the given design */ - PAD_NC(GPP_H23, NONE), - /* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> I2S_HP_SCLK_R */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* GPP_R1 : [NF1: HDA_SYNC NF2: I2S0_SFRM NF3: DMIC_CLK_B1] ==> I2S_HP_SFRM_R */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> I2S_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), - /* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* GPP_R4 : [NF1: HDA_RST# NF2: I2S2_SCLK NF3: DMIC_CLK_A0] ==> DMIC_CLK0_R */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), - /* GPP_R5 : [NF1: HDA_SDI1 NF2: I2S2_SFRM NF3: DMIC_DATA0] ==> DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), - /* GPP_R6 : [NF2: I2S2_TXD NF3: DMIC_CLK_A1] ==> DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), - /* GPP_R7 : [NF2: I2S2_RXD NF3: DMIC_DATA1] ==> DMIC_DATA1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), - /* GPP_S0 : [NF1: SNDW0_CLK NF4: I2S1_SCLK] ==> I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), - /* GPP_S1 : [NF1: SNDW0_DATA NF4: I2S1_SFRM] ==> I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), - /* GPP_S2 : [NF1: SNDW1_CLK NF2: DMIC_CKLA0 NF4: I2S1_TXD] ==> I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), - /* GPP_S3 : [NF1: SNDW1_DATA NF2: DMIC_DATA0 NF4: I2S1_RXD] ==> I2S_PCH_RX_SPKR_TX */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), - /* GPP_S4 : net NC is not present in the given design */ - PAD_NC(GPP_S4, NONE), - /* GPP_S5 : net NC is not present in the given design */ - PAD_NC(GPP_S5, NONE), - /* GPP_S6 : net NC is not present in the given design */ - PAD_NC(GPP_S6, NONE), - /* GPP_S7 : net NC is not present in the given design */ - PAD_NC(GPP_S7, NONE), - /* GPP_T2 : No heuristic was found useful */ - PAD_NC(GPP_T2, NONE), - /* GPP_T3 : No heuristic was found useful */ - PAD_NC(GPP_T3, NONE), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D3, 1, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - - /* TPM is on I2C port 1 */ - /* H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TPM_R_SDA */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TPM_R_SCL */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - - /* Mem straps */ - /* B3 : PROC_GP2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_B3, NONE, DEEP), - /* E3 : PROC_GP0 ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E3, NONE, DEEP), - /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), - /* E7 : PROC_GP1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E7, NONE, DEEP), -}; - -static const struct pad_config romstage_gpio_table[] = { - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), -}; - -const struct pad_config *variant_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(gpio_table); - return gpio_table; -} - -const struct pad_config *variant_gpio_override_table(size_t *num) -{ - *num = 0; - return NULL; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -const struct pad_config *variant_romstage_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} diff --git a/src/mainboard/google/brya/variants/ghost/include/variant/ec.h b/src/mainboard/google/brya/variants/ghost/include/variant/ec.h deleted file mode 100644 index 7a2a6ff..0000000 --- a/src/mainboard/google/brya/variants/ghost/include/variant/ec.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __VARIANT_EC_H__ -#define __VARIANT_EC_H__ - -#include <baseboard/ec.h> - -#endif diff --git a/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h b/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h deleted file mode 100644 index c4fe342..0000000 --- a/src/mainboard/google/brya/variants/ghost/include/variant/gpio.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> - -#endif diff --git a/src/mainboard/google/brya/variants/ghost/memory.c b/src/mainboard/google/brya/variants/ghost/memory.c deleted file mode 100644 index 7bf0072..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory.c +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <gpio.h> -#include <soc/romstage.h> - -static const struct mb_cfg baseboard_memcfg = { - .type = MEM_TYPE_LP5X, - - /* - * DQ byte map - * - * To calculate from schematics, reference - * ADL_LP5_DqMapCpu2Dram sheet of this spreadsheet: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .lpx_dq_map = { - .ddr0 = { - .dq0 = { 5, 0, 4, 1, 2, 6, 7, 3 }, - .dq1 = { 11, 15, 13, 12, 10, 14, 8, 9 }, - }, - .ddr1 = { - .dq0 = { 9, 10, 11, 8, 13, 14, 12, 15 }, - .dq1 = { 0, 2, 1, 3, 7, 5, 6, 4 }, - }, - .ddr2 = { - .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0 }, - .dq1 = { 12, 14, 15, 13, 11, 10, 8, 9 }, - }, - .ddr3 = { - .dq0 = { 15, 14, 12, 13, 10, 9, 11, 8 }, - .dq1 = { 7, 6, 4, 5, 0, 3, 1, 2 }, - }, - .ddr4 = { - .dq0 = { 15, 14, 12, 13, 10, 9, 8, 11 }, - .dq1 = { 1, 3, 0, 2, 5, 6, 7, 4 }, - }, - .ddr5 = { - .dq0 = { 9, 10, 11, 8, 12, 15, 13, 14 }, - .dq1 = { 3, 7, 2, 6, 0, 4, 5, 1 }, - }, - .ddr6 = { - .dq0 = { 11, 8, 10, 9, 12, 14, 13, 15 }, - .dq1 = { 0, 7, 1, 2, 6, 4, 3, 5 }, - }, - .ddr7 = { - .dq0 = { 1, 2, 3, 0, 7, 5, 6, 4 }, - .dq1 = { 15, 14, 11, 13, 8, 9, 12, 10 }, - }, - }, - - /* - * DQS CPU<>DRAM map - * - * To calculate from schematics, reference - * MTL_RPL_ADL_LP5_DqsMapCpu2Dram sheet of this spreadsheet: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .lpx_dqs_map = { - .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, - .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, - .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, - }, - - /* Enable Early Command Training */ - .ect = true, - - .UserBd = BOARD_TYPE_MOBILE, - - .lp5x_config = { - /* - * CA and CS signals are in descending order. - * - * Reference the MTL_RPL_ADL_LP5_CccConfig sheet of - * this spreadsheet for instructions: - * https://cdrdv2.intel.com/v1/dl/getContent/573387 - */ - .ccc_config = 0xff, - }, -}; - -const struct mb_cfg *variant_memory_params(void) -{ - return &baseboard_memcfg; -} - -int variant_memory_sku(void) -{ - /* - * Memory configuration board straps - * - MEM_STRAP_0: GPP_E3 - * - MEM_STRAP_1: GPP_E2 - * - MEM_STRAP_2: GPP_E1 - * - MEM_STRAP_3: GPP_E7 - * - * MEM_STRAP_0 is LSB, and MEM_STRAP_3 is MSB. - */ - gpio_t spd_gpios[] = { - GPP_E3, - GPP_E2, - GPP_E1, - GPP_E7, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - -bool variant_is_half_populated(void) -{ - /* GPIO_MEM_CH_SEL is GPP_B3 */ - return gpio_get(GPP_B3); -} diff --git a/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc b/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc deleted file mode 100644 index 80729d7..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/Makefile.inc +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E, MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 -SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN -SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt deleted file mode 100644 index 026ac07..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/dram_id.generated.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/ghost/memory src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -H9JCNNNBK3MLYR-N6E 0 (0000) -H58G56AK6BX069 1 (0001) -MT62F512M32D2DR-031 WT:B 0 (0000) -K3LKLKL0EM-MGCN 2 (0010) -MT62F1G32D2DS-026 WT:B 3 (0011) diff --git a/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt deleted file mode 100644 index 6f4f2a7..0000000 --- a/src/mainboard/google/brya/variants/ghost/memory/mem_parts_used.txt +++ /dev/null @@ -1,16 +0,0 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name -H9JCNNNBK3MLYR-N6E -H58G56AK6BX069 -MT62F512M32D2DR-031 WT:B -K3LKLKL0EM-MGCN -MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/ghost/overridetree.cb b/src/mainboard/google/brya/variants/ghost/overridetree.cb deleted file mode 100644 index 95c1b4d..0000000 --- a/src/mainboard/google/brya/variants/ghost/overridetree.cb +++ /dev/null @@ -1,294 +0,0 @@ -chip soc/intel/alderlake - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | FPMCU | - #| I2C0 | Audio | - #| I2C1 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C2 | Misc (Cam, Display, LED) | - #| I2C3 | Touchscreen | - #| I2C4 | NC | - #| I2C5 | Touchpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - - # I2C Port Config - register "serial_io_i2c_mode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexI2C7] = PchSerialIoDisabled, - }" - - # GSPI config - register "serial_io_gspi_mode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoPci, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 - register "usb2_ports[2]" = "USB2_PORT_EMPTY" - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # DCI port - register "usb2_ports[5]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - - register "usb3_ports[0]" = "USB3_PORT_EMPTY" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port - register "usb3_ports[3]" = "USB3_PORT_EMPTY" - - register "tcss_ports[0]" = "TCSS_PORT_EMPTY" - register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # TypeC C1 - register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" # TypeC C0 - - device domain 0 on - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end - device ref pcie_rp6 off end - device ref pcie_rp7 off end - device ref pcie_rp8 off end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port2 as dfp[0].typec_port - device generic 0 on end - end - end - device ref tcss_dma1 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on end - end - end - device ref i2c0 on - chip drivers/i2c/cs42l42 - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "ts_inv" = "true" - register "ts_dbnc_rise" = "RISE_DEB_1000_MS" - register "ts_dbnc_fall" = "FALL_DEB_0_MS" - register "btn_det_init_dbnce" = "100" - register "btn_det_event_dbnce" = "10" - register "bias_lvls[0]" = "15" - register "bias_lvls[1]" = "8" - register "bias_lvls[2]" = "4" - register "bias_lvls[3]" = "1" - register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" - register "hs_bias_sense_disable" = "true" - device i2c 48 on end - end - chip drivers/i2c/max98396 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" - register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 3c on end - end - chip drivers/i2c/max98396 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" - register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 3d on end - end - end - device ref i2c1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end - device ref i2c2 on - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" - register "remote_name" = ""IPU0"" - register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" - - register "has_power_resource" = "1" - - # Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - - register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" # EN_UCAM_PWR - register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" # UCAM_RST_L - - # ON - register "on_seq.ops_cnt" = "4" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - - # OFF - register "off_seq.ops_cnt" = "3" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - - device i2c 36 on end - end - chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" - register "acpi_uid" = "1" - register "acpi_name" = ""NVM0"" - register "chip_name" = ""M24C64X"" - register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" - - register "nvm_size" = "0x2000" - register "nvm_pagesize" = "1" - register "nvm_readonly" = "1" - register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c64"" - device i2c 50 on end - end - end - device ref ipu on - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used - register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" - register "cio2_prt[0]" = "1" - device generic 0 on end - end - end - device ref gspi0 on - chip drivers/nxp/uwb - register "name" = ""UWB0"" - register "desc" = ""NXP UWB Module"" - register "speed" = "1000000" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)" - register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)" - register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)" - device spi 0 on end - end - end - device ref gspi1 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" - device spi 0 on end - end # FPMCU - end - device ref pch_espi on - chip ec/google/chromeec - # Replicate Brya, except we have 2 ports instead of 3. - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] - device pnp 0c09.0 on end - end - end - device ref pmc hidden - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/conn - # C0: Left side (on DB) - use usb2_port1 as usb2_port - use tcss_usb3_port3 as usb3_port - device generic 0 alias conn0 on end - end - chip drivers/intel/pmc_mux/conn - # C1: Right side (on MLB) - use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port - device generic 1 alias conn1 on end - end - end - end - end - device ref tcss_xhci on - chip drivers/usb/acpi - device ref tcss_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C0 is on the LEFT panel, LEFT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end - end - end - end - end - device ref xhci on - chip drivers/usb/acpi - device ref xhci_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (DB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C0 is on the LEFT panel, LEFT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear) - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port2 on end - end - end - end - end - end -end -- To view, visit https://review.coreboot.org/c/coreboot/+/67299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Gerrit-Change-Number: 67299 Gerrit-PatchSet: 2 Gerrit-Owner: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: util/lint: Add lint tests to make sure they fail correctly
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64974 ) Change subject: util/lint: Add lint tests to make sure they fail correctly ...................................................................... util/lint: Add lint tests to make sure they fail correctly Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Signed-off-by: Martin Roth <martin(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/lint/check_lint_tests 1 file changed, 156 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/util/lint/check_lint_tests b/util/lint/check_lint_tests index 6c050ee..24c75c9 100755 --- a/util/lint/check_lint_tests +++ b/util/lint/check_lint_tests @@ -1,48 +1,157 @@ -#!/usr/bin/env bash +#!/usr/bin/env sh + +rootdir=${PWD} # test to make sure the lint tests fail SPACE=' ' UNDERSCORE='_' -#lint-stable-000-license-headers -TESTFILE000a=src/arch/x86/thread.c -TESTFILE000b=src/arch/riscv/misc.c -sed -i.bak 's/^[[:space:]]\*[[:space:]].*//' ${TESTFILE000a} -sed -i.bak 's/^[[:space:]]\*[[:space:]]but WITHOUT ANY WARRANTY;//' ${TESTFILE000b} +# lint-stable-000-license-headers +TESTFILE000a="${rootdir}/src/arch/x86/thread.c" +TESTFILE000b="${rootdir}/src/arch/riscv/misc.c" +TESTFILE000c="${rootdir}/src/lib/hardwaremain.c" -#lint-stable-003-whitespace -TESTFILE003=src/acpi/sata.c -sed -i.bak 's/^$/ /' ${TESTFILE003} +# lint-stable-003-whitespace +TESTFILE003="${rootdir}/src/acpi/sata.c" +# lint-stable-004-style-labels +TESTFILE004="${rootdir}/src/soc/nvidia/tegra124/spi.c" +# lint-stable-005-board-status +TESTFILE005a="${rootdir}/src/mainboard/google/storm/board_info.txt" +# lint-stable-006-board-name +TESTFILE006="${rootdir}/src/mainboard/ibase/mb899/Kconfig.name" +# lint-stable-008-kconfig +TESTFILE008="${rootdir}/src/lib/Kconfig" +# lint-stable-009-old-licenses +TESTFILE009="${rootdir}/src/superio/common/conf_mode.c" +# lint-stable-010-asm-syntax +TESTFILE010="${rootdir}/src/arch/x86/assembly_entry.S" +# lint-stable-012-executable-bit +TESTFILE012="${rootdir}/src/lib/libgcc.c" +# lint-stable-013-site-local +TESTFILE013="$(mktemp --tmpdir=site-local)" +# lint-stable-016-non-ascii +TESTFILE016="${rootdir}/src/lib/halt.c" +# lint-stable-017-configs +TESTFILE017="${rootdir}/configs/testconfig" +# lint-stable-018-symlinks +TESTFILE018="${rootdir}/src/testKconfig" +# lint-stable-019-header-files +TESTFILE019=${rootdir}/test +# lint-stable-021-coreboot-lowercase +TESTFILE021=${rootdir}/test +# lint-stable-022-clang-format +TESTFILE022=${rootdir}/test +# lint-stable-023-filenames +TESTFILE023=${rootdir}/test +# lint-stable-024-kconfig-no-subsystem +TESTFILE024=${rootdir}/test +# lint-stable-026-line-endings +TESTFILE026=${rootdir}/test +# lint-stable-027-maintainers-syntax +TESTFILE027="${rootdir}/MAINTAINERS" -#lint-stable-004-style-labels -TESTFILE004=src/soc/nvidia/tegra124/spi.c -sed -i.bak 's/^done:/ done:/' ${TESTFILE004} +if [ "$1" = "--reset" ]; then + echo "Resetting testfiles" + echo "lint-stable-000-license-headers" + git checkout "${TESTFILE000a}" "${TESTFILE000b}" "${TESTFILE000c}" + echo "lint-stable-003-whitespace" + git checkout "${TESTFILE003}" + echo "lint-stable-004-style-labels" + git checkout "${TESTFILE004}" + echo "lint-stable-005-board-status" + git checkout "${TESTFILE005a}" + echo "lint-stable-006-board-name" + git checkout "${TESTFILE006}" + echo "lint-stable-008-kconfig" + git checkout "${TESTFILE008}" + echo "lint-stable-009-old-licenses" + git checkout "${TESTFILE009}" + echo "lint-stable-010-asm-syntax" + git checkout "${TESTFILE010}" + echo "lint-stable-012-executable-bit" + git checkout "${TESTFILE012}" + echo "lint-stable-013-site-local" + git reset "${TESTFILE013}"; rm -vf "${TESTFILE013}" + echo "lint-stable-016-non-ascii" + git checkout "${TESTFILE016}" + echo "lint-stable-017-configs" + rm -vf "${TESTFILE017}" + echo "lint-stable-018-symlinks" + rm -vf "${TESTFILE018}" + echo "lint-stable-019-header-files" + git checkout "${TESTFILE019}" + echo "lint-stable-021-coreboot-lowercase" + git checkout "${TESTFILE021}" + echo "lint-stable-022-clang-format" + git checkout "${TESTFILE022}" + echo "lint-stable-023-filenames" + git checkout "${TESTFILE023}" + echo "lint-stable-024-kconfig-no-subsystem" + git checkout "${TESTFILE024}" + echo "lint-stable-026-line-endings" + git checkout "${TESTFILE026}" -#lint-stable-005-board-status -TESTFILE005a=src/mainboard/google/storm/board_info.txt -sed -i.bak 's/^Category:.*/Category: lint/' ${TESTFILE005a} + echo "lint-stable-027-maintainers-syntax" + git checkout "${TESTFILE027}" -#lint-stable-006-board-name -TESTFILE006=src/mainboard/ibase/mb899/Kconfig.name -rm -f ${TESTFILE006} -#lint-stable-008-kconfig +else + echo "Modifying files for linter testing" -#lint-stable-009-old-licenses -TESTFILE009=src/superio/common/conf_mode.c -sed -i "s/for more details./for more details.\n \* You${SPACE}should${SPACE}have received a copy of the GNU General Public License\n \* along with this program; if not, write to the Free Software\n \* Foundation, Inc./" ${TESTFILE009} -git add ${TESTFILE009} + echo "lint-stable-000-license-headers" + sed -i.bak 's|^/\*.*||' "${TESTFILE000a}" + #sed -i.bak 's|^.*]SPDX-License-Identifier.*||' "${TESTFILE000b}" + #sed -i.bak 's|^.*]GPL-2.0-only|GPL-2.0|' "${TESTFILE000c}" -#lint-stable-010-asm-syntax -TESTFILE010=src/arch/x86/bootblock_crt0.S -sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" ${TESTFILE010} -git add ${TESTFILE010} + echo "lint-stable-003-whitespace" + sed -i.bak 's/^$/ /' "${TESTFILE003}" -#lint-stable-012-executable-bit -TESTFILE012=src/lib/libgcc.c -chmod +x ${TESTFILE012} + echo "lint-stable-004-style-labels" + sed -i.bak 's/^done:/ done:/' "${TESTFILE004}" -#lint-stable-013-site-local -mkdir -p site-local -TESTFILE013=$(mktemp --tmpdir=site-local) -git add -f ${TESTFILE013} + echo "lint-stable-005-board-status" + sed -i.bak 's/^Category:.*/Category: lint/' "${TESTFILE005a}" + + echo "lint-stable-006-board-name" + rm -f "${TESTFILE006}" + + echo "lint-stable-008-kconfig" + sed -i.bak 's|config MISSING_BOARD_RESET|config MISSINGBOARDRESET|' "${TESTFILE008}" + + echo "lint-stable-009-old-licenses" + sed -i "s|^.*]SPDX-License-Identifier.*|\* for more details.\n \* You${SPACE}should${SPACE}have received a copy of the GNU General Public License\n \* along with this program; if not, write to the Free Software\n \* Foundation, Inc.|" "${TESTFILE009}" + git add "${TESTFILE009}" + + echo "lint-stable-010-asm-syntax" + sed -i "1s/^/.att${UNDERSCORE}syntax noprefix\n/" "${TESTFILE010}" + git add "${TESTFILE010}" + + echo "lint-stable-012-executable-bit" + chmod +x "${TESTFILE012}" + + echo "lint-stable-013-site-local" + mkdir -p site-local + git add -f "${TESTFILE013}" + + echo "lint-stable-016-non-ascii" + sed -i.bak 's|halt(|halt'"$(echo "\007")"'(|' "${TESTFILE016}" + + echo "lint-stable-017-configs" + make olddefconfig + cp .config "${TESTFILE017}" + + echo "lint-stable-018-symlinks" + rm -f "${TESTFILE018}" + ln -s src/Kconfig "${TESTFILE018}" + git add -f "${TESTFILE018}" + + # lint-stable-019-header-files + # lint-stable-021-coreboot-lowercase + # lint-stable-022-clang-format + # lint-stable-023-filenames + # lint-stable-024-kconfig-no-subsystem + # lint-stable-026-line-endings + echo "lint-stable-027-maintainers-syntax" + sed -i.bak 's|src/cpu/x86/$|src/cpu/x86|' "${TESTFILE027}" + +fi -- To view, visit https://review.coreboot.org/c/coreboot/+/64974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6 Gerrit-Change-Number: 64974 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/dedede/var/shotzo: Update DPTF parameters
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67214 ) Change subject: mb/google/dedede/var/shotzo: Update DPTF parameters ...................................................................... mb/google/dedede/var/shotzo: Update DPTF parameters Update DPTF parameters from internal thermal team. BUG=b:244373677 BRANCH=firmware-dedede-13606.B TEST=Build image and verified by thermal team. Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/shotzo/overridetree.cb 1 file changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb index d84e859..91848e5 100644 --- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb @@ -30,11 +30,63 @@ register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" + + register "tcc_offset" = "5" # TCC of 100C + # USB Port Configuration register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Lan device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + # Default DPTF Policy for all drawcia boards if not overridden + register "options.tsr[0].desc" = ""Ambient"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 60000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 60000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 6500, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 100, + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/67214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4 Gerrit-Change-Number: 67214 Gerrit-PatchSet: 4 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: allocator_v4: Treat above 4G resources more natively
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65413 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: allocator_v4: Treat above 4G resources more natively ...................................................................... allocator_v4: Treat above 4G resources more natively We currently have two competing mechanisms to limit the placement of resources: 1. the explicit `.limit` field of a resource, and 2. the IORESOURCE_ABOVE_4G flag. This makes the resource allocator unnecessarily complex. Ideally, we would always reduce the `.limit` field if we want to "pin" a specific resource below 4G. However, as that's not done across the tree yet, we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint to implicitly lower the `limit` of a resource. In this patch, this is done inside the effective_limit() function that hides the flag from the rest of the allocator. To automatically place resources above 4G if their limit allows it, we have to allocate from top down. Hence, we disable the prompt for RESOURCE_ALLOCATION_TOP_DOWN if resources above 4G are requested. One implication of the changes is that we act differently when a cold-plugged device reports a prefetchable resource with 32-bit limit. Before this change, we would fail to allocate the resource. After this change, it forces everything on the same root port below the 4G line. A possible solution to get completely rid of the IORESOURCE_ABOVE_4G flag would be rules to place resources of certain devices below 4G. For instance, the primary VGA device and storage and HID devices could be made available to a payload that can only address 32 bits. For now, effective_limit() provides us enough abstraction as if the `limit` would be the only variable to consider. With this, we get rid of all the special handling of above 4G resources during phase 2 of the allocator. Which saves us about 20% of the code :D Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65413 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 78 insertions(+), 166 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/device/Kconfig b/src/device/Kconfig index af9beb3..8d10c17f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -934,7 +934,7 @@ above 4G boundary as well. config RESOURCE_ALLOCATION_TOP_DOWN - bool "Allocate resources from top down" + bool "Allocate resources from top down" if !PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G default y depends on RESOURCE_ALLOCATOR_V4 diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 222f1e9..03cec3e 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stdint.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <device/device.h> #include <memrange.h> @@ -22,6 +24,17 @@ return bus && bus->children; } +static resource_t effective_limit(const struct resource *const res) +{ + /* Always allow bridge resources above 4G. */ + if (res->flags & IORESOURCE_BRIDGE) + return res->limit; + + const resource_t quirk_4g_limit = + res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; + return MIN(res->limit, quirk_4g_limit); +} + #define res_printk(depth, str, ...) printk(BIOS_DEBUG, "%*c"str, depth, ' ', __VA_ARGS__) /* @@ -95,22 +108,8 @@ * starts at the domain level takes into account all these constraints * thus working on a global view. */ - if (child_res->limit < bridge_res->limit) - bridge_res->limit = child_res->limit; - - /* - * Propagate the downstream resource request to allocate above 4G - * boundary to upstream bridge resource. This ensures that during - * pass 2, the resource allocator at domain level has a global view - * of all the downstream device requirements and thus address space - * is allocated as per updated flags in the bridge resource. - * - * Since the bridge resource is a single window, all the downstream - * resources of this bridge resource will be allocated in space above - * the 4G boundary. - */ - if (child_res->flags & IORESOURCE_ABOVE_4G) - bridge_res->flags |= IORESOURCE_ABOVE_4G; + if (effective_limit(child_res) < bridge_res->limit) + bridge_res->limit = effective_limit(child_res); /* * Alignment value of 0 means that the child resource has no alignment @@ -223,129 +222,6 @@ die("Unexpected resource type: flags(%d)!\n", res->flags); } -/* - * If the resource is NULL or if the resource is not assigned, then it - * cannot be used for allocation for downstream devices. - */ -static bool is_resource_invalid(const struct resource *res) -{ - return (res == NULL) || !(res->flags & IORESOURCE_ASSIGNED); -} - -static void initialize_domain_io_resource_memranges(struct memranges *ranges, - const struct resource *res, - unsigned long memrange_type) -{ - memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); -} - -static void initialize_domain_mem_resource_memranges(struct memranges *ranges, - const struct resource *res, - unsigned long memrange_type) -{ - resource_t res_base; - resource_t res_limit; - - const resource_t limit_4g = 0xffffffff; - - res_base = res->base; - res_limit = res->limit; - - /* - * Split the resource into two separate ranges if it crosses the 4G - * boundary. Memrange type is set differently to ensure that memrange - * does not merge these two ranges. For the range above 4G boundary, - * given memrange type is ORed with IORESOURCE_ABOVE_4G. - */ - if (res_base <= limit_4g) { - - resource_t range_limit; - - /* Clip the resource limit at 4G boundary if necessary. */ - range_limit = MIN(res_limit, limit_4g); - memranges_insert(ranges, res_base, range_limit - res_base + 1, memrange_type); - - /* - * If the resource lies completely below the 4G boundary, nothing more - * needs to be done. - */ - if (res_limit <= limit_4g) - return; - - /* - * If the resource window crosses the 4G boundary, then update res_base - * to add another entry for the range above the boundary. - */ - res_base = limit_4g + 1; - } - - if (res_base > res_limit) - return; - - /* - * If resource lies completely above the 4G boundary or if the resource - * was clipped to add two separate ranges, the range above 4G boundary - * has the resource flag IORESOURCE_ABOVE_4G set. This allows domain to - * handle any downstream requests for resource allocation above 4G - * differently. - */ - memranges_insert(ranges, res_base, res_limit - res_base + 1, - memrange_type | IORESOURCE_ABOVE_4G); -} - -/* - * This function initializes memranges for domain device. If the - * resource crosses 4G boundary, then this function splits it into two - * ranges -- one for the window below 4G and the other for the window - * above 4G. The latter range has IORESOURCE_ABOVE_4G flag set to - * satisfy resource requests from downstream devices for allocations - * above 4G. - */ -static void initialize_domain_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) -{ - unsigned char align = get_alignment_by_resource_type(res); - - memranges_init_empty_with_alignment(ranges, NULL, 0, align); - - if (is_resource_invalid(res)) - return; - - if (res->flags & IORESOURCE_IO) - initialize_domain_io_resource_memranges(ranges, res, memrange_type); - else - initialize_domain_mem_resource_memranges(ranges, res, memrange_type); -} - -/* - * This function initializes memranges for bridge device. Unlike domain, - * bridge does not need to care about resource window crossing 4G - * boundary. This is handled by the resource allocator at domain level - * to ensure that all downstream bridges are allocated space either - * above or below 4G boundary as per the state of IORESOURCE_ABOVE_4G - * for the respective bridge resource. - * - * So, this function creates a single range of the entire resource - * window available for the bridge resource. Thus all downstream - * resources of the bridge for the given resource type get allocated - * space from the same window. If there is any downstream resource of - * the bridge which requests allocation above 4G, then all other - * downstream resources of the same type under the bridge get allocated - * above 4G. - */ -static void initialize_bridge_memranges(struct memranges *ranges, const struct resource *res, - unsigned long memrange_type) -{ - unsigned char align = get_alignment_by_resource_type(res); - - memranges_init_empty_with_alignment(ranges, NULL, 0, align); - - if (is_resource_invalid(res)) - return; - - memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); -} - static void print_resource_ranges(const struct device *dev, const struct memranges *ranges) { const struct range_entry *r; @@ -383,12 +259,13 @@ if (!resource->size) continue; - if (memranges_steal(ranges, resource->limit, resource->size, resource->align, - type_match, &resource->base, allocate_top_down) == false) { + if (memranges_steal(ranges, effective_limit(resource), resource->size, + resource->align, type_match, &resource->base, + allocate_top_down) == false) { printk(BIOS_ERR, " ERROR: Resource didn't fit!!! "); printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", - dev_path(dev), resource->index, - resource->size, resource->limit, resource2str(resource)); + dev_path(dev), resource->index, resource->size, + effective_limit(resource), resource2str(resource)); continue; } @@ -471,8 +348,8 @@ /* * This function creates a list of memranges of given type using the - * resource that is provided. If the given resource is NULL or if the - * resource window size is 0, then it creates an empty list. This + * resource that is provided. If the given resource is unassigned or if + * the resource window size is 0, then it creates an empty list. This * results in resource allocation for that resource type failing for * all downstream devices since there is nothing to allocate from. * @@ -486,16 +363,17 @@ static void setup_resource_ranges(const struct device *dev, const struct resource *res, unsigned long type, struct memranges *ranges) { + const unsigned char alignment = get_alignment_by_resource_type(res); + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); - if (dev->path.type == DEVICE_PATH_DOMAIN) { - initialize_domain_memranges(ranges, res, type); + memranges_init_empty_with_alignment(ranges, NULL, 0, alignment); + if (res->flags & IORESOURCE_ASSIGNED) + memranges_insert(ranges, res->base, res->limit - res->base + 1, type); + if (dev->path.type == DEVICE_PATH_DOMAIN) constrain_domain_resources(dev, ranges, type); - } else { - initialize_bridge_memranges(ranges, res, type); - } print_resource_ranges(dev, ranges); } @@ -608,26 +486,12 @@ * the resource allocation at domain level considers mem and prefmem * together when finding the best fit based on the biggest resource * requirement. - * - * However, resource requests for allocation above 4G boundary need to - * be handled separately if the domain resource window crosses this - * boundary. There is a single window for resource of type - * IORESOURCE_MEM. When creating memranges, this resource is split into - * two separate ranges -- one for the window below 4G boundary and other - * for the window above 4G boundary (with IORESOURCE_ABOVE_4G flag set). - * Thus, when allocating child resources, requests for below and above - * the 4G boundary are handled separately by setting the type_mask and - * type_match to allocate_child_resources() accordingly. */ res = find_domain_resource(domain, IORESOURCE_MEM); if (res) { setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); allocate_child_resources(domain->link_list, &ranges, - IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, - IORESOURCE_MEM); - allocate_child_resources(domain->link_list, &ranges, - IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, - IORESOURCE_MEM | IORESOURCE_ABOVE_4G); + IORESOURCE_TYPE_MASK, IORESOURCE_MEM); cleanup_resource_ranges(domain, &ranges, res); } -- To view, visit https://review.coreboot.org/c/coreboot/+/65413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Gerrit-Change-Number: 65413 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2022