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[M] Change in coreboot[master]: Documentation: Add some more acronyms to the list.
by build bot (Jenkins) (Code Review) 04 Sep '22

04 Sep '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67330 ) Change subject: Documentation: Add some more acronyms to the list. ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158016): https://review.coreboot.org/c/coreboot/+/67330/comment/cc13c3ab_e54aadc6 PS1, Line 6: Subject line should not end with a period. -- To view, visit https://review.coreboot.org/c/coreboot/+/67330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Gerrit-Change-Number: 67330 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:51:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add some more acronyms to the list.
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67330 ) Change subject: Documentation: Add some more acronyms to the list. ...................................................................... Documentation: Add some more acronyms to the list. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d --- M Documentation/acronyms.md 1 file changed, 53 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/67330/1 diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 83b61a3..20ba746 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -11,6 +11,7 @@ `acpihelp _XXX` * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication) * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space. + Better abbreviated as 4GiB * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G) ## A @@ -45,6 +46,10 @@ * ALIB - AMD: ACPI-ASL Library * ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor) * ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit) +* AMBA - ARM: [**Advanced Microcontroller Bus + Architecture*]](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_…: + An open standard to connect and manage functional blocks in an SoC + (System on a Chip) * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.co… - Also referred to as SBI: Sideband Interface @@ -53,7 +58,7 @@ * AOAC - AMD: Always On, Always Connected * AP - Application processor - The main processor on the board (as opposed to the embedded controller or other processors that may be on - the system), any cores in processor chip that isn’t the BSP - Boot + the system), any cores in processor chip that aren't the BSP - Boot Strap Processor. * APCB - AMD: AMD PSP Customization Block * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API) @@ -123,6 +128,7 @@ stored as a single object, this was co-opted by the open source communities to mean any proprietary binary file that is not available as source code. +* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering) * BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management… * BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format) * BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials) @@ -165,7 +171,8 @@ * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity) * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim) * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer) -* CL - Change List - A git patch in gerrit +* CL - ChangeList - Another name for a patch or commit. This seems to be + Perforce notation. * CLK - Clock - Used when there isn't enough room for 2 additional characters - similar to RST, for people who hate vowels. * CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake) @@ -180,6 +187,7 @@ * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi) * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged. * CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device) +* CPPC - AMD: Collaborative Processor Performance Controls * CPS - Characters Per Second * CPU - [**Central Processing Unit**](http://en.wikipedia.org/wiki/Central_processing_unit) @@ -196,12 +204,14 @@ * CSI - MIPI: [**Camera Serial Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface) * CSME - Intel: Converged Security and Management Engine +* CTLE - Intel: Continuous Time Linear Equalization * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Expos… -* CZN - AMD: Cezanne - CPU Family 19h, Model 50h +* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h ## D +* D$ - Data Cache * D-States - [**ACPI Device power states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_In… D0-D3 - These are device specific power states, with each higher @@ -223,6 +233,8 @@ * DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel) * DDI - Intel: Digital Display Interface * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate) +* DEVAPC - Mediatek: Device Access Permission Control +* DFP - USB: Downstream Facing port * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protoc… * DID - Device Identifier * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM) @@ -243,6 +255,7 @@ * DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton) * DOS - Disk Operating System * DP - DisplayPort +* DPM - Mediatek: DRAM Power Manager * DPTF - Intel: Dynamic Power and Thermal Framework * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory) * DRTM - Dynamic Root of Trust for Measurement @@ -250,7 +263,10 @@ data-in pin is generally referred to as D, and the data-out pin is Q, thus the IO Data signal lines are referred to as DQ lines. * DQS - Memory: Data Q Strobe - Data valid signal for DDR memory. -* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management) +* DRM - [**Digital Rights + Management**](https://en.wikipedia.org/wiki/Digital_rights_management) +* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or + an Upstream Facing (UFP). * DRQ - DMA Request * DRTU - Intel: Diagnostics and Regulatory Testing Utility * DSDT - The [**Differentiated System Descriptor @@ -262,12 +278,15 @@ * DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line) * DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor) * DTB - U-Boot: Device Tree Binary -* dTPM - Discrete Trusted Platform Module +* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip, + vs Integrated TPMs or fTPMs (Firmware TPMs). * DTS - U-Boot: Device Tree Source * DVFS - ARM: Dynamic Voltage and Frequency Scaling * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface) * DVT - Production Timeline: Design Validation Test -* DW - DesignWare +* DW - DesignWare: A portfolio of silicon IP blocks for sale by the + Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA, + I2c, memory controllers and more. * DXE - UEFI: [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_In… * DXIO - AMD: Distributed CrossBar I/O @@ -283,7 +302,7 @@ Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_… - A DRAM standard introduced in 1994 that improved upon, but was backwards compatible with FPM (Fast Page Mode) memory. -* EDP - [**Embedded DisplayPort**](DisplayPort) +* EDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP) * EDS - Intel: External Design Specification * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake: electrical erasable programmable ROM). @@ -340,7 +359,9 @@ * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus) * FSP - Intel: Firmware Support Package * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol) -* FTPM - Firmware TPM +* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is + based in firmware instead of actual hardware. It typically runs in + some sort of TEE (Trusted Execution Environment). ## G @@ -407,6 +428,7 @@ ## I +* I$ - Instruction Cache * I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for communication generally between different ICs on a circuit board. * [https://www.esacademy.com/en/library/technical-articles-and-documents/misce… @@ -540,6 +562,7 @@ * MCU - [**MicroController Unit**](https://en.wikipedia.org/wiki/Microcontroller) * MDFIO - Intel: Multi-Die Fabric IO +* MDN - AMD: Mendocino * ME - Intel: Management Engine * MEI - Intel: ME Interface (Previously known as HECI) * Memory training - the process of finding the best speeds, voltages, @@ -621,8 +644,8 @@ * ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state * ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state. -* ODM - Original Design Manufacturer -* OEM - Original Equipment Manufacturer +* ODM - [Original Design Manufacturer](https://en.wikipedia.org/wiki/Original_design_manufacturer) +* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufactur… * OHCI - [**Open Host Controller Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB… - non-proprietary USB Host controller for USB 1.1 (May also refer to @@ -669,7 +692,7 @@ function's configuration space from 256 bytes to 4K. * PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express) * PCMCIA: Personal Computer Memory Card International Association -* PCO - AMD: Picasso +* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso) * PCR: TPM: Platform Configuration Register * PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage. Setting it low drives it to ground through a resistor. * PD - Power Delivery - This is a specification for communicating power @@ -873,6 +896,7 @@ * SPI - [**Serial Peripheral Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) * SPL - AMD: Security Patch Level +* SPM - Mediatek: System Power Manager * SPMI - MIPI: System Power Management Interface * SRAM - Static Random Access Memory * SSD - Solid State Drive @@ -889,7 +913,9 @@ Bay**](https://en.wikipedia.org/wiki/SSI_CEB) * SSI-TEB - Physical board format: [**SSI Thin Electronics Bay**](https://en.wikipedia.org/wiki/SSI_CEB) +* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing) * STAPM - AMD: Skin Temperature Aware Power Management +* STB - AMD: Smart Trace Buffer * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) (SIO) device provides a system with any of a number of different peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT @@ -909,7 +935,8 @@ * TDMA - Time-Division Multiple Access * TDP - [**Thermal Design Power**](https://en.wikipedia.org/wiki/Thermal_design_power) -* TEE - Trusted Execution Environment +* TEE - [**Trusted Execution + Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment) * TFTP - Network Protocol: Trivial File Transfer Protocol * TGL - Intel: Tigerlake * THC - Touch Host Controller @@ -918,6 +945,7 @@ * TLA - Techtronics Logic Analyzer * TLA - Three Letter Acronym * TLB - [**Translation Lookside +* TME - Intel: Total Memory Encryption Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer) * TOCTOU - Time-Of-Check to Time-Of-Use * TOLUM - Top of Low Usable Memory @@ -927,6 +955,7 @@ * TSC - [**Time Stamp Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter) * TSEG - TOM (Top of Memory) Segment +* TSR - Temperature Sensor * TWAIN - Technology without an interesting name. * TX - Transmit * TXE - Intel: Trusted eXecution Engine @@ -940,6 +969,7 @@ * UDK - UEFI: UEFI Development Kit * UDP - User Datagram Protocol * UEFI - Unified Extensible Firmware Interface +* UFP - USB: Upstream Facing Port * UFS - Universal Flash storage * UHCI - USB: [**Universal Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… @@ -989,6 +1019,7 @@ tablets, it's on the the side away from the screen. * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer) * WLAN - Wireless LAN (Local Area Network) +* WWAN - Telecommunication: Wireless WAN (Wide Area Network) * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29) * WO - Write-only * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN) -- To view, visit https://review.coreboot.org/c/coreboot/+/67330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Gerrit-Change-Number: 67330 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: allocator_v4: Treat above 4G resources more natively
by Angel Pons (Code Review) 04 Sep '22

04 Sep '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65413 ) Change subject: allocator_v4: Treat above 4G resources more natively ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: This was merged too soon... CB:67329 CB:67328 -- To view, visit https://review.coreboot.org/c/coreboot/+/65413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955 Gerrit-Change-Number: 65413 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:29:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: allocator_v4: Disable top-down mode by default
by Angel Pons (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67328 ) Change subject: allocator_v4: Disable top-down mode by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Gerrit-Change-Number: 67328 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:26:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "allocator_v4: Treat above 4G resources more natively"
by Angel Pons (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67329 ) Change subject: Revert "allocator_v4: Treat above 4G resources more natively" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc Gerrit-Change-Number: 67329 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:26:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "allocator_v4: Treat above 4G resources more natively"
by Nico Huber (Code Review) 04 Sep '22

04 Sep '22

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67329 ) Change subject: Revert "allocator_v4: Treat above 4G resources more natively" ...................................................................... Revert "allocator_v4: Treat above 4G resources more natively" This reverts commit 117e436115484f0ce184114b22b716616592e77e. Depends on top-down allocation to keep the behavior to place hot-plug reservations above 4G. The latter was merged prema- turely, though. Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig M src/device/resource_allocator_v4.c 2 files changed, 182 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/67329/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 8d10c17f..af9beb3 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -934,7 +934,7 @@ above 4G boundary as well. config RESOURCE_ALLOCATION_TOP_DOWN - bool "Allocate resources from top down" if !PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G + bool "Allocate resources from top down" default y depends on RESOURCE_ALLOCATOR_V4 diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 03cec3e..222f1e9 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> -#include <commonlib/helpers.h> #include <console/console.h> #include <device/device.h> #include <memrange.h> @@ -24,17 +22,6 @@ return bus && bus->children; } -static resource_t effective_limit(const struct resource *const res) -{ - /* Always allow bridge resources above 4G. */ - if (res->flags & IORESOURCE_BRIDGE) - return res->limit; - - const resource_t quirk_4g_limit = - res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; - return MIN(res->limit, quirk_4g_limit); -} - #define res_printk(depth, str, ...) printk(BIOS_DEBUG, "%*c"str, depth, ' ', __VA_ARGS__) /* @@ -108,8 +95,22 @@ * starts at the domain level takes into account all these constraints * thus working on a global view. */ - if (effective_limit(child_res) < bridge_res->limit) - bridge_res->limit = effective_limit(child_res); + if (child_res->limit < bridge_res->limit) + bridge_res->limit = child_res->limit; + + /* + * Propagate the downstream resource request to allocate above 4G + * boundary to upstream bridge resource. This ensures that during + * pass 2, the resource allocator at domain level has a global view + * of all the downstream device requirements and thus address space + * is allocated as per updated flags in the bridge resource. + * + * Since the bridge resource is a single window, all the downstream + * resources of this bridge resource will be allocated in space above + * the 4G boundary. + */ + if (child_res->flags & IORESOURCE_ABOVE_4G) + bridge_res->flags |= IORESOURCE_ABOVE_4G; /* * Alignment value of 0 means that the child resource has no alignment @@ -222,6 +223,129 @@ die("Unexpected resource type: flags(%d)!\n", res->flags); } +/* + * If the resource is NULL or if the resource is not assigned, then it + * cannot be used for allocation for downstream devices. + */ +static bool is_resource_invalid(const struct resource *res) +{ + return (res == NULL) || !(res->flags & IORESOURCE_ASSIGNED); +} + +static void initialize_domain_io_resource_memranges(struct memranges *ranges, + const struct resource *res, + unsigned long memrange_type) +{ + memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); +} + +static void initialize_domain_mem_resource_memranges(struct memranges *ranges, + const struct resource *res, + unsigned long memrange_type) +{ + resource_t res_base; + resource_t res_limit; + + const resource_t limit_4g = 0xffffffff; + + res_base = res->base; + res_limit = res->limit; + + /* + * Split the resource into two separate ranges if it crosses the 4G + * boundary. Memrange type is set differently to ensure that memrange + * does not merge these two ranges. For the range above 4G boundary, + * given memrange type is ORed with IORESOURCE_ABOVE_4G. + */ + if (res_base <= limit_4g) { + + resource_t range_limit; + + /* Clip the resource limit at 4G boundary if necessary. */ + range_limit = MIN(res_limit, limit_4g); + memranges_insert(ranges, res_base, range_limit - res_base + 1, memrange_type); + + /* + * If the resource lies completely below the 4G boundary, nothing more + * needs to be done. + */ + if (res_limit <= limit_4g) + return; + + /* + * If the resource window crosses the 4G boundary, then update res_base + * to add another entry for the range above the boundary. + */ + res_base = limit_4g + 1; + } + + if (res_base > res_limit) + return; + + /* + * If resource lies completely above the 4G boundary or if the resource + * was clipped to add two separate ranges, the range above 4G boundary + * has the resource flag IORESOURCE_ABOVE_4G set. This allows domain to + * handle any downstream requests for resource allocation above 4G + * differently. + */ + memranges_insert(ranges, res_base, res_limit - res_base + 1, + memrange_type | IORESOURCE_ABOVE_4G); +} + +/* + * This function initializes memranges for domain device. If the + * resource crosses 4G boundary, then this function splits it into two + * ranges -- one for the window below 4G and the other for the window + * above 4G. The latter range has IORESOURCE_ABOVE_4G flag set to + * satisfy resource requests from downstream devices for allocations + * above 4G. + */ +static void initialize_domain_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + unsigned char align = get_alignment_by_resource_type(res); + + memranges_init_empty_with_alignment(ranges, NULL, 0, align); + + if (is_resource_invalid(res)) + return; + + if (res->flags & IORESOURCE_IO) + initialize_domain_io_resource_memranges(ranges, res, memrange_type); + else + initialize_domain_mem_resource_memranges(ranges, res, memrange_type); +} + +/* + * This function initializes memranges for bridge device. Unlike domain, + * bridge does not need to care about resource window crossing 4G + * boundary. This is handled by the resource allocator at domain level + * to ensure that all downstream bridges are allocated space either + * above or below 4G boundary as per the state of IORESOURCE_ABOVE_4G + * for the respective bridge resource. + * + * So, this function creates a single range of the entire resource + * window available for the bridge resource. Thus all downstream + * resources of the bridge for the given resource type get allocated + * space from the same window. If there is any downstream resource of + * the bridge which requests allocation above 4G, then all other + * downstream resources of the same type under the bridge get allocated + * above 4G. + */ +static void initialize_bridge_memranges(struct memranges *ranges, const struct resource *res, + unsigned long memrange_type) +{ + unsigned char align = get_alignment_by_resource_type(res); + + memranges_init_empty_with_alignment(ranges, NULL, 0, align); + + if (is_resource_invalid(res)) + return; + + memranges_insert(ranges, res->base, res->limit - res->base + 1, memrange_type); +} + static void print_resource_ranges(const struct device *dev, const struct memranges *ranges) { const struct range_entry *r; @@ -259,13 +383,12 @@ if (!resource->size) continue; - if (memranges_steal(ranges, effective_limit(resource), resource->size, - resource->align, type_match, &resource->base, - allocate_top_down) == false) { + if (memranges_steal(ranges, resource->limit, resource->size, resource->align, + type_match, &resource->base, allocate_top_down) == false) { printk(BIOS_ERR, " ERROR: Resource didn't fit!!! "); printk(BIOS_DEBUG, " %s %02lx * size: 0x%llx limit: %llx %s\n", - dev_path(dev), resource->index, resource->size, - effective_limit(resource), resource2str(resource)); + dev_path(dev), resource->index, + resource->size, resource->limit, resource2str(resource)); continue; } @@ -348,8 +471,8 @@ /* * This function creates a list of memranges of given type using the - * resource that is provided. If the given resource is unassigned or if - * the resource window size is 0, then it creates an empty list. This + * resource that is provided. If the given resource is NULL or if the + * resource window size is 0, then it creates an empty list. This * results in resource allocation for that resource type failing for * all downstream devices since there is nothing to allocate from. * @@ -363,17 +486,16 @@ static void setup_resource_ranges(const struct device *dev, const struct resource *res, unsigned long type, struct memranges *ranges) { - const unsigned char alignment = get_alignment_by_resource_type(res); - printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); - memranges_init_empty_with_alignment(ranges, NULL, 0, alignment); - if (res->flags & IORESOURCE_ASSIGNED) - memranges_insert(ranges, res->base, res->limit - res->base + 1, type); - if (dev->path.type == DEVICE_PATH_DOMAIN) + if (dev->path.type == DEVICE_PATH_DOMAIN) { + initialize_domain_memranges(ranges, res, type); constrain_domain_resources(dev, ranges, type); + } else { + initialize_bridge_memranges(ranges, res, type); + } print_resource_ranges(dev, ranges); } @@ -486,12 +608,26 @@ * the resource allocation at domain level considers mem and prefmem * together when finding the best fit based on the biggest resource * requirement. + * + * However, resource requests for allocation above 4G boundary need to + * be handled separately if the domain resource window crosses this + * boundary. There is a single window for resource of type + * IORESOURCE_MEM. When creating memranges, this resource is split into + * two separate ranges -- one for the window below 4G boundary and other + * for the window above 4G boundary (with IORESOURCE_ABOVE_4G flag set). + * Thus, when allocating child resources, requests for below and above + * the 4G boundary are handled separately by setting the type_mask and + * type_match to allocate_child_resources() accordingly. */ res = find_domain_resource(domain, IORESOURCE_MEM); if (res) { setup_resource_ranges(domain, res, IORESOURCE_MEM, &ranges); allocate_child_resources(domain->link_list, &ranges, - IORESOURCE_TYPE_MASK, IORESOURCE_MEM); + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, + IORESOURCE_MEM); + allocate_child_resources(domain->link_list, &ranges, + IORESOURCE_TYPE_MASK | IORESOURCE_ABOVE_4G, + IORESOURCE_MEM | IORESOURCE_ABOVE_4G); cleanup_resource_ranges(domain, &ranges, res); } -- To view, visit https://review.coreboot.org/c/coreboot/+/67329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc Gerrit-Change-Number: 67329 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: allocator_v4: Disable top-down mode by default
by Nico Huber (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Nico Huber. Hello Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67328 to look at the new patch set (#2). Change subject: allocator_v4: Disable top-down mode by default ...................................................................... allocator_v4: Disable top-down mode by default The top-down allocation feature was merged prematurely before platforms that don't report their resources correctly were fixed. Let's turn it off by default. Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/Kconfig 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/67328/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e Gerrit-Change-Number: 67328 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Documentation/releases: Add details about edk2 updates
by build bot (Jenkins) (Code Review) 04 Sep '22

04 Sep '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66440 ) Change subject: Documentation/releases: Add details about edk2 updates ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592f0ee971737ef271d1df9142551eb24b775a06 Gerrit-Change-Number: 66440 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:21:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: payloads/edk2: Add the recipes to assemble UniversalPayload
by build bot (Jenkins) (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Sean Rhodes, Martin L Roth, Stefan Reinauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65932 ) Change subject: payloads/edk2: Add the recipes to assemble UniversalPayload ...................................................................... Patch Set 39: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/65932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6363c92f8155007e05c682694d7413fd4630b6d Gerrit-Change-Number: 65932 Gerrit-PatchSet: 39 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:20:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: payloads/edk2: Add a recipe to build the ShimLayer
by Sean Rhodes (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Martin L Roth, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64485 ) Change subject: payloads/edk2: Add a recipe to build the ShimLayer ...................................................................... Patch Set 57: (2 comments) File payloads/external/edk2/Makefile: https://review.coreboot.org/c/coreboot/+/64485/comment/f0a2aebd_ce299550 PS56, Line 253: $(WORKSPACE)/Build/UniversalPayload.elf prep > Nit: indent an extra level to show that this is a continuation of the previous line. Done https://review.coreboot.org/c/coreboot/+/64485/comment/d9e18e19_4dc6b2c3 PS56, Line 254: ; > change to && instead of ; - this prevents the next commands from running if the 'cd' fails for some […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I043271994f40813d9059a89420d4311d9d5802b1 Gerrit-Change-Number: 64485 Gerrit-PatchSet: 57 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 20:19:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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