coreboot-gerrit September 2022

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[M] Change in coreboot[master]: vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67167 ) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00 ...................................................................... vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00 Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00. Changes include: - FspsUpd.h: 1. Add VccInAuxImonSlope UPD 2. Update UPD Offset in FspsUpd.h BUG=b:242152105 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h 1 file changed, 68 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h index b7cb818..05fffb4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h @@ -1555,7 +1555,17 @@ /** Offset 0x06A0 - Reserved **/ - UINT8 Reserved27[10]; + UINT8 Reserved27[7]; + +/** Offset 0x06A7 - VccIn Aux Imon slope correction + PCODE MMIO Mailbox: VccIn Aux Imon slope correction. 0 - Auto Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 VccInAuxImonSlope; + +/** Offset 0x06A8 - Reserved +**/ + UINT8 Reserved28[2]; /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable @@ -1564,7 +1574,7 @@ /** Offset 0x06AB - Reserved **/ - UINT8 Reserved28[13]; + UINT8 Reserved29[13]; /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1587,7 +1597,7 @@ /** Offset 0x06BC - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved30[2]; /** Offset 0x06BE - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = @@ -1621,7 +1631,7 @@ /** Offset 0x06C9 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved31; /** Offset 0x06CA - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value @@ -1632,7 +1642,7 @@ /** Offset 0x06CB - Reserved **/ - UINT8 Reserved31[32]; + UINT8 Reserved32[32]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1826,7 +1836,7 @@ /** Offset 0x0894 - Reserved **/ - UINT8 Reserved32; + UINT8 Reserved33; /** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1836,7 +1846,7 @@ /** Offset 0x0896 - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved34[2]; /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer @@ -1846,7 +1856,7 @@ /** Offset 0x089C - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved35; /** Offset 0x089D - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; @@ -1878,7 +1888,7 @@ /** Offset 0x0929 - Reserved **/ - UINT8 Reserved35[28]; + UINT8 Reserved36[28]; /** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -1936,7 +1946,7 @@ /** Offset 0x09A1 - Reserved **/ - UINT8 Reserved36[3]; + UINT8 Reserved37[3]; /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase @@ -2225,7 +2235,7 @@ /** Offset 0x0A45 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved38; /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2400,7 +2410,7 @@ /** Offset 0x0A6B - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. @@ -2425,7 +2435,7 @@ /** Offset 0x0A89 - Reserved **/ - UINT8 Reserved39[3]; + UINT8 Reserved40[3]; /** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2475,7 +2485,7 @@ /** Offset 0x0A9C - Reserved **/ - UINT8 Reserved40[4]; + UINT8 Reserved41[4]; /** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values @@ -2489,7 +2499,7 @@ /** Offset 0x0AC4 - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved42[4]; /** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2522,7 +2532,7 @@ /** Offset 0x0ADB - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved43; /** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2622,7 +2632,7 @@ /** Offset 0x0B00 - Reserved **/ - UINT8 Reserved43[12]; + UINT8 Reserved44[12]; /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. @@ -2715,7 +2725,7 @@ /** Offset 0x0BD1 - Reserved **/ - UINT8 Reserved44[3]; + UINT8 Reserved45[3]; /** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -2992,7 +3002,7 @@ /** Offset 0x0CA2 - Reserved **/ - UINT8 Reserved45[2]; + UINT8 Reserved46[2]; /** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3006,7 +3016,7 @@ /** Offset 0x0CAC - Reserved **/ - UINT8 Reserved46[5]; + UINT8 Reserved47[5]; /** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable @@ -3016,7 +3026,7 @@ /** Offset 0x0CB2 - Reserved **/ - UINT8 Reserved47[4]; + UINT8 Reserved48[4]; /** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; @@ -3409,7 +3419,7 @@ /** Offset 0x0D2D - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3449,7 +3459,7 @@ /** Offset 0x0D3A - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved50[2]; /** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -3552,7 +3562,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved50[4]; + UINT8 Reserved51[4]; /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled @@ -3624,7 +3634,7 @@ /** Offset 0x0D82 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved52; /** Offset 0x0D83 - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: @@ -3635,7 +3645,7 @@ /** Offset 0x0D84 - Reserved **/ - UINT8 Reserved52[32]; + UINT8 Reserved53[32]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3684,7 +3694,7 @@ /** Offset 0x0DAB - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved54; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3836,7 +3846,7 @@ /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved54[16]; + UINT8 Reserved55[16]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, Default = 0 @@ -3858,7 +3868,7 @@ /** Offset 0x0FAF - Reserved **/ - UINT8 Reserved55[33]; + UINT8 Reserved56[33]; /** Offset 0x0FD0 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3885,7 +3895,7 @@ /** Offset 0x0FD7 - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved57; /** Offset 0x0FD8 - Emmc Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help @@ -3919,7 +3929,7 @@ /** Offset 0x0FF0 - Reserved **/ - UINT8 Reserved57[69]; + UINT8 Reserved58[69]; /** Offset 0x1035 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -3929,7 +3939,7 @@ /** Offset 0x1036 - Reserved **/ - UINT8 Reserved58[122]; + UINT8 Reserved59[138]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3948,11 +3958,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x10B0 +/** Offset 0x10C0 **/ UINT8 UnusedUpdSpace45[6]; -/** Offset 0x10B6 +/** Offset 0x10C6 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/67167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Gerrit-Change-Number: 67167 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.corp-partner.google.com> Gerrit-CC: Jesper Lin <jesper_lin(a)wistron.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Saurabh Mishra, Ronak Kanabar, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67167 ) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00 ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h: https://review.coreboot.org/c/coreboot/+/67167/comment/18cf64f7_eeccf377 PS4, Line 3898: UINT8 Reserved57; Maybe in some future commit, these could be renamed to just match their offsets so that they don't need to be renumbered every time. -- To view, visit https://review.coreboot.org/c/coreboot/+/67167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Gerrit-Change-Number: 67167 Gerrit-PatchSet: 4 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.corp-partner.google.com> Gerrit-CC: Jesper Lin <jesper_lin(a)wistron.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa: Disable the stylus GPIO pins based on fw_config
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: V Sowmya, Tim Wawrzynczak. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66929 ) Change subject: mb/google/nissa: Disable the stylus GPIO pins based on fw_config ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/66929/comment/b70714ae_3d66dd3d PS2, Line 9: GPIO's Nit: GPIOs -- To view, visit https://review.coreboot.org/c/coreboot/+/66929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe9f379abe10a741642e11d4833d3a53489693a Gerrit-Change-Number: 66929 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromeec: Modify ufp from type-c role
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Dtrain Hsu, Paul Menzel, Zhuohao Lee, Ricky Chang. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67168 ) Change subject: ec/google/chromeec: Modify ufp from type-c role ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67168/comment/f9e5628f_42e2deaa PS3, Line 9: In order to fix the USB port of type-C dongle has no function after reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA). Please wrap. -- To view, visit https://review.coreboot.org/c/coreboot/+/67168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73a4a6ec37129388783599125f067068d155d93f Gerrit-Change-Number: 67168 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 16:00:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Arthur Heymans, Werner Zeh. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67099 ) Change subject: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67099/comment/7729d4cf_3df527cf PS3, Line 12: devietree devicetree File src/drivers/i2c/rv3028c7/chip.h: https://review.coreboot.org/c/coreboot/+/67099/comment/09a8994f_eeafc202 PS3, Line 2: Add guards around header file? https://review.coreboot.org/c/coreboot/+/67099/comment/6433b40e_40edb4bd PS3, Line 28: CARGE_VIA_3K CHARGE_? Same below. https://review.coreboot.org/c/coreboot/+/67099/comment/88113048_f794616a PS3, Line 38: /* User year to set */ /* User year to set (2-digit) */ https://review.coreboot.org/c/coreboot/+/67099/comment/77c28363_86d000e0 PS3, Line 41: cap_cahrge cap_charge? File src/drivers/i2c/rv3028c7/rv3028c7.c: https://review.coreboot.org/c/coreboot/+/67099/comment/a6ce518f_c40dee34 PS3, Line 22: } while ((status & EE_BUSY_BIT) && !stopwatch_expired(&sw)); Add a 1ms delay here so this time can be used elsewhere if needed? See thread_yield functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/67099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Gerrit-Change-Number: 67099 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 04 Sep 2022 15:56:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/i2c_bus: Add routines to read and write multiple bytes
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67098 ) Change subject: device/i2c_bus: Add routines to read and write multiple bytes ...................................................................... device/i2c_bus: Add routines to read and write multiple bytes Some devices require that several bytes are written with a single I2C write command. Extend the i2c_bus interface functions and add both, read and write for more than one byte at a defined byte offset. Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67098 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/device/i2c_bus.c M src/include/device/i2c_bus.h 2 files changed, 102 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 8368c24..f0d7dd1 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -183,3 +183,73 @@ return -1; } } + +int i2c_dev_read_at(struct device *const dev, uint8_t *const buf, const size_t len, + uint8_t off) +{ + struct device *const busdev = i2c_busdev(dev); + if (!busdev) + return -1; + + if (busdev->ops->ops_i2c_bus) { + const struct i2c_msg msg[] = { + { + .flags = 0, + .slave = dev->path.i2c.device, + .buf = &off, + .len = sizeof(off), + }, + { + .flags = I2C_M_RD, + .slave = dev->path.i2c.device, + .buf = buf, + .len = len, + }, + }; + + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); + if (ret) + return ret; + else + return len; + } else { + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + return -1; + } +} + +int i2c_dev_write_at(struct device *const dev, uint8_t *const buf, const size_t len, + uint8_t off) +{ + struct device *const busdev = i2c_busdev(dev); + if (!busdev) + return -1; + + if (busdev->ops->ops_i2c_bus) { + const struct i2c_msg msg[] = { + { + .flags = 0, + .slave = dev->path.i2c.device, + .buf = &off, + .len = sizeof(off), + }, + { + .flags = I2C_M_NOSTART, + .slave = dev->path.i2c.device, + .buf = buf, + .len = len, + }, + }; + + const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg, + ARRAY_SIZE(msg)); + if (ret) + return ret; + else + return len; + } else { + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + return -1; + } +} diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 1a7e777..4c9b98d 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -90,5 +90,19 @@ * value on error. */ int i2c_dev_read_at16(struct device *, uint8_t *buf, size_t len, uint16_t off); +/* + * Sends the 8-bit register offset `off` and reads `len` bytes into `buf`. + * + * Returns the number of bytes read on success, negative `enum cb_err` + * value on error. + */ +int i2c_dev_read_at(struct device *, uint8_t *buf, size_t len, uint8_t off); +/* + * Sends the 8-bit register offset `off` and writes `len` bytes from `buf`. + * + * Returns the number of bytes written on success, negative `enum cb_err` + * value on error. + */ +int i2c_dev_write_at(struct device *, uint8_t *buf, size_t len, uint8_t off); #endif /* _DEVICE_I2C_BUS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/67098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303 Gerrit-Change-Number: 67098 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: security/vboot/tpm: Avoid duplicate vb2api_secdata_firmware_create calls
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67219 ) Change subject: security/vboot/tpm: Avoid duplicate vb2api_secdata_firmware_create calls ...................................................................... security/vboot/tpm: Avoid duplicate vb2api_secdata_firmware_create calls For TPM2, vb2api_secdata_firmware_create() is already called from setup_firmware_space() from _factory_initialize_tpm(). Therefore move the duplicate call from factory_initialize_tpm() to TPM1's _factory_initialize_tpm(). Change-Id: I892df65c847e1aeeabef8a7578bec743b639a127 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67219 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/secdata_tpm.c 1 file changed, 20 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Aseda Aboagye: Looks good to me, but someone else must approve diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 450c681..3ad7fc8 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -488,6 +488,7 @@ TPM_PERMANENT_FLAGS pflags; uint32_t result; + vb2api_secdata_firmware_create(ctx); vb2api_secdata_kernel_create_v0(ctx); result = tlcl_get_permanent_flags(&pflags); @@ -558,12 +559,6 @@ { uint32_t result; - /* - * Set initial values of secdata_firmware space. - * kernel space is created in _factory_initialize_tpm(). - */ - vb2api_secdata_firmware_create(ctx); - VBDEBUG("TPM: factory initialization\n"); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/67219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I892df65c847e1aeeabef8a7578bec743b639a127 Gerrit-Change-Number: 67219 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/lint: ignore util/goswid, a new submodule
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67327 ) Change subject: util/lint: ignore util/goswid, a new submodule ...................................................................... util/lint: ignore util/goswid, a new submodule git submodules should be ignored when parsing the coreboot tree for lint errors. Those should be handled in their own commit checks. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85 --- M util/lint/lint-stable-003-whitespace 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/67327/1 diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 9a6db00..5174120 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -5,7 +5,7 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.gif$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$|\.md$' +EXCLUDELIST='^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|^util/goswid$|COPYING|LICENSE|README|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$|\.gif$|\.ttf$|\.woff$|\.png$|\.eot$|\.vbt$|\.ico$|\.md$' INCLUDELIST="src util payloads Makefile* toolchain.inc tests" # shellcheck disable=SC2086,SC2046 -- To view, visit https://review.coreboot.org/c/coreboot/+/67327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85 Gerrit-Change-Number: 67327 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/lint/lint: Add -I option to invert test results
by Martin L Roth (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67193 to look at the new patch set (#2). Change subject: util/lint/lint: Add -I option to invert test results ...................................................................... util/lint/lint: Add -I option to invert test results To test the linters, we want to invert the results so that any test that passes shows up as a failure. This will allow us to verify that all of the linters are working correctly. This will be tested nightly as well as on changes to the lint tools. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c --- M util/lint/lint 1 file changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/67193/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c Gerrit-Change-Number: 67193 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd: Add amdfw.rom to fmap if it is at 0x20000
by Bao Zheng (Code Review) 04 Sep '22

04 Sep '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/67326 to review the following change. Change subject: soc/amd: Add amdfw.rom to fmap if it is at 0x20000 ...................................................................... soc/amd: Add amdfw.rom to fmap if it is at 0x20000 For the AMD family SOC which only accepts one EFS header at 0x20000, CBFS layout can not handle. So we need to add it into the flashmap. FLASH@0xFF000000 16M { BIOS { EC 128K AMDFW @128K 2M RW_MRC_CACHE 64K FMAP 4K COREBOOT(CBFS) } } TODO: Need to handle the case which flash size is other than 16MB. Change-Id: I777f0b975a5aecc3a5f64a533c2dd2161fb88195 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/Makefile.inc 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/67326/1 diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 03e57c0..435e59c 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -26,10 +26,16 @@ amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin) +#TODO +ifeq ($(AMD_SOC_FWM_POSITION), 4278321152) +$(call add_intermediate, AMDFWROM, $(obj)/amdfw.rom) + $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFW -f $(obj)/amdfw.rom --fill-upward +else cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(AMD_SOC_FWM_POSITION) apu/amdfw-type := raw +endif ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a -- To view, visit https://review.coreboot.org/c/coreboot/+/67326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I777f0b975a5aecc3a5f64a533c2dd2161fb88195 Gerrit-Change-Number: 67326 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit September 2022