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Change subject: mb/google/corsola: Fix ANX7625 power-on T4 sequence
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> how about the boot time? […]
The delay won't impact the boot time of the normal boot. `display_init_required()` will determine whether `configure_display` should be run or not.
Ayo still has some questions for Analogix. Let's wait until Analogix clarifies the questions.
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Change subject: mb/google/dedede/var/shotzo: Config I2C times for touchscreen/audio
......................................................................
mb/google/dedede/var/shotzo: Config I2C times for touchscreen/audio
Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning.
BUG=b:244403643
BRANCH=firmware-dedede-13606.B
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/shotzo/overridetree.cb
1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/67242/2
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EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67209 )
Change subject: mb/google/skyrim/var/winterhold: Add gpio override settings
......................................................................
Patch Set 6:
(4 comments)
File src/mainboard/google/skyrim/variants/winterhold/gpio.c:
https://review.coreboot.org/c/coreboot/+/67209/comment/4a5dec72_1fa2817e
PS5, Line 7: ramstage*/
> nit: add a space before '*/'
Done
https://review.coreboot.org/c/coreboot/+/67209/comment/368dec2e_3a18cd78
PS5, Line 16:
> Nit: remove extra space. […]
Done
https://review.coreboot.org/c/coreboot/+/67209/comment/a3d3641f_7055950a
PS5, Line 19: // NC
> Remove, or move inside the other comment and add to all of the other comments>
Done
https://review.coreboot.org/c/coreboot/+/67209/comment/e78ffade_d1465d37
PS5, Line 22: /* CLK_REQ1_L / EMMC */
> remove?
Done
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Change subject: soc/amd: Add amdfw.rom to fmap if it is at 0x20000
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Change subject: soc/amd/*: Put code about PSP FW into common Makefile.inc
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Change subject: soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66706/comment/c27b4681_32a62775
PS5, Line 14:
> nit: change to spaces as the indentation above and below.
Ack
https://review.coreboot.org/c/coreboot/+/66706/comment/494da454_9ad39081
PS5, Line 26: https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/CpuMpPei/CpuMpPei.…
> I think the link is no longer accurate, at least I can't make sense out of the line (it's just a closing brace). I guess you could quote the relevant snippet of code.
I have added wrong line number it seems. Corrected now as replaced the line number with the function name in proper.
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan, Ronak Kanabar, Eric Lai, Werner Zeh,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module
......................................................................
soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need
to use coreboot wrapper for performing any
operation over APs.
2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
to skip FSP running CPU feature programming.
Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.
FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).
Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.
Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.
TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.
Without this patch:
Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.
[SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
APICID - 0x00000000, BIST - 0x00000000
[SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0
With this patch:
No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 92 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/66706/6
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