coreboot-gerrit September 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S
by Reka Norman (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Reka Norman, Andrey Petrov. Hello build bot (Jenkins), Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67334 to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S ...................................................................... drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init(). However, most Intel platforms actually load FSP-S earlier than this, in soc_fsp_load(). So the timestamp is added in the wrong place. Add the timestamp in fsps_load() instead, after the load_done early return so that it will only be added for the first call. Before: 949:finished CSE firmware sync 961,833 (17,998) 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) 18:finished LZ4 decompress (ignore for x86) 1,018,797 (469) 30:device enumeration 1,035,096 (16,298) 971:loading FSP-S 1,048,082 (12,986) 954:calling FspSiliconInit 1,049,331 (1,249) After: 949:finished CSE firmware sync 959,355 (16,370) 971:loading FSP-S 978,139 (18,784) 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) 18:finished LZ4 decompress (ignore for x86) 1,016,271 (475) 30:device enumeration 1,032,567 (16,295) 954:calling FspSiliconInit 1,046,867 (14,300) BUG=b:239769975 TEST="loading FSP-S" is added in the right place on nivviks (see above). Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/67334/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/67334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Gerrit-Change-Number: 67334 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S
by Reka Norman (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Reka Norman, Andrey Petrov. Hello build bot (Jenkins), Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67334 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S ...................................................................... drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init(). However, most Intel platforms actually load FSP-S earlier than this, in soc_fsp_load(). So the timestamp is added in the wrong place. Add the timestamp in fsps_load() instead, after the load_done early return so that it will only be added for the first call. Before: 949:finished CSE firmware sync 961,833 (17,998) 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) 18:finished LZ4 decompress (ignore for x86) 1,018,797 (469) 30:device enumeration 1,035,096 (16,298) 971:loading FSP-S 1,048,082 (12,986) 954:calling FspSiliconInit 1,049,331 (1,249) After: 949:finished CSE firmware sync 959,355 (16,370) 971:loading FSP-S 978,139 (18,784) 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) 18:finished LZ4 decompress (ignore for x86) 1,016,271 (475) 30:device enumeration 1,032,567 (16,295) 954:calling FspSiliconInit 1,046,867 (14,300) BUG=b:239769975 TEST="loading FSP-S" is added in the right place on nivviks (see above). Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/67334/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Gerrit-Change-Number: 67334 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S
by build bot (Jenkins) (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67334 ) Change subject: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S ...................................................................... Patch Set 1: (6 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/78c2b889_43fcc1b4 PS1, Line 18: 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/b2c4b1b2_4b490cf8 PS1, Line 20: 30:device enumeration 1,035,096 (16,298) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/c3081423_75c11b8b PS1, Line 21: 971:loading FSP-S 1,048,082 (12,986) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/22daf623_3b244083 PS1, Line 27: 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/19c63865_c792ab1b PS1, Line 29: 30:device enumeration 1,032,567 (16,295) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158035): https://review.coreboot.org/c/coreboot/+/67334/comment/e5d1d40a_d80b6430 PS1, Line 30: 954:calling FspSiliconInit 1,046,867 (14,300) Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/67334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Gerrit-Change-Number: 67334 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 05:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S
by Reka Norman (Code Review) 05 Sep '22

05 Sep '22

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/67334 ) Change subject: drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S ...................................................................... drivers/intel/fsp2_0: Fix location of timestamp for loading FSP-S Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init(). However, most Intel platforms actually load FSP-S earlier than this, in soc_fsp_load(). So the timestamp is added in the wrong place. Add the timestamp in fsps_load() instead, after the load_done early return so that it will only be added for the first call. Before: 949:finished CSE firmware sync 961,833 (17,998) 17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495) 18:finished LZ4 decompress (ignore for x86) 1,018,797 (469) 30:device enumeration 1,035,096 (16,298) 971:loading FSP-S 1,048,082 (12,986) 954:calling FspSiliconInit 1,049,331 (1,249) After: 949:finished CSE firmware sync 959,355 (16,370) 971:loading FSP-S 978,139 (18,784) 17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656) 18:finished LZ4 decompress (ignore for x86) 1,016,271 (475) 30:device enumeration 1,032,567 (16,295) 954:calling FspSiliconInit 1,046,867 (14,300) BUG=b:239769975 TEST="loading FSP-S" is added in the right place on nivviks (see above). Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/67334/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ae5d620..87f77a2 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -217,6 +217,8 @@ if (load_done) return; + timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); + if (resume_from_stage_cache()) { printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n"); stage_cache_load_stage(STAGE_REFCODE, fsps); @@ -245,7 +247,6 @@ void fsp_silicon_init(void) { - timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); fsps_load(); do_silicon_init(&fsps_hdr); -- To view, visit https://review.coreboot.org/c/coreboot/+/67334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61 Gerrit-Change-Number: 67334 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Modify fan speed/duty table
by Sumeet R Pawnikar (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Dtrain Hsu, Tim Wawrzynczak, Ricky Chang. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67307 ) Change subject: mb/google/brya/var/kinox: Modify fan speed/duty table ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/67307/comment/2d504fe7_a155d717 PS2, Line 209: [10] = { 45, 2566, 0, 0, }, : [11] = { 43, 2415, 0, 0, }, : [12] = { 40, 2010, 0, 0, }, : [13] = { 36, 1813, 0, 0, }, : [14] = { 35, 1686, 0, 0, }, : [15] = { 32, 1404, 0, 0, }, : [16] = { 30, 1160, 0, 0, }, : [17] = { 20, 760, 0, 0, }, : [18] = { 10, 760, 0, 0, }, : [19] = { 0, 0, 0, 0, } How did you verify these values working on the system as per above changes ? Please share the details under TEST section or Commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/67307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458 Gerrit-Change-Number: 67307 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 05:25:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
by Werner Zeh (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Mario Scheithauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67169 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 ...................................................................... mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/67169/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/67169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Gerrit-Change-Number: 67169 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
by Werner Zeh (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Martin L Roth. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67169 ) Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/67169/comment/0ce9f0c3_af806b9a PS1, Line 12: chose > choose Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/67169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Gerrit-Change-Number: 67169 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 05:08:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
by build bot (Jenkins) (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67169 ) Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158034): https://review.coreboot.org/c/coreboot/+/67169/comment/856b2e08_bd2dc15f PS2, Line 11: supported. Limit the capabilities in the SD card controller to DDR50 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/67169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Gerrit-Change-Number: 67169 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 05 Sep 2022 05:08:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50
by Werner Zeh (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Mario Scheithauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67169 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 ...................................................................... mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50 Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/67169/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Gerrit-Change-Number: 67169 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal
by build bot (Jenkins) (Code Review) 05 Sep '22

05 Sep '22

Attention is currently required from: Martin L Roth, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67099 ) Change subject: drivers/i2c: Add a new RTC RV-3028-C7 from Micro Crystal ...................................................................... Patch Set 4: (2 comments) File src/drivers/i2c/rv3028c7/rv3028c7.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158030): https://review.coreboot.org/c/coreboot/+/67099/comment/022b4967_0be97bcb PS4, Line 26: if (status & EE_BUSY_BIT) { braces {} are not necessary for any arm of this statement Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-158030): https://review.coreboot.org/c/coreboot/+/67099/comment/9bb8b3d4_7b005e1a PS4, Line 89: if (i2c_dev_write_at(dev, buf, sizeof(buf), 0) != sizeof(buf)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/67099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb Gerrit-Change-Number: 67099 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 05 Sep 2022 05:05:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2022