coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

1 participants
1234 discussions

Change in coreboot[master]: Makefile.inc: Add bootblock to CBFS before others
by Julius Werner (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64547 ) Change subject: Makefile.inc: Add bootblock to CBFS before others ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64547/comment/4a6cfb9b_7ea6d549 PS2, Line 9: cbfstool > > The problem is that it still needs to be updated again every time a new CBFS file is added. […] Yes, I think that's exactly what it will need to have. The way this works on Arm is that coreboot generates bootblock.raw.bin, then usually a platform-specific utility (this would roughly be the equivalent to your ifwitool, I think) transforms that into a bootblock.bin that wraps the code in the required platform-specific encoding including headers, checksums, etc. Finally the Makefiles copy that bootblock.bin into the BOOTBLOCK FMAP section. cbfstool scans the whole FMAP section for the metadata hash magic number, so no matter how it is packaged, as long as it's not compressed or encrypted or anything it will find it. Then it can update the hash as needed. For cases where that area is covered by a checksum or something, there's a mechanism in cbfstool/platform_fixups.c to detect which kind of platform image it is and then update the necessary hashes. This framework worked pretty well for the platforms we've tried for now (Qualcomm and MediaTek), since cbfstool doesn't need to know how to generate the whole platform-specific data structure from scratch, it just needs to know how to find and update any checksums in it. I hope this will transfer to the x86 cases as well. So you would still have your ifwitool or whatever to initially create the IFWI, but cbfstool would need to know how to recompute any checksums in it after it has updated it in-place. It would be nice if we could standardize on all these platforms using the name "BOOTBLOCK" for the FMAP section that contains the bootblock (even if it's technically an "IFWI" or whatever), but we can make cbfstool look for other sections too if necessary. I think +Karthik has been looking into implementing this for AMD -- that one is definitely on our roadmap. For IFWI I was told that this only worked that way on APL/GLK, and starting with JSL the mechanism changed again to something more in line with the big core Intel chips (with bootblock in CBFS). Is that true? If so, I think we (Google) are currently not really planning to work on supporting CBFS verification for APL/GLK and expect the issue to just obsolete itself eventually. But if anyone else wants to implement support for it, they're of course welcome to do so. -- To view, visit https://review.coreboot.org/c/coreboot/+/64547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be Gerrit-Change-Number: 64547 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 21:51:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/rex: Add entry stubs of each stage
by Tarun Tuli (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64591 ) Change subject: mb/google/rex: Add entry stubs of each stage ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2310e58ab92bdb0ce86a9f7284cc0b3e04a2889f Gerrit-Change-Number: 64591 Gerrit-PatchSet: 14 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 21:27:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/meteorlake: Refactor bootblock SoC programming code
by Tarun Tuli (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Kapil Porwal, Angel Pons, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64793 ) Change subject: soc/intel/meteorlake: Refactor bootblock SoC programming code ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/bootblock/bootblock.c: https://review.coreboot.org/c/coreboot/+/64793/comment/fad61d66_427b900a PS1, Line 15: bootblock_ioe_die_early_init(); Could we add a short comment why switching the order solves the hang to the commit comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/64793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a Gerrit-Change-Number: 64793 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 21:24:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Fix for PCIe source clock assignment
by Cliff Huang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Jeremy Compostella, Tim Wawrzynczak. Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63947 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Fix for PCIe source clock assignment ...................................................................... soc/intel/alderlake: Fix for PCIe source clock assignment When an enabled root port without pcie_rp clock being specified, the empty structure provides invalid info, which indicates '0' is the clock source and request. If a root port does not use clock source, it should still need to provide pcie_rp clock structure with flags set to PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it is considered that pcie_rp clock structure is not provided for that root port. Add check and skip for enabled root port that does not have clock structure. In addition, a root port can not use a free running clock or clock set to LAN. Note that ClockUsage is either free running clock, LAN clock, or the root port number which consumes the clock. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63947/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Gerrit-Change-Number: 63947 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Fixed for PCIe source clock assignment
by Cliff Huang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Bora Guvendik, Jeremy Compostella, Tim Wawrzynczak. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63947 ) Change subject: soc/intel/alderlake: Fixed for PCIe source clock assignment ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63947/comment/50e04563_dc1ac7ee PS6, Line 7: Fixed > Fix Done https://review.coreboot.org/c/coreboot/+/63947/comment/fca01ece_e858fa35 PS6, Line 10: false > invalid Done https://review.coreboot.org/c/coreboot/+/63947/comment/39a825ca_ca93b4bd PS6, Line 10: is > " is" Done File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/63947/comment/8d3ffc9e_e6d3f013 PS6, Line 60: cfg[i].flags == 0 > More C idiomatic for no bits set test would be !cfg[i]. […] Done https://review.coreboot.org/c/coreboot/+/63947/comment/ae7ab623_6428f14b PS6, Line 61: ! > What do you think of "Missing clock structure definition for root port %d" ? The index here is config count and is not the same as root port number. -- To view, visit https://review.coreboot.org/c/coreboot/+/63947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c Gerrit-Change-Number: 63947 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 21:24:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/adl: Add missing claimed memory regions
by Eran Mitrani (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Eran Mitrani, Subrata Banik, Angel Pons, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64677 to look at the new patch set (#10). Change subject: soc/intel/adl: Add missing claimed memory regions ...................................................................... soc/intel/adl: Add missing claimed memory regions This CL adds the missing regions from this list in the bug mentioned below The Alder Lake chipset has several more reserved memory regions that are unavailable to the resource allocator than are currently marked as such in the system agent code. This CL adds the following regions: MMSPI CRAB_ABORT TPM LT_SECURITY APIC MMCONF DSM TSEG PMRR GSM DPR BUG=b:149830546 Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/include/soc/systemagent.h M src/soc/intel/alderlake/systemagent.c M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h 6 files changed, 276 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64677/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/64677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f Gerrit-Change-Number: 64677 Gerrit-PatchSet: 10 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver
by Tarun Tuli (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Paul Menzel, Tim Wawrzynczak, Kapil Porwal, Eric Lai, Lean Sheng Tan. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64592 ) Change subject: drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Gerrit-Change-Number: 64592 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 21:16:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/lenovo/*/romstage: Use common hybrid_graphics_init
by Peter Lemenkov (Code Review) 01 Jun '22

01 Jun '22

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33807 Change subject: mb/lenovo/*/romstage: Use common hybrid_graphics_init ...................................................................... mb/lenovo/*/romstage: Use common hybrid_graphics_init Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h M src/drivers/lenovo/hybrid_graphics/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c 7 files changed, 30 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33807/1 diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h index b238440..2f7cce6 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -17,5 +17,6 @@ #define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); +void hybrid_graphics_init(void); #endif /* _DRIVERS_LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 35cb384..e4b27bb 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -24,6 +24,9 @@ #include "hybrid_graphics.h" #include "chip.h" +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> + /* * Returns the hybrid graphics presence and user's card preferences. */ @@ -94,3 +97,29 @@ " FIXME: dGPU power handling not implemented\n"); } } + +void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index ebf5aed..2f7ceb4 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 49de58d..2eed168 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index 1f4b90d..98ff418 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -23,32 +23,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5c23b8e..c23b896 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 67cf97c..1b76def 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -25,32 +25,6 @@ #include <device/device.h> #include <device/pci.h> -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - void pch_enable_lpc(void) { /* EC Decode Range Port60/64, Port62/66 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c3c5c94ce6c6b3fb44c2540a6fa7953a28b761 Gerrit-Change-Number: 33807 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/lenovo/w541/Kconfig: sort alphabetically
by Paul Fagerburg (Code Review) 01 Jun '22

01 Jun '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63997 ) Change subject: mb/lenovo/w541/Kconfig: sort alphabetically ...................................................................... mb/lenovo/w541/Kconfig: sort alphabetically Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/w541/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig index 507de1a..2cb4cf6 100644 --- a/src/mainboard/lenovo/w541/Kconfig +++ b/src/mainboard/lenovo/w541/Kconfig @@ -13,9 +13,9 @@ select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT - select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM select NORTHBRIDGE_INTEL_HASWELL select NO_UART_ON_SUPERIO select SERIRQ_CONTINUOUS_MODE -- To view, visit https://review.coreboot.org/c/coreboot/+/63997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Gerrit-Change-Number: 63997 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabetically
by Paul Fagerburg (Code Review) 01 Jun '22

01 Jun '22

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63996 ) Change subject: mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabetically ...................................................................... mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabetically Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/haswell/Kconfig 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/lenovo/haswell/Kconfig b/src/mainboard/lenovo/haswell/Kconfig index 48b1103..126e92d 100644 --- a/src/mainboard/lenovo/haswell/Kconfig +++ b/src/mainboard/lenovo/haswell/Kconfig @@ -11,16 +11,14 @@ select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE - select MEMORY_MAPPED_TPM - select MAINBOARD_HAS_TPM1 select INTEL_GMA_HAVE_VBT select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM1 select MAINBOARD_USES_IFD_GBE_REGION select MEMORY_MAPPED_TPM - select NO_UART_ON_SUPERIO select NORTHBRIDGE_INTEL_HASWELL + select NO_UART_ON_SUPERIO select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SYSTEM_TYPE_LAPTOP -- To view, visit https://review.coreboot.org/c/coreboot/+/63996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Gerrit-Change-Number: 63996 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2022