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Change subject: soc/intel/meteorlake: Refactor bootblock SoC programming code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/64793/comment/fad61d66_427b900a
PS1, Line 15: bootblock_ioe_die_early_init();
Could we add a short comment why switching the order solves the hang to the commit comment?
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Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Cliff Huang, Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63947
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Change subject: soc/intel/alderlake: Fix for PCIe source clock assignment
......................................................................
soc/intel/alderlake: Fix for PCIe source clock assignment
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63947/7
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Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63947 )
Change subject: soc/intel/alderlake: Fixed for PCIe source clock assignment
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63947/comment/50e04563_dc1ac7ee
PS6, Line 7: Fixed
> Fix
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/fca01ece_e858fa35
PS6, Line 10: false
> invalid
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/39a825ca_ca93b4bd
PS6, Line 10: is
> " is"
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63947/comment/8d3ffc9e_e6d3f013
PS6, Line 60: cfg[i].flags == 0
> More C idiomatic for no bits set test would be !cfg[i]. […]
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/ae7ab623_6428f14b
PS6, Line 61: !
> What do you think of "Missing clock structure definition for root port %d" ?
The index here is config count and is not the same as root port number.
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/adl: Add missing claimed memory regions
......................................................................
soc/intel/adl: Add missing claimed memory regions
This CL adds the missing regions from this list in the bug mentioned
below
The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently
marked as such in the system agent code. This CL adds the
following regions:
MMSPI
CRAB_ABORT
TPM
LT_SECURITY
APIC
MMCONF
DSM
TSEG
PMRR
GSM
DPR
BUG=b:149830546
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/include/soc/systemagent.h
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
6 files changed, 276 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64677/10
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Change subject: drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver
......................................................................
Patch Set 3: Code-Review+2
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