Attention is currently required from: Bora Guvendik, Jeremy Compostella, Tim Wawrzynczak. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63947 )
Change subject: soc/intel/alderlake: Fixed for PCIe source clock assignment ......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63947/comment/50e04563_dc1ac7ee PS6, Line 7: Fixed
Fix
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/fca01ece_e858fa35 PS6, Line 10: false
invalid
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/39a825ca_ca93b4bd PS6, Line 10: is
" is"
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63947/comment/8d3ffc9e_e6d3f013 PS6, Line 60: cfg[i].flags == 0
More C idiomatic for no bits set test would be !cfg[i]. […]
Done
https://review.coreboot.org/c/coreboot/+/63947/comment/ae7ab623_6428f14b PS6, Line 61: !
What do you think of "Missing clock structure definition for root port %d" ?
The index here is config count and is not the same as root port number.
-
Cliff Huang (Code Review)