Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63946 )
Change subject: mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVP
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/63946/comment/edabfdff_b4e77915
PS5, Line 429: device ref pcie_rp3 on end # W/A to FSP issue
: device ref pcie_rp4 on end # W/A to FSP issue
> the comment says WA for FSP issue. […]
This was ported to start with initially, probably ported from ADL-M RVP (src/mainboard/intel/adlrvp/devicetree_m.cb). There is no specific changes just for these two lines. It also results in warning messages in PCIe clock assignment. I tested and I didn't run into any problem.
--
To view, visit https://review.coreboot.org/c/coreboot/+/63946
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf
Gerrit-Change-Number: 63946
Gerrit-PatchSet: 5
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Comment-Date: Wed, 01 Jun 2022 21:02:41 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-MessageType: comment
Attention is currently required from: Bora Guvendik, Cliff Huang, Jeremy Compostella, Subrata Banik, Tim Wawrzynczak.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63943 )
Change subject: soc/intel/alderlake: add support for external source clock
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63943/comment/7c9b15ec_41a8b22a
PS6, Line 9: includingsource
> missing space.
Done
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63943/comment/2b14f830_2fdb5630
PS6, Line 239: default 10 if SOC_INTEL_ALDERLAKE_PCH_P
> Why do you change the line ? Couldn't you just change the value ?
Change was done to the same line, but SOC_INTEL_ALDERLAKE_PCH_S got merged then.
https://review.coreboot.org/c/coreboot/+/63943/comment/e1be5844_be51a0e7
PS6, Line 241: 3
> three
Done
https://review.coreboot.org/c/coreboot/+/63943/comment/638630dd_1c8f28c0
PS6, Line 241: clock
> clocks
Done
https://review.coreboot.org/c/coreboot/+/63943/comment/a6ac3ecb_8417f863
PS6, Line 242: This done
> This is done
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/63943
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Gerrit-Change-Number: 63943
Gerrit-PatchSet: 6
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Comment-Date: Wed, 01 Jun 2022 20:56:02 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: Bora Guvendik, Cliff Huang, Subrata Banik, Tim Wawrzynczak.
Hello Bora Guvendik, Anil Kumar K, build bot (Jenkins), Cliff Huang, Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63943
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: add support for external source clock
......................................................................
soc/intel/alderlake: add support for external source clock
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/63943/7
--
To view, visit https://review.coreboot.org/c/coreboot/+/63943
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Gerrit-Change-Number: 63943
Gerrit-PatchSet: 7
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Bora Guvendik, Anil Kumar K, Jeremy Compostella, Subrata Banik, Tim Wawrzynczak.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63942 )
Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
......................................................................
Patch Set 7:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63942/comment/c683b338_8904cb50
PS6, Line 671: if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
> double negation is unnecessary in a if statement. […]
double negation has been used in several places. also, in if-conditions. if-condition is used here only update when different from FSP default.
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/63942/comment/8dc5b8bd_45f078dd
PS6, Line 30: /* indicates that this root port is built-in */
> missing ending dot character.
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/63942
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Gerrit-Change-Number: 63942
Gerrit-PatchSet: 7
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-CC: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Comment-Date: Wed, 01 Jun 2022 20:47:04 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Tim Wawrzynczak.
Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63942
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
......................................................................
soc/intel/alderlake: support for PCIe slot & device detect timeout
add timeout for root port detection and pass to FSP.
add 'slot implemented' flag and pass to FSP.
PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/63942/7
--
To view, visit https://review.coreboot.org/c/coreboot/+/63942
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Gerrit-Change-Number: 63942
Gerrit-PatchSet: 7
Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com>
Gerrit-CC: Tim Crawford <tcrawford(a)system76.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Philipp Hug, Patrick Georgi, Jakub Czapiga, ron minnich.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64737 )
Change subject: commonlib: Clean up compiler.h
......................................................................
Patch Set 4:
(8 comments)
File src/commonlib/bsd/include/commonlib/bsd/compiler.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/35e8f73e_b8781e8b
PS4, Line 8: #define __packed __attribute__((__gcc_struct__, __packed__))
Prefer __packed over __attribute__((__packed__))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/702b2f35_b172a2aa
PS4, Line 10: #define __packed __attribute__((__packed__))
Prefer __packed over __attribute__((__packed__))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/92852789_a846fcbf
PS4, Line 15: #define __aligned(x) __attribute__((__aligned__(x)))
Prefer __aligned(x) over __attribute__((__aligned__(x)))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/ae1c1fd1_9107a955
PS4, Line 19: #define __unused __attribute__((__unused__))
__always_unused or __maybe_unused is preferred over __attribute__((__unused__))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/4fb0ec37_91917fad
PS4, Line 27: #define __weak __attribute__((__weak__))
Prefer __weak over __attribute__((__weak__))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/538a4768_f9c6d63b
PS4, Line 31: #define __noreturn __attribute__((__noreturn__))
Prefer __noreturn over __attribute__((__noreturn__))
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/9ce4fb90_1bddc896
PS4, Line 35: #define __always_inline inline __attribute__((__always_inline__))
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150416):
https://review.coreboot.org/c/coreboot/+/64737/comment/09270676_6ec266b1
PS4, Line 35: #define __always_inline inline __attribute__((__always_inline__))
Prefer __always_inline over __attribute__((__always_inline__))
--
To view, visit https://review.coreboot.org/c/coreboot/+/64737
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b
Gerrit-Change-Number: 64737
Gerrit-PatchSet: 4
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org>
Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Wed, 01 Jun 2022 20:37:36 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment