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Change in coreboot[master]: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
by Iru Cai (vimacs) (Code Review) 02 May '24

02 May '24

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39398 to review the following change. Change subject: mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant ...................................................................... mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/8560w.md A Documentation/mainboard/hp/8560w_flash.webp M Documentation/mainboard/index.md M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig.name A src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt A src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c A src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb 10 files changed, 477 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39398/1 diff --git a/Documentation/mainboard/hp/8560w.md b/Documentation/mainboard/hp/8560w.md new file mode 100644 index 0000000..6a7c197 --- /dev/null +++ b/Documentation/mainboard/hp/8560w.md @@ -0,0 +1,82 @@ +# HP EliteBook 8560w + +This page describes how to run coreboot on the [HP EliteBook 8560w]. + +## Required proprietary blobs + +- Intel Firmware Descriptor, ME and GbE firmware +- EC: please read [EliteBook Series](elitebook_series) + +## Flashing instructions + +HP EliteBook 8560w has an 8MB SOIC-8 flash chip on the bottom of the +mainboard. You just need to remove the service cover, and use an SOIC-8 +clip to read and flash the chip. + +![8560w_chip_location](8560w_flash.webp) + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Model | MX25L6406E | ++---------------------+------------+ +| Size | 8 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | no | ++---------------------+------------+ +| Dual BIOS feature | no | ++---------------------+------------+ +| In circuit flashing | yes | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +``` + +## Untested + +- mainboards with 4 memory slots + +## Working + +- i7-2720QM, 8G+8G +- Arch Linux boot from SeaBIOS payload +- EHCI debug: the port is beside the eSATA port +- SATA +- eSATA +- USB2 and USB3 +- keyboard +- Gigabit Ethernet +- WLAN +- WWAN +- VGA and DisplayPort +- audio +- EC ACPI +- Using `me_cleaner` +- dock: PS/2 keyboard, USB, DisplayPort +- TPM +- S3 suspend/resume + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | SMSC LPC47n217 | ++------------------+--------------------------------------------------+ +| EC | SMSC KBC1126 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[HP EliteBook 8560w]: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… diff --git a/Documentation/mainboard/hp/8560w_flash.webp b/Documentation/mainboard/hp/8560w_flash.webp new file mode 100644 index 0000000..b8295bc --- /dev/null +++ b/Documentation/mainboard/hp/8560w_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index e46e0f3..a20a0bf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -55,6 +55,7 @@ ### EliteBook series - [EliteBook common](hp/elitebook_series.md) +- [EliteBook 8560w](hp/8560w.md) - [EliteBook 8760w](hp/8760w.md) ## Intel diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig index d0105ff..0ec0d27 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig @@ -37,6 +37,7 @@ default "2760p" if BOARD_HP_2760P default "8460p" if BOARD_HP_8460P default "8470p" if BOARD_HP_8470P + default "8560w" if BOARD_HP_8560W default "8770w" if BOARD_HP_8770W default "folio_9470m" if BOARD_HP_FOLIO_9470M default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1 @@ -47,6 +48,7 @@ default "EliteBook 2760p" if BOARD_HP_2760P default "EliteBook 8460p" if BOARD_HP_8460P default "EliteBook 8470p" if BOARD_HP_8470P + default "EliteBook 8560w" if BOARD_HP_8560W default "EliteBook 8770w" if BOARD_HP_8770W default "EliteBook Folio 9470m" if BOARD_HP_FOLIO_9470M default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1 @@ -75,6 +77,7 @@ default 1 if BOARD_HP_2760P default 1 if BOARD_HP_8460P default 2 if BOARD_HP_8470P + default 1 if BOARD_HP_8560W default 2 if BOARD_HP_8770W default 0 if BOARD_HP_FOLIO_9470M default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name index c4a8662..360373e 100644 --- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name @@ -61,6 +61,17 @@ select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_LPC47N217 +config BOARD_HP_8560W + bool "EliteBook 8560w" + + select BOARD_HP_SNB_IVB_LAPTOPS + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_SMSC_LPC47N217 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + config BOARD_HP_8770W bool "EliteBook 8770w" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt new file mode 100644 index 0000000..af1e296 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-8560w-mobile-workstation/… +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2011 diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c new file mode 100644 index 0000000..57eafe2 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/early_init.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* USB0 */ + { 1, 1, 0 }, /* USB1 */ + { 1, 1, 1 }, /* eSATA */ + { 1, 1, 1 }, /* camera */ + { 0, 0, 2 }, + { 1, 0, 2 }, /* bluetooth */ + { 0, 0, 3 }, + { 1, 0, 3 }, + { 0, 1, 4 }, + { 1, 1, 4 }, /* WWAN */ + { 1, 0, 5 }, + { 1, 0, 5 }, /* dock */ + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c new file mode 100644 index 0000000..29358aa --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c new file mode 100644 index 0000000..d7573d5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/hda_verb.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d7605, /* Codec Vendor / Device ID: IDT */ + 0x103c1631, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c1631), + AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0b, 0x0421401f), + AZALIA_PIN_CFG(0, 0x0c, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x90a60130), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb new file mode 100644 index 0000000..d716b46 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2020 The coreboot project Authors. +# +# SPDX-License-Identifier: GPL-2.0-or-later +# + +chip northbridge/intel/sandybridge + device domain 0x0 on + subsystemid 0x103c 0x1631 inherit + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + # HDD(0), ODD(1), eSATA(4) + register "sata_port_map" = "0x3b" + + device pci 1c.0 on end # PCIe Port #1, WWAN + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/39398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950 Gerrit-Change-Number: 39398 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: [WIP] mb/hp: Add HP ProBook 640 G1
by Iru Cai (vimacs) (Code Review) 02 May '24

02 May '24

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46130 to review the following change. Change subject: [WIP] mb/hp: Add HP ProBook 640 G1 ...................................................................... [WIP] mb/hp: Add HP ProBook 640 G1 Generate code from autoport. It boots to Arch Linux in a USB disk from SeaBIOS payload. EC ACPI doesn't work yet. This board doesn't have HP Sure Start enabled, so we can use all the flash regions, and relocate the EC firmware with CB:41393. Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/640g1.md A src/mainboard/hp/probook_640_g1/Kconfig A src/mainboard/hp/probook_640_g1/Kconfig.name A src/mainboard/hp/probook_640_g1/Makefile.inc A src/mainboard/hp/probook_640_g1/acpi/ec.asl A src/mainboard/hp/probook_640_g1/acpi/platform.asl A src/mainboard/hp/probook_640_g1/acpi/superio.asl A src/mainboard/hp/probook_640_g1/acpi_tables.c A src/mainboard/hp/probook_640_g1/board_info.txt A src/mainboard/hp/probook_640_g1/bootblock.c A src/mainboard/hp/probook_640_g1/devicetree.cb A src/mainboard/hp/probook_640_g1/dsdt.asl A src/mainboard/hp/probook_640_g1/gma-mainboard.ads A src/mainboard/hp/probook_640_g1/gpio.c A src/mainboard/hp/probook_640_g1/hda_verb.c A src/mainboard/hp/probook_640_g1/mainboard.c A src/mainboard/hp/probook_640_g1/romstage.c 17 files changed, 635 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46130/1 diff --git a/Documentation/mainboard/hp/640g1.md b/Documentation/mainboard/hp/640g1.md new file mode 100644 index 0000000..048633f --- /dev/null +++ b/Documentation/mainboard/hp/640g1.md @@ -0,0 +1,65 @@ +# HP ProBook 640 G1 + +This page is about the notebook [HP ProBook 640 G1]. + +## Release status + +(TBD) + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip. We can extract the EC firmware from +the OEM firmware, and insert it in the coreboot image. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +(TBD) + +## Debugging + +The serial port on dock can be used to debug the laptop. + +## Test status + +### Known issues + +(TBD) + +- EC ACPI is not working yet. + +### Untested + +(TBD) + +### Working + +(TBD) + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell (FCPGA946) | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point HM87 | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP ProBook 640 G1]: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04823617 diff --git a/src/mainboard/hp/probook_640_g1/Kconfig b/src/mainboard/hp/probook_640_g1/Kconfig new file mode 100644 index 0000000..d23a3fb --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig @@ -0,0 +1,42 @@ +if BOARD_HP_PROBOOK_640_G1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_SMSC_LPC47N217 + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/probook_640_g1" + +config MAINBOARD_PART_NUMBER + string + default "HP ProBook 640 G1" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +endif diff --git a/src/mainboard/hp/probook_640_g1/Kconfig.name b/src/mainboard/hp/probook_640_g1/Kconfig.name new file mode 100644 index 0000000..f809069 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_PROBOOK_640_G1 + bool "ProBook 640 G1" diff --git a/src/mainboard/hp/probook_640_g1/Makefile.inc b/src/mainboard/hp/probook_640_g1/Makefile.inc new file mode 100644 index 0000000..fa23791 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/probook_640_g1/acpi/ec.asl b/src/mainboard/hp/probook_640_g1/acpi/ec.asl new file mode 100644 index 0000000..ab3a35c --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> \ No newline at end of file diff --git a/src/mainboard/hp/probook_640_g1/acpi/platform.asl b/src/mainboard/hp/probook_640_g1/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/probook_640_g1/acpi/superio.asl b/src/mainboard/hp/probook_640_g1/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/probook_640_g1/acpi_tables.c b/src/mainboard/hp/probook_640_g1/acpi_tables.c new file mode 100644 index 0000000..f9ac854 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi_tables.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/probook_640_g1/board_info.txt b/src/mainboard/hp/probook_640_g1/board_info.txt new file mode 100644 index 0000000..28b9c2f --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year +Board URL: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ diff --git a/src/mainboard/hp/probook_640_g1/bootblock.c b/src/mainboard/hp/probook_640_g1/bootblock.c new file mode 100644 index 0000000..b5b6d43 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void mainboard_config_superio(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/probook_640_g1/devicetree.cb b/src/mainboard/hp/probook_640_g1/devicetree.cb new file mode 100644 index 0000000..4056b9d --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/devicetree.cb @@ -0,0 +1,88 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, dq_pins_interleaved, usb_xhci_on_resume, gfx + register "dq_pins_interleaved" = "false" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x1993 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x7" + # 0(HDD), 1(ODD), 5(M.2) + register "sata_port_map" = "0x37" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WLAN + device pci 1c.7 on end # PCIe Port #8, Card Reader + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x5f" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/probook_640_g1/dsdt.asl b/src/mainboard/hp/probook_640_g1/dsdt.asl new file mode 100644 index 0000000..769d907 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/probook_640_g1/gma-mainboard.ads b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads new file mode 100644 index 0000000..a6af0ac --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/probook_640_g1/gpio.c b/src/mainboard/hp/probook_640_g1/gpio.c new file mode 100644 index 0000000..629117a --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gpio.c @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio19 = GPIO_INVERT, + .gpio21 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/probook_640_g1/hda_verb.c b/src/mainboard/hp/probook_640_g1/hda_verb.c new file mode 100644 index 0000000..5c0f943 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/probook_640_g1/mainboard.c b/src/mainboard/hp/probook_640_g1/mainboard.c new file mode 100644 index 0000000..3f023d0 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/probook_640_g1/romstage.c b/src/mainboard/hp/probook_640_g1/romstage.c new file mode 100644 index 0000000..63c2fb8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/romstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa2; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0080, 1, 0, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 3, USB_PORT_DOCK }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* M.2 */ + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* WLAN */ + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 6, USB_PORT_DOCK }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 0, 2 }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Gerrit-Change-Number: 46130 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46973 ) Change subject: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices ...................................................................... soc/intel/broadwell: Add ACPI CIDs for SerialIO devices Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46973/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 2bacd2b..1e6dbac 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -166,6 +166,7 @@ // LynxPoint-LP Return ("INT33C2") } + Name (_CID, "INT33C2") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -242,6 +243,7 @@ // LynxPoint-LP Return ("INT33C3") } + Name (_CID, "INT33C3") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -318,6 +320,7 @@ // LynxPoint-LP Return ("INT33C0") } + Name (_CID, "INT33C0") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -379,6 +382,7 @@ // LynxPoint-LP Return ("INT33C1") } + Name (_CID, "INT33C1") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -452,6 +456,7 @@ // LynxPoint-LP Return ("INT33C4") } + Name (_CID, "INT33C4") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -525,6 +530,7 @@ // LynxPoint-LP Return ("INT33C5") } + Name (_CID, "INT33C5") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/46973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Gerrit-Change-Number: 46973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps
by Angel Pons (Code Review) 13 Apr '24

13 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47029 ) Change subject: soc/intel/broadwell/pch/sata.c: Add missing SATA init steps ...................................................................... soc/intel/broadwell/pch/sata.c: Add missing SATA init steps WildcatPoint-LP BIOS spec lists them, and are the same for Lynxpoint. Keep the BWG comments for now, since both platforms will be merged soon. Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47029/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 91c2ff5..e9d70f1 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -95,6 +95,15 @@ /* Setup register 98h */ reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba28c1591affafeb37097084c2fa58128974bd00 Gerrit-Change-Number: 47029 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47046 ) Change subject: sb/intel/lynxpoint/lpc.c: Follow Broadwell's order ...................................................................... sb/intel/lynxpoint/lpc.c: Follow Broadwell's order Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 35 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47046/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1845273..d1780fa 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -190,7 +190,6 @@ u16 reg16; u32 reg32; const char *state; - u16 pmbase = get_pmbase(); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; @@ -232,26 +231,6 @@ pci_write_config16(dev, GEN_PMCON_3, reg16); printk(BIOS_INFO, "Set power %s after power failure.\n", state); - /* Set up NMI on errors. */ - reg8 = inb(0x61); - reg8 &= 0x0f; /* Higher Nibble must be 0 */ - reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ - // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ - reg8 |= (1 << 2); /* PCI SERR# Disable for now */ - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); /* Set NMI. */ - } else { - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ - } - outb(reg8, 0x70); - /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); // SMI# rate 1 minute @@ -275,6 +254,11 @@ /* SMI setup based on device tree configuration */ enable_alt_smi(config->alt_gp_smi_en); } +} + +static void pch_misc_init(struct device *dev) +{ + u16 pmbase = get_pmbase(); /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT @@ -282,12 +266,40 @@ reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x70); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Indicate DRAM init done for MRC S3 to know it can resume */ + pci_or_config8(dev, GEN_PMCON_2, 1 << 7); + + /* Enable BIOS updates outside of SMM */ + pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); + /* Clear magic status bits to prevent unexpected wake */ RCBA32_OR(0x3310, (1 << 4) | (1 << 5) | (1 << 0)); reg16 = RCBA16(0x3f02); reg16 &= ~0xf; RCBA16(0x3f02) = reg16; + + pch_enable_serial_irqs(dev); } /* LynxPoint PCH Power Management init */ @@ -461,18 +473,8 @@ apm_control(APM_CNT_ACPI_DISABLE); } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { - /* Indicate DRAM init done for MRC S3 to know it can resume */ - pci_or_config8(dev, GEN_PMCON_2, 1 << 7); - /* * Enable DMI ASPM in the PCH */ @@ -488,14 +490,14 @@ /* IO APIC initialization. */ pch_enable_ioapic(dev); - pch_enable_serial_irqs(dev); - /* Setup the PIRQ. */ pch_pirq_init(dev); /* Setup power options. */ pch_power_options(dev); + pch_misc_init(dev); + /* Initialize power management */ if (pch_is_lp()) { lpt_lp_pm_init(dev); @@ -519,8 +521,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/47046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1 Gerrit-Change-Number: 47046 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp`
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49177 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp` ...................................................................... [UNTESTED] sb/intel/bd82x6x: Replace `write_iobp` Use the already-existing `pch_iobp_update` function instead. Only update individual fields, like reference code does. Several replay issues still remain, and have been marked with comments. Follow-ups will handle them. Change-Id: I5b95134a504d693f8e6f2df35784bf75037b7b16 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 71 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/49177/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 903dc01..0b60d13 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -16,41 +16,6 @@ #include "pch.h" #include "chip.h" -static void wait_iobp(void) -{ - while (RCBA8(IOBPS) & 1) - ; // implement timeout? -} - -static u32 read_iobp(u32 address) -{ - u32 ret; - - RCBA32(IOBPIRI) = address; - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - wait_iobp(); - ret = RCBA32(IOBPD); - wait_iobp(); - RCBA8(IOBPS); // call wait_iobp() instead here? - return ret; -} - -static void write_iobp(u32 address, u32 val) -{ - /* this function was probably pch_iobp_update with the andvalue - * being 0. So either the IOBP read can be removed or this function - * and the pch_iobp_update function in ramstage could be merged */ - read_iobp(address); - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - wait_iobp(); - - RCBA32(IOBPD) = val; - wait_iobp(); - RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; - - RCBA8(IOBPS); // call wait_iobp() instead here? -} - void early_pch_init_native_dmi_pre(void) { /* Link Capabilities Register */ @@ -184,67 +149,79 @@ pch_assign_pcie_lane_mapping(); - write_iobp(0xea007f62, 0x00590133); - write_iobp(0xec007f62, 0x00590133); - write_iobp(0xec007f64, 0x59555588); - write_iobp(0xea0040b9, 0x0001051c); - write_iobp(0xeb0040a1, 0x800084ff); - write_iobp(0xec0040a1, 0x800084ff); - write_iobp(0xea004001, 0x00008400); - write_iobp(0xeb004002, 0x40201758); - write_iobp(0xec004002, 0x40201758); - write_iobp(0xea004002, 0x00601758); - write_iobp(0xea0040a1, 0x810084ff); - write_iobp(0xeb0040b1, 0x0001c598); - write_iobp(0xec0040b1, 0x0001c598); - write_iobp(0xeb0040b6, 0x0001c598); - write_iobp(0xea0000a9, 0x80ff969f); - write_iobp(0xea0001a9, 0x80ff969f); - write_iobp(0xeb0040b2, 0x0001c396); - write_iobp(0xeb0040b3, 0x0001c396); - write_iobp(0xec0040b2, 0x0001c396); - write_iobp(0xea0001a9, 0x80ff94ff); - write_iobp(SATA_IOBP_SP0G3IR, 0x0088037f); - write_iobp(0xea0000a9, 0x80ff94ff); - write_iobp(SATA_IOBP_SP1G3IR, 0x0088037f); + pch_iobp_update(0xea007f62, ~(0xff << 16), 0x59 << 16); + pch_iobp_update(0xec007f62, ~(0xff << 16), 0x59 << 16); + pch_iobp_update(0xec007f64, ~(0xf << 24), 0x9 << 24); + pch_iobp_update(0xea0040b9, ~0xffff, 0x051c); + pch_iobp_update(0xeb0040a1, ~(0x3ff << 3), 0x9f << 3); + pch_iobp_update(0xec0040a1, ~(0x3ff << 3), 0x9f << 3); - write_iobp(0xea007f05, 0x00010642); - write_iobp(0xea0040b7, 0x0001c91c); - write_iobp(0xea0040b8, 0x0001c91c); - write_iobp(0xeb0040a1, 0x820084ff); - write_iobp(0xec0040a1, 0x820084ff); - write_iobp(0xea007f0a, 0xc2480000); + /* Some CPT-only writes go here */ - write_iobp(0xec00404d, 0x1ff177f); - write_iobp(0xec000084, 0x5a600000); - write_iobp(0xec000184, 0x5a600000); - write_iobp(0xec000284, 0x5a600000); - write_iobp(0xec000384, 0x5a600000); - write_iobp(0xec000094, 0x000f0501); - write_iobp(0xec000194, 0x000f0501); - write_iobp(0xec000294, 0x000f0501); - write_iobp(0xec000394, 0x000f0501); - write_iobp(0xec000096, 0x00000001); - write_iobp(0xec000196, 0x00000001); - write_iobp(0xec000296, 0x00000001); - write_iobp(0xec000396, 0x00000001); - write_iobp(0xec000001, 0x00008c08); - write_iobp(0xec000101, 0x00008c08); - write_iobp(0xec000201, 0x00008c08); - write_iobp(0xec000301, 0x00008c08); - write_iobp(0xec0040b5, 0x0001c518); - write_iobp(0xec000087, 0x06077597); - write_iobp(0xec000187, 0x06077597); - write_iobp(0xec000287, 0x06077597); - write_iobp(0xec000387, 0x06077597); - write_iobp(0xea000050, 0x00bb0157); - write_iobp(0xea000150, 0x00bb0157); - write_iobp(0xec007f60, 0x77777d77); - write_iobp(0xea00008d, 0x01320000); - write_iobp(0xea00018d, 0x01320000); - write_iobp(0xec0007b2, 0x04514b5e); - write_iobp(0xec00078c, 0x40000200); - write_iobp(0xec000780, 0x02000020); + pch_iobp_update(0xea004001, ~(3 << 10), 1 << 10); + pch_iobp_update(0xeb004002, ~0, 1 << 30 | 1 << 21); + pch_iobp_update(0xec004002, ~0, 1 << 30 | 1 << 21); + pch_iobp_update(0xea004002, ~0, 1 << 22 | 1 << 21); + pch_iobp_update(0xea0040a1, ~0, 1 << 24); + pch_iobp_update(0xeb0040b1, ~0xffff, 0xc598); + pch_iobp_update(0xec0040b1, ~0xffff, 0xc598); + pch_iobp_update(0xeb0040b6, ~0xffff, 0xc598); + pch_iobp_update(0xea0000a9, ~(3 << 14), 2 << 14); + pch_iobp_update(0xea0001a9, ~(3 << 14), 2 << 14); + pch_iobp_update(0xeb0040b2, ~0xffff, 0xc396); + pch_iobp_update(0xeb0040b3, ~0xffff, 0xc396); + pch_iobp_update(0xec0040b2, ~0xffff, 0xc396); + + /* Assumes SATA direct connect, trace length <= 3.5" */ + pch_iobp_update(0xea0001a9, ~(0x3ff << 3), 0x29f << 3); + pch_iobp_update(SATA_IOBP_SP0G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); + pch_iobp_update(0xea0000a9, ~(0x3ff << 3), 0x29f << 3); + pch_iobp_update(SATA_IOBP_SP1G3IR, ~(0xff << 16 | 0x3f << 8), 0x88 << 16 | 3 << 8); + + /* TODO: Needs special handling */ + pch_iobp_update(0xea007f05, 0, 0x00010642); + + pch_iobp_update(0xea0040b7, ~0xffff, 0xc91c); + pch_iobp_update(0xea0040b8, ~0xffff, 0xc91c); + pch_iobp_update(0xeb0040a1, ~0, 1 << 25); + pch_iobp_update(0xec0040a1, ~0, 1 << 25); + pch_iobp_update(0xea007f0a, ~0, 3 << 30); + + /* PPT A0 resume-only xHCI workaround goes here */ + + /* TODO: This section is PPT-only */ + pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); + pch_iobp_update(0xec000084, ~(1 << 31), 0); + pch_iobp_update(0xec000184, ~(1 << 31), 0); + pch_iobp_update(0xec000284, ~(1 << 31), 0); + pch_iobp_update(0xec000384, ~(1 << 31), 0); + pch_iobp_update(0xec000094, ~0, 0xf << 16); + pch_iobp_update(0xec000194, ~0, 0xf << 16); + pch_iobp_update(0xec000294, ~0, 0xf << 16); + pch_iobp_update(0xec000394, ~0, 0xf << 16); + pch_iobp_update(0xec000096, ~0x3ff, 1); + pch_iobp_update(0xec000196, ~0x3ff, 1); + pch_iobp_update(0xec000296, ~0x3ff, 1); + pch_iobp_update(0xec000396, ~0x3ff, 1); + pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); + pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); + pch_iobp_update(0xea00008d, ~0, 3 << 20); + pch_iobp_update(0xea00018d, ~0, 3 << 20); + + /* TODO: Figure out what these writes mean */ + pch_iobp_update(0xec0007b2, 0, 0x04514b5e); + pch_iobp_update(0xec00078c, 0, 0x40000200); + pch_iobp_update(0xec000780, 0, 0x02000020); } static void pch_enable_gbe(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b95134a504d693f8e6f2df35784bf75037b7b16 Gerrit-Change-Number: 49177 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Improve channel disable logic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45500 ) Change subject: nb/intel/sandybridge: Improve channel disable logic ...................................................................... nb/intel/sandybridge: Improve channel disable logic Do not consider the failed channel's SPDs in emergency mode. Also, force a full training if not resuming from S3 and the saved data indicates a channel has failed. Special care needs to be taken as the selected memory frequency could be raised after a channel has been disabled. Tested on Asus P8Z77-V LX2, with a good DIMM on channel 0 and a bad DIMM on channel 1. The failing channel causes errors when discovering timB, and emergency mode raminit for the other channel is good enough to boot. With this commit: a. Regular boots always result in full training. b. The board still boots, as emergency raminit trained the good DIMM. c. S3 resume still works in all tested configurations. d. If pretending the bad DIMM is slower: 1. The MPLL gets locked at the slow frequency of the bad DIMM. 2. The first raminit attempt still fails miserably on the bad DIMM. 3. Emergency mode uses the frequency the MPLL is locked at. 4. The board boots with the good DIMM running at the slow frequency. With good DIMMs on both channels, everything works the same as before. Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 38 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45500/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 319fea3..51c57c6 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -43,15 +43,7 @@ /* Disable a channel in ramctr_timing */ static void disable_channel(ramctr_timing *ctrl, int channel) { - ctrl->rankmap[channel] = 0; - - memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); - - ctrl->channel_size_mb[channel] = 0; - ctrl->cmd_stretch[channel] = 0; - ctrl->mad_dimm[channel] = 0; - memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); - memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); + ctrl->failed_channels |= BIT(channel); } static bool nb_supports_ecc(const uint32_t capid0_a) @@ -163,6 +155,10 @@ FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; + /* Skip decoding the SPDs of failed channels */ + if (ctrl->failed_channels & BIT(channel)) + continue; + ch_dimms = 0; /* Count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { @@ -345,8 +341,21 @@ system_reset(); } + /* + * Discard the saved data if it is from raminit emergency mode. + * Ideally, we would not advertise support for ACPI S3 in such + * cases, because there is evidence that the RAM has stability + * problems. Until then, skip this sanity check on S3 resumes. + */ + if (!s3resume && ctrl_cached && ctrl_cached->failed_channels) { + printk(BIOS_ERR, "Stored timings indicate channels have failed.\n"); + + ctrl_cached = NULL; + } + /* Verify MRC cache for fast boot */ if (!s3resume && ctrl_cached) { + /* Load SPD unique information data. */ memset(spds, 0, sizeof(spds)); mainboard_get_spd(spds, 1); @@ -391,6 +400,13 @@ } if (err) { + /* + * We can't reinitialize the DRAM MPLL at a different frequency. + * As we want to ignore the SPDs on the failed channel, we have + * to use the same tCK in emergency mode to avoid some troubles. + */ + const u32 old_tCK = ctrl.tCK; + /* Fallback: disable failing channel */ printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); printram("Disable failing channel.\n"); @@ -398,12 +414,15 @@ /* Reset internal state */ reinit_ctrl(&ctrl, cpuid); - /* Reset DDR3 frequency */ - dram_find_spds_ddr3(spds, &ctrl); - /* Disable failing channel */ disable_channel(&ctrl, GET_ERR_CHANNEL(err)); + /* Restore tCK */ + ctrl.tCK = old_tCK; + + /* Recalculate DDR3 frequency */ + dram_find_spds_ddr3(spds, &ctrl); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); } diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 32f2b44..cf3d6a9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -105,7 +105,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 typedef struct odtmap_st { u16 rttwr; @@ -185,6 +185,9 @@ /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ u16 mdll_wake_delay; + /* Bitmap of channels that have failed */ + u8 failed_channels; + u8 rankmap[NUM_CHANNELS]; int ref_card_offset[NUM_CHANNELS]; u32 mad_dimm[NUM_CHANNELS]; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index c23a5ac..a469910 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -265,7 +265,9 @@ printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); - ctrl->tCK = get_mem_min_tck(); + /* In emergency mode, use provided tCK if non-zero. Otherwise, calculate it. */ + if (!ctrl->failed_channels || !ctrl->tCK) + ctrl->tCK = get_mem_min_tck(); /* Find CAS latency */ while (1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/45500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d34594561680906cb0b15a9c6a5fa7a773c0496 Gerrit-Change-Number: 45500 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49169 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function ...................................................................... [UNTESTED] sb/intel/bd82x6x: Clean up `early_pch_init` function It was being run twice, in both bootblock and romstage. Using Lynxpoint as a reference, reorder the code so that it is only run once. Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 37 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/49169/1 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..f594a9f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,8 +3,15 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <types.h> + #include "pch.h" +static void map_rcba(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +} + static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -33,13 +40,14 @@ void bootblock_early_southbridge_init(void) { + map_rcba(); enable_spi_prefetching_and_caching(); - - early_pch_init(); - enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); + + pch_enable_lpc_decode(); + mainboard_pch_lpc_setup(); } diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 6daafe0..f684a96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -216,26 +216,6 @@ write_iobp(0xec000780, 0x02000020); } -static void pch_enable_bars(void) -{ - pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); - - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - - /* Enable GPIO functionality. */ - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -} - -static void pch_generic_setup(void) -{ - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ -} - static void pch_enable_gbe(void) { uint8_t wanted_buc; @@ -260,7 +240,27 @@ } } -static void pch_enable_lpc_decode(void) +static void pch_enable_bars(void) +{ + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); + + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); + + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + + /* Enable GPIO functionality. */ + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); +} + +static void pch_generic_setup(void) +{ + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ +} + +void pch_enable_lpc_decode(void) { /* * Enable some common LPC IO ranges: @@ -298,18 +298,13 @@ void early_pch_init(void) { - pch_enable_lpc_decode(); - - mainboard_pch_lpc_setup(); + pch_enable_gbe(); pch_enable_bars(); - pch_generic_setup(); - - pch_enable_gbe(); - setup_pch_gpios(&mainboard_gpio_map); - if (ENV_ROMSTAGE) - enable_smbus(); + pch_generic_setup(); + + enable_smbus(); } diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index dcab839..3b91e31 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,6 +56,7 @@ /* Optional mainboard hook to do additional LPC configuration or to override what is set up by default. */ void mainboard_pch_lpc_setup(void); +void pch_enable_lpc_decode(void); void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia77042c0640929cec05fdd9a9f8c7235fdfe8390 Gerrit-Change-Number: 49169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49178 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic ...................................................................... [UNTESTED] sb/intel/bd82x6x: Account for PCH type in IOBP magic The initial steps came out of trace output from a Panther Point system. Add missing Cougar Point steps, and guard Panther Point specific steps. Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 33 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/49178/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0b60d13..e86297b 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -156,7 +156,10 @@ pch_iobp_update(0xeb0040a1, ~(0x3ff << 3), 0x9f << 3); pch_iobp_update(0xec0040a1, ~(0x3ff << 3), 0x9f << 3); - /* Some CPT-only writes go here */ + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec004086, ~0, 1 << 30); + pch_iobp_update(0xec004086, ~0, 1 << 31); + } pch_iobp_update(0xea004001, ~(3 << 10), 1 << 10); pch_iobp_update(0xeb004002, ~0, 1 << 30 | 1 << 21); @@ -189,34 +192,35 @@ /* PPT A0 resume-only xHCI workaround goes here */ - /* TODO: This section is PPT-only */ - pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); - pch_iobp_update(0xec000084, ~(1 << 31), 0); - pch_iobp_update(0xec000184, ~(1 << 31), 0); - pch_iobp_update(0xec000284, ~(1 << 31), 0); - pch_iobp_update(0xec000384, ~(1 << 31), 0); - pch_iobp_update(0xec000094, ~0, 0xf << 16); - pch_iobp_update(0xec000194, ~0, 0xf << 16); - pch_iobp_update(0xec000294, ~0, 0xf << 16); - pch_iobp_update(0xec000394, ~0, 0xf << 16); - pch_iobp_update(0xec000096, ~0x3ff, 1); - pch_iobp_update(0xec000196, ~0x3ff, 1); - pch_iobp_update(0xec000296, ~0x3ff, 1); - pch_iobp_update(0xec000396, ~0x3ff, 1); - pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); - pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); - pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); - pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); - pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); - pch_iobp_update(0xea00008d, ~0, 3 << 20); - pch_iobp_update(0xea00018d, ~0, 3 << 20); + if (pch_silicon_type() == PCH_TYPE_CPT) { + pch_iobp_update(0xec00404d, ~(0xff3f << 8), 0xff17 << 8); + pch_iobp_update(0xec000084, ~(1 << 31), 0); + pch_iobp_update(0xec000184, ~(1 << 31), 0); + pch_iobp_update(0xec000284, ~(1 << 31), 0); + pch_iobp_update(0xec000384, ~(1 << 31), 0); + pch_iobp_update(0xec000094, ~0, 0xf << 16); + pch_iobp_update(0xec000194, ~0, 0xf << 16); + pch_iobp_update(0xec000294, ~0, 0xf << 16); + pch_iobp_update(0xec000394, ~0, 0xf << 16); + pch_iobp_update(0xec000096, ~0x3ff, 1); + pch_iobp_update(0xec000196, ~0x3ff, 1); + pch_iobp_update(0xec000296, ~0x3ff, 1); + pch_iobp_update(0xec000396, ~0x3ff, 1); + pch_iobp_update(0xec000001, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000101, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000201, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec000301, ~0, 3 << 10 | 1 << 3); + pch_iobp_update(0xec0040b5, ~0xffff, 0xc518); + pch_iobp_update(0xec000087, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000187, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000287, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xec000387, ~(0xf << 8), 5 << 8); + pch_iobp_update(0xea000050, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xea000150, ~(0xff << 16), 0xbb << 16); + pch_iobp_update(0xec007f60, ~(0xf << 8), 0xd << 8); + pch_iobp_update(0xea00008d, ~0, 3 << 20); + pch_iobp_update(0xea00018d, ~0, 3 << 20); + } /* TODO: Figure out what these writes mean */ pch_iobp_update(0xec0007b2, 0, 0x04514b5e); -- To view, visit https://review.coreboot.org/c/coreboot/+/49178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2569f9c436f545a5e3ffda5a31ab27c27469f540 Gerrit-Change-Number: 49178 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49181 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge ...................................................................... [UNTESTED] sb/intel/bd82x6x: Get DMI TC/VC mapping from northbridge Both ends of the DMI link must use the same TC/VC mapping. Since the register values are identical, pass the northbridge values as parameters and have the southbridge code use them. This prevents any inconsistency. Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/early_dmi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 27 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49181/1 diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index bcf3e4c..7d536b5 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -180,26 +180,33 @@ printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* - * Virtual Channel resources must match settings in RCBA! - * * Channel Vp and Vm are documented in: * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel Pentium * Processor Family, and Desktop Intel Celeron Processor Family Vol. 2" */ - /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0 */ + const u32 vc0 = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1 */ + const u32 vc1 = (1 << 31) | (1 << 24) | (0x11 << 1); + + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + const u32 vcp = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + const u32 vcm = (1 << 31) | (7 << 24) | (0x40 << 1); + + DMIBAR32(DMIVC0RCTL) = vc0; + DMIBAR32(DMIVC1RCTL) = vc1; + DMIBAR32(DMIVCPRCTL) = vcp; + DMIBAR32(DMIVCMRCTL) = vcm; /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1; - early_pch_init_native_dmi_post(); + /* Ensure the PCH side uses the same virtual channel settings */ + early_pch_init_native_dmi_post(vc0, vc1, vcp, vcm); /* * BIOS Requirement: Check if DMI VC Negotiation was successful. diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 251ff86..eac8e1f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -28,7 +28,7 @@ RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2; } -void early_pch_init_native_dmi_post(void) +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm) { u32 reg32; @@ -42,47 +42,21 @@ RCBA8(UPDCR) = RCBA8(UPDCR) | 1 << 2 | 1 << 0; - /* - * Virtual Channel resources must match settings in DMIBAR! - * - * Some of the following settings are taken from - * "Intel Core i5-600, i3-500 Desktop Processor Series and Intel - * Pentium Desktop Processor 6000 Series Vol. 2" datasheet and - * serialice traces. - */ + /* Virtual Channel 0 */ + RCBA32(V0CTL) = vc0; - /* Virtual Channel 0 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC0 and TC3 and TC4 to VC0. - */ - - RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - - /* Virtual Channel 1 Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC1 and TC5 to VC1. - */ - RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Virtual Channel 1 */ + RCBA32(V1CTL) = vc1; /* Read back register */ RCBA32(V1CTL); - /* Virtual Channel private Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC2 and TC6 to VCp. - */ - RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Virtual Channel private */ + RCBA32(CIR31) = vcp; /* Read back register */ RCBA32(CIR31); - /* Virtual Channel ME Resource Control Register. - * Enable channel. - * Set Virtual Channel Identifier. - * Map TC7 to VCm. - */ - RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1); + /* Virtual Channel ME */ + RCBA32(CIR32) = vcm; /* Lock Virtual Channel Resource control register. */ RCBA32(CIR0) |= TCLOCKDN; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 42c56a2..5eaaf51 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -63,7 +63,7 @@ void early_pch_init_native(void); void early_pch_init(void); void early_pch_init_native_dmi_pre(void); -void early_pch_init_native_dmi_post(void); +void early_pch_init_native_dmi_post(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm); struct southbridge_usb_port { -- To view, visit https://review.coreboot.org/c/coreboot/+/49181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598cd5b6bd1af22ee2ae25a4f29cae381116bd5d Gerrit-Change-Number: 49181 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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