Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64735 )
Change subject: cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD
......................................................................
cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD
There are too many "FIT" in firmware land. In order to reduce possible
confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this
patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool
argument, so calling scripts will now need to replace `-t fit` with `-t
fit_payload`).
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
---
M src/arch/arm/boot.c
M src/arch/riscv/boot.c
M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
M src/lib/prog_loaders.c
M src/security/tpm/tspi/crtm.c
M util/cbfstool/cbfs.h
M util/cbfstool/cbfstool.c
M util/nvramtool/cbfs.h
8 files changed, 16 insertions(+), 16 deletions(-)
Approvals:
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c
index b18473b..7d9f960 100644
--- a/src/arch/arm/boot.c
+++ b/src/arch/arm/boot.c
@@ -13,7 +13,7 @@
cache_sync_instructions();
switch (prog_cbfs_type(prog)) {
- case CBFS_TYPE_FIT:
+ case CBFS_TYPE_FIT_PAYLOAD:
/*
* We only load Linux payloads from the ramstage, so provide a hint to
* the linker that the below functions do not need to be included in
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 119039d..a59f9d1 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -27,7 +27,7 @@
struct prog *prog = args->prog;
void *fdt = HLS()->fdt;
- if (prog_cbfs_type(prog) == CBFS_TYPE_FIT)
+ if (prog_cbfs_type(prog) == CBFS_TYPE_FIT_PAYLOAD)
fdt = prog_entry_arg(prog);
if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
index dc80ed0..be5c9cd 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
@@ -23,7 +23,7 @@
CBFS_TYPE_LEGACY_STAGE = 0x10,
CBFS_TYPE_STAGE = 0x11,
CBFS_TYPE_SELF = 0x20,
- CBFS_TYPE_FIT = 0x21,
+ CBFS_TYPE_FIT_PAYLOAD = 0x21,
CBFS_TYPE_OPTIONROM = 0x30,
CBFS_TYPE_BOOTSPLASH = 0x40,
CBFS_TYPE_RAW = 0x50,
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 0b68805..0139ca4 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -160,7 +160,7 @@
case CBFS_TYPE_SELF: /* Simple ELF */
selfload_mapped(payload, mapping, BM_MEM_RAM);
break;
- case CBFS_TYPE_FIT: /* Flattened image tree */
+ case CBFS_TYPE_FIT_PAYLOAD: /* Flattened image tree */
if (CONFIG(PAYLOAD_FIT_SUPPORT)) {
fit_payload(payload, mapping);
break;
diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c
index 41f6a94..24133d9 100644
--- a/src/security/tpm/tspi/crtm.c
+++ b/src/security/tpm/tspi/crtm.c
@@ -131,7 +131,7 @@
case CBFS_TYPE_MRC:
case CBFS_TYPE_STAGE:
case CBFS_TYPE_SELF:
- case CBFS_TYPE_FIT:
+ case CBFS_TYPE_FIT_PAYLOAD:
pcr_index = TPM_CRTM_PCR;
break;
default:
diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 21a5d6f..e1f705e 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -33,7 +33,7 @@
{CBFS_TYPE_CBFSHEADER, "cbfs header"},
{CBFS_TYPE_STAGE, "stage"},
{CBFS_TYPE_SELF, "simple elf"},
- {CBFS_TYPE_FIT, "fit"},
+ {CBFS_TYPE_FIT_PAYLOAD, "fit_payload"},
{CBFS_TYPE_OPTIONROM, "optionrom"},
{CBFS_TYPE_BOOTSPLASH, "bootsplash"},
{CBFS_TYPE_RAW, "raw"},
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index cebfef6..b2d5cdb 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -1196,7 +1196,7 @@
if (ret != 0) {
ret = parse_fit_to_payload(buffer, &output, param.compression);
if (ret == 0)
- header->type = htobe32(CBFS_TYPE_FIT);
+ header->type = htobe32(CBFS_TYPE_FIT_PAYLOAD);
}
/* If it's not an FIT, see if it's a UEFI FV */
diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h
index 35b98cf..0bded53 100644
--- a/util/nvramtool/cbfs.h
+++ b/util/nvramtool/cbfs.h
@@ -24,15 +24,15 @@
Users are welcome to use any other value for their
components */
-#define CBFS_TYPE_STAGE 0x10
-#define CBFS_TYPE_SELF 0x20
-#define CBFS_TYPE_FIT 0x21
-#define CBFS_TYPE_OPTIONROM 0x30
-#define CBFS_TYPE_BOOTSPLASH 0x40
-#define CBFS_TYPE_RAW 0x50
-#define CBFS_TYPE_VSA 0x51
-#define CBFS_TYPE_MBI 0x52
-#define CBFS_TYPE_MICROCODE 0x53
+#define CBFS_TYPE_STAGE 0x10
+#define CBFS_TYPE_SELF 0x20
+#define CBFS_TYPE_FIT_PAYLOAD 0x21
+#define CBFS_TYPE_OPTIONROM 0x30
+#define CBFS_TYPE_BOOTSPLASH 0x40
+#define CBFS_TYPE_RAW 0x50
+#define CBFS_TYPE_VSA 0x51
+#define CBFS_TYPE_MBI 0x52
+#define CBFS_TYPE_MICROCODE 0x53
#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
--
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Gerrit-Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a
Gerrit-Change-Number: 64735
Gerrit-PatchSet: 3
Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-MessageType: merged
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64877 )
Change subject: soc/intel/cmn/cse: Fix return type for `devfn`
......................................................................
soc/intel/cmn/cse: Fix return type for `devfn`
This patch fixes the return type for `devfn` variable inside
heci_set_to_d0i3(). `PCI_DEVFN` macro returns `unsigned int`
instead of `pci_devfn_t`.
TEST=Able to build and boot to ChromeOS without any failure.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ib3a575aa7d71cbe6932e823917b57c5558387433
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64877/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index e01b1cf..1c7e218 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1012,7 +1012,7 @@
void heci_set_to_d0i3(void)
{
for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) {
- pci_devfn_t devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i);
+ unsigned int devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i);
if (!is_cse_devfn_visible(devfn))
continue;
--
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Hello build bot (Jenkins), Sean Rhodes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64855
to look at the new patch set (#2).
Change subject: soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
......................................................................
soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
This patch implements heci_init() API that perform initialization of
all HECI devices as per MAX_HECI_DEVICES config.
BUG=none
TEST=Able to build and boot google/taeko with this change. No CSE
error observed with `heci_init()` called from romstage.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 47 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/64855/2
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Jeremy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63941 )
Change subject: mb/intel/adlrvp: Add 5G WWAN ACPI support for ADL-P RVP
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63941/comment/f5164fb9_70d5942a
PS3, Line 70: # register "reset_delay_ms" = "1000"
Why is this comment out ? If unnecessary it should just be removed.
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Jeremy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63947 )
Change subject: soc/intel/alderlake: Fixed for PCIe source clock assignment
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63947/comment/2528756a_4ea85042
PS6, Line 7: Fixed
Fix
https://review.coreboot.org/c/coreboot/+/63947/comment/c207609a_0e3501c9
PS6, Line 10: is
" is"
https://review.coreboot.org/c/coreboot/+/63947/comment/60903462_c73f065b
PS6, Line 10: false
invalid
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63947/comment/db0bf3aa_0f0a0916
PS6, Line 60: cfg[i].flags == 0
More C idiomatic for no bits set test would be !cfg[i].flags
https://review.coreboot.org/c/coreboot/+/63947/comment/8e59662a_1db1ec3c
PS6, Line 61: !
What do you think of "Missing clock structure definition for root port %d" ?
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Change subject: mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVP
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/intel/adlrvp/gpio.c:
https://review.coreboot.org/c/coreboot/+/63945/comment/d24d1c25_db4423fe
PS6, Line 189: // PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
you should remove this line altogether if unnecessary instead of commenting it out.
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Change subject: soc/intel/alderlake: add support for external source clock
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63943/comment/9523ad0e_a8887858
PS6, Line 9: includingsource
missing space.
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63943/comment/2a434b3e_fb4156f3
PS6, Line 239: default 10 if SOC_INTEL_ALDERLAKE_PCH_P
Why do you change the line ? Couldn't you just change the value ?
https://review.coreboot.org/c/coreboot/+/63943/comment/afa8610d_c2096abf
PS6, Line 241: 3
three
https://review.coreboot.org/c/coreboot/+/63943/comment/3a2049c1_e7140570
PS6, Line 241: clock
clocks
https://review.coreboot.org/c/coreboot/+/63943/comment/7c206f2d_f7fc217c
PS6, Line 242: This done
This is done
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CoolStar Organization has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50011 )
Change subject: [HACK][WIP] mb/google/zork: Remove all GPE wake sources
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
correct way to fix this is to remove the GPE and mark the GpioInt as either ExclusiveAndWake or SharedAndWake
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