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Change subject: soc/intel/adl: Add missing claimed memory regions
......................................................................
soc/intel/adl: Add missing claimed memory regions
This CL adds the missing regions from this list in the bug mentioned
below
The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently
marked as such in the system agent code. This CL adds the
following regions:
MMSPI
CRAB_ABORT
TPM
LT_SECURITY
APIC
MMCONF
DSM
TSEG
PMRR
GSM
DPR
BUG=b:149830546
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/include/soc/systemagent.h
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
6 files changed, 260 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64677/13
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64677
to look at the new patch set (#12).
Change subject: soc/intel/adl: Add missing claimed memory regions
......................................................................
soc/intel/adl: Add missing claimed memory regions
This CL adds the missing regions from this list in the bug mentioned
below
The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently
marked as such in the system agent code. This CL adds the
following regions:
MMSPI
CRAB_ABORT
TPM
LT_SECURITY
APIC
MMCONF
DSM
TSEG
PMRR
GSM
DPR
BUG=b:149830546
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/include/soc/systemagent.h
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
6 files changed, 263 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64677/12
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Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Angel Pons, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64677
to look at the new patch set (#11).
Change subject: soc/intel/adl: Add missing claimed memory regions
......................................................................
soc/intel/adl: Add missing claimed memory regions
This CL adds the missing regions from this list in the bug mentioned
below
The Alder Lake chipset has several more reserved memory regions that
are unavailable to the resource allocator than are currently
marked as such in the system agent code. This CL adds the
following regions:
MMSPI
CRAB_ABORT
TPM
LT_SECURITY
APIC
MMCONF
DSM
TSEG
PMRR
GSM
DPR
BUG=b:149830546
Change-Id: I80df95f9146934d6a2d23e525c22be3a9a7e2b9f
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/include/soc/systemagent.h
M src/soc/intel/alderlake/systemagent.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_def.h
6 files changed, 278 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/64677/11
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64846 )
Change subject: Documentation: Update coreboot 4.17 release notes
......................................................................
Patch Set 3: Code-Review+2
(5 comments)
File Documentation/releases/coreboot-4.17-relnotes.md:
https://review.coreboot.org/c/coreboot/+/64846/comment/19d52ea9_f3306b47
PS3, Line 11: successful
Add a dot.
https://review.coreboot.org/c/coreboot/+/64846/comment/c959f076_17306e12
PS3, Line 122:
nit: Add second empty line
https://review.coreboot.org/c/coreboot/+/64846/comment/c252712d_8b6749ea
PS3, Line 141: (because it is part of another firmware section (IFWI or a different
: CBFS), the CRTM measurement fails.
> A closing bracket is missing here.
I would replace the outer brackets with commas.
https://review.coreboot.org/c/coreboot/+/64846/comment/068ddc75_cc65b59b
PS3, Line 246:
nit: Add second empty line
https://review.coreboot.org/c/coreboot/+/64846/comment/2b5af0af_36c8b38c
PS3, Line 285: linux
nit: Uppercase L
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Change subject: drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver
......................................................................
Patch Set 3: Code-Review+1
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Change subject: Documentation/releases: Deprecate Intel Icelake SoC
......................................................................
Patch Set 2: Code-Review+2
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Change subject: Makefile.inc: Add bootblock to CBFS before others
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/64547/comment/4a6cfb9b_7ea6d549
PS2, Line 9: cbfstool
> > The problem is that it still needs to be updated again every time a new CBFS file is added. […]
Yes, I think that's exactly what it will need to have.
The way this works on Arm is that coreboot generates bootblock.raw.bin, then usually a platform-specific utility (this would roughly be the equivalent to your ifwitool, I think) transforms that into a bootblock.bin that wraps the code in the required platform-specific encoding including headers, checksums, etc. Finally the Makefiles copy that bootblock.bin into the BOOTBLOCK FMAP section.
cbfstool scans the whole FMAP section for the metadata hash magic number, so no matter how it is packaged, as long as it's not compressed or encrypted or anything it will find it. Then it can update the hash as needed. For cases where that area is covered by a checksum or something, there's a mechanism in cbfstool/platform_fixups.c to detect which kind of platform image it is and then update the necessary hashes.
This framework worked pretty well for the platforms we've tried for now (Qualcomm and MediaTek), since cbfstool doesn't need to know how to generate the whole platform-specific data structure from scratch, it just needs to know how to find and update any checksums in it. I hope this will transfer to the x86 cases as well. So you would still have your ifwitool or whatever to initially create the IFWI, but cbfstool would need to know how to recompute any checksums in it after it has updated it in-place. It would be nice if we could standardize on all these platforms using the name "BOOTBLOCK" for the FMAP section that contains the bootblock (even if it's technically an "IFWI" or whatever), but we can make cbfstool look for other sections too if necessary.
I think +Karthik has been looking into implementing this for AMD -- that one is definitely on our roadmap. For IFWI I was told that this only worked that way on APL/GLK, and starting with JSL the mechanism changed again to something more in line with the big core Intel chips (with bootblock in CBFS). Is that true? If so, I think we (Google) are currently not really planning to work on supporting CBFS verification for APL/GLK and expect the issue to just obsolete itself eventually. But if anyone else wants to implement support for it, they're of course welcome to do so.
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Change subject: mb/google/rex: Add entry stubs of each stage
......................................................................
Patch Set 14: Code-Review+2
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