coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

1 participants
1234 discussions

Change in coreboot[master]: util/cbfstool/elogtool.c: Convert args into struct in flashrom helper
by Edward O'Callaghan (Code Review) 01 Jun '22

01 Jun '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64880 ) Change subject: util/cbfstool/elogtool.c: Convert args into struct in flashrom helper ...................................................................... util/cbfstool/elogtool.c: Convert args into struct in flashrom helper vboot signatures for flashrom r/w helpers changed in the upstream commit bd2971326ee94fc5. Reflect the change here to allow vboot ref and coreboot to realign. BUG=b:207808292,b:231152447 BRANCH=none TEST=builds with vboot_ref uprev. Change-Id: Ie7e75065a76dc8523a2dfe8171e1c0dd1be7fa7e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M util/cbfstool/elogtool.c 1 file changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/64880/1 diff --git a/util/cbfstool/elogtool.c b/util/cbfstool/elogtool.c index 253e2ee..164c1d1 100644 --- a/util/cbfstool/elogtool.c +++ b/util/cbfstool/elogtool.c @@ -78,16 +78,16 @@ */ static int elog_read(struct buffer *buffer, const char *filename) { - if (filename == NULL) { - uint8_t *buf; - uint32_t buf_size; + struct firmware_image image = { + .programmer = FLASHROM_PROGRAMMER_INTERNAL_AP, + }; - if (flashrom_read(FLASHROM_PROGRAMMER_INTERNAL_AP, ELOG_RW_REGION_NAME, - &buf, &buf_size) != VB2_SUCCESS) { + if (filename == NULL) { + if (flashrom_read(&image, ELOG_RW_REGION_NAME) != VB2_SUCCESS) { fprintf(stderr, "Could not read RW_ELOG region using flashrom\n"); return ELOGTOOL_EXIT_READ_ERROR; } - buffer_init(buffer, NULL, buf, buf_size); + buffer_init(buffer, NULL, image.data, image.size); } else if (buffer_from_file(buffer, filename) != 0) { fprintf(stderr, "Could not read input file: %s\n", filename); return ELOGTOOL_EXIT_READ_ERROR; @@ -108,9 +108,14 @@ */ static int elog_write(struct buffer *buf, const char *filename) { + struct firmware_image image = { + .programmer = FLASHROM_PROGRAMMER_INTERNAL_AP, + .data = buffer_get(buf), + .size = buffer_size(buf), + }; + if (filename == NULL) { - if (flashrom_write(FLASHROM_PROGRAMMER_INTERNAL_AP, ELOG_RW_REGION_NAME, - buffer_get(buf), buffer_size(buf)) != VB2_SUCCESS) { + if (flashrom_write(&image, ELOG_RW_REGION_NAME) != VB2_SUCCESS) { fprintf(stderr, "Failed to write to RW_ELOG region using flashrom\n"); return ELOGTOOL_EXIT_WRITE_ERROR; -- To view, visit https://review.coreboot.org/c/coreboot/+/64880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7e75065a76dc8523a2dfe8171e1c0dd1be7fa7e Gerrit-Change-Number: 64880 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: commonlib: Clean up compiler.h
by Yu-Ping Wu (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Philipp Hug, Patrick Georgi, Jakub Czapiga, Julius Werner, ron minnich. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64737 ) Change subject: commonlib: Clean up compiler.h ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b Gerrit-Change-Number: 64737 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jun 2022 01:23:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/corsola: Enable ps8640 for steelix
by wen zhang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: zanxi chen. wen zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64790 ) Change subject: mb/google/corsola: Enable ps8640 for steelix ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549 Gerrit-Change-Number: 64790 Gerrit-PatchSet: 3 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Jun 2022 01:13:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Reka Norman (Code Review) 01 Jun '22

01 Jun '22

Reka Norman has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Reka Norman (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Arthur Heymans, Eric Lai, Kyösti Mälkki, Felix Held. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Reboot and suspend are working again a few builds later. […] It was CB:63475 that fixed it. -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jun 2022 00:49:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/acpi: Rework to reduce code duplication
by Abel Briggs (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Wonkyu Kim, Subrata Banik, Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Reka Norman, Mario Scheithauer, Angel Pons, Julius Werner, Arthur Heymans, Karthikeyan Ramasubramanian. Abel Briggs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64012 ) Change subject: ec/acpi: Rework to reduce code duplication ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > Abel, can you add a topic on your EC patch train? Will be easier to track. Done - topic is now "ec-cleanup". -- To view, visit https://review.coreboot.org/c/coreboot/+/64012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda5c030ff81f1046be58aa1fcafdcf71a27cd41 Gerrit-Change-Number: 64012 Gerrit-PatchSet: 10 Gerrit-Owner: Abel Briggs <abelbriggs1(a)hotmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Jun 2022 00:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Docs/relnotes-4.17: Fix typo
by Martin L Roth (Code Review) 01 Jun '22

01 Jun '22

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/64549 ) Change subject: Docs/relnotes-4.17: Fix typo ...................................................................... Abandoned fixed in release notes before merge. -- To view, visit https://review.coreboot.org/c/coreboot/+/64549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If844d07853cdbaf8bcf3cf21f72952273c5728b5 Gerrit-Change-Number: 64549 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: Documentation: Update coreboot 4.17 release notes
by Martin L Roth (Code Review) 01 Jun '22

01 Jun '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64846 ) Change subject: Documentation: Update coreboot 4.17 release notes ...................................................................... Documentation: Update coreboot 4.17 release notes These are the final release notes before the release. They will be updated immediately following the release with final numbers and the commit ids that the release spans. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Id9491ad9aa6ab3eb5504bee85591f3b1d9bf6cc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/releases/coreboot-4.17-relnotes.md 1 file changed, 325 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.17-relnotes.md b/Documentation/releases/coreboot-4.17-relnotes.md index bb55d7f..d8b343d 100644 --- a/Documentation/releases/coreboot-4.17-relnotes.md +++ b/Documentation/releases/coreboot-4.17-relnotes.md @@ -1,20 +1,50 @@ -Upcoming release - coreboot 4.17 -================================ +coreboot 4.17 +======================================================================== -The 4.17 release is planned for May, 2022. -We are continuing the quarterly release cadence in order to enable others to -release quarterly on a fresher version of coreboot. +The coreboot 4.17 release is being done on June 1, 2022. -Update this document with changes that should be in the release notes. +Since the 4.16 release, we've had over 1260 new commits by around 150 +contributors. Of those people, roughly 15 were first-time contributors. -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +As always, we appreciate everyone who has contributed and done the hard +work to make the coreboot project successful. -Significant changes -------------------- + +Major Bugfixes in this release +------------------------------ +* [CVE-2022-29264](https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-292… + + +New Mainboards +-------------- + +* Clevo L140MU / L141MU / L142MU +* Dell Precision T1650 +* Google Craask +* Google Gelarshie +* Google Kuldax +* Google Mithrax +* Google Osiris +* HP Z220 CMT Workstation +* Star Labs LabTop Mk III (i7-8550u) +* Star Labs LabTop Mk IV (i3-10110U and i7-10710U) +* Star Labs Lite Mk III (N5000) +* Star Labs Lite Mk IV (N5030) + + +Removed Mainboards +------------------ + +* Google Deltan +* Google Deltaur + +Significant or interesting changes +---------------------------------- + +These changes are a few that were selected as a sampling of particularly +interesting commits. + ### CBMEM init hooks changed @@ -22,20 +52,295 @@ * CBMEM_CREATION_HOOK: Used only in the first stage that creates cbmem, typically romstage. For instance code that migrates data from cache as ram to dram would use this hook. -* CBMEM_READY_HOOK: Used in every stage that has cbmeme. An example would - initializing the cbmem console by appending to what previous stages +* CBMEM_READY_HOOK: Used in every stage that has cbmem. An example would + be initializing the cbmem console by appending to what previous stages logged. -This reason for this change is improved flexibility with regards to which +The reason for this change is improved flexibility with regards to which stage initializes cbmem. + ### Payloads + * SeaBIOS: Update stable release from 1.14.0 to 1.16.0 * iPXE: Update stable release from 2019.3 to 2022.1 -* Add new coreDOOM payload, a port of Doom to libpayload * Add "GRUB2 atop SeaBIOS" aka "SeaGRUB" option, which builds GRUB2 as a - secondary payload for SeaBIOS with the GRUB2 set as the default boot entry. - This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as a fallback - method to access hardware that the native GRUB2 payload cannot access. + secondary payload for SeaBIOS with GRUB2 set as the default boot + entry. This allows GRUB2 to use BIOS callbacks provided by SeaBIOS as + a fallback method to access hardware that the native GRUB2 payload + cannot access. * Add option to build SeaBIOS and GRUB2 as secondary payloads +* Add new coreDOOM payload. See commit message below. -### Add significant changes here + +### payloads/external: Add support for coreDOOM payload + +coreDOOM is a port of DOOM to libpayload, based on the doomgeneric +source port. It renders the game to the coreboot linear framebuffer, +and loads WAD files from CBFS. + + +### cpu/x86/smm_module_load: Rewrite setup_stub + +This code was hard to read as it did too much and had a lot of state +to keep track of. + +It also looks like the staggered entry points were first copied and +only later the parameters of the first stub were filled in. This +means that only the BSP stub is actually jumping to the permanent +smihandler. On the APs the stub would jump to wherever c_handler +happens to point to, which is likely 0. This effectively means that on +APs it's likely easy to have arbitrary code execution in SMM which is a +security problem. + +Note: This patch fixes CVE-2022-29264 for the 4.17 release. + + +### cpu/x86/smm_module_loader.c: Rewrite setup + +This code is much easier to read if one does not have to keep track of +mutable variables. + +This also fixes the alignment code on the TSEG smihandler setup code. +It was aligning the code upwards instead of downwards which would cause +it to encroach a part of the save state. + + +### cpu/x86/smm: Add sinkhole mitigation to relocatable smmstub + +The sinkhole exploit exists in placing the lapic base such that it +messes with GDT. This can be mitigated by checking the lapic MSR +against the current program counter. + + +### cpu/x86/64bit: Generate static page tables from an assembly file + +This removes the need for a tool to generate simple identity pages. +Future patches will link this page table directly into the stages on +some platforms so having an assembly file makes a lot of sense. + +This also optimizes the size of the page of each 4K page by placing +the PDPE_table below the PDE. + + +### cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI + +This change will allow the SMI handler to write to the cbmem console +buffer. Normally SMIs can only be debugged using some kind of serial +port (UART). By storing the SMI logs into cbmem we can debug SMIs using +'cbmem -1'. Now that these logs are available to the OS we could also +verify there were no errors in the SMI handler. + +Since SMM can write to all of DRAM, we can't trust any pointers +provided by cbmem after the OS has booted. For this reason we store the +cbmem console pointer as part of the SMM runtime parameters. The cbmem +console is implemented as a circular buffer so it will never write +outside of this area. + + +### security/tpm/crtm: Add a function to measure the bootblock on SoC level + +On platforms where the bootblock is not included in CBFS anymore +because it is part of another firmware section (IFWI or a different +CBFS), the CRTM measurement fails. + +This patch adds a new function to provide a way at SoC level to measure +the bootblock. Following patches will add functionality to retrieve the +bootblock from the SoC related location and measure it from there. +In this way the really executed code will be measured. + + +### soc/amd/common/block/psp: Add platform secure boot support + +Add Platform Secure Boot (PSB) enablement via the PSP if it is not +already enabled. Upon receiving psb command, PSP will program PSB fuses +as long as BIOS signing key token is valid. +Refer to the AMD PSB user guide doc# 56654, Revision# 1.00. +Unfortunately this document is only available with NDA customers. + + +### drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler + +This patch implements coreboot native debug handler to manage the FSP +event messages. + +'FSP Event Handlers' feature introduced in FSP to generate event +messages to aid in the debugging of firmware issues. This eliminates +the need for FSP to directly write debug messages to the UART and FSP +might not need to know the board related UART port configuration. +Instead FSP signals the bootloader to inform it of a new debug message. +This allows the coreboot to provide board specific methods of reporting +debug messages, example: legacy UART or LPSS UART etc. + +This implementation has several advantages as: +1. FSP relies on XIP 'DebugLib' driver even while printing FSP-S debug + messages, hence, without ROM being cached, post 'romstage' would + results into sluggish boot with FSP debug enabled. + This patch utilities coreboot native debug implementation which is + XIP during FSP-M and relocatable to DRAM based resource for FSP-S. + +2. This patch simplifies the FSP DebugLib implementation and remove the + need to have serial port library. Instead coreboot 'printk' can be + used for display FSP serial messages. Additionally, unifies the debug + library between coreboot and FSP. + +3. This patch is also useful to get debug prints even with FSP + non-serial image (refer to 'Note' below) as FSP PEIMs are now + leveraging coreboot debug library instead FSP 'NULL' DebugLib + reference for release build. + +4. Can optimize the FSP binary size by removing the DebugLib dependency + from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary + size is reduced by ~100KB+ and FSP-S debug library size is also + reduced by ~300KB+ (FSP-S debug and release binary size is exactly + same with this code changes). The total savings is ~400KB for each + FSP copy, and in case of Chrome AP firmware with 3 copies, the total + savings would be 400KB * 3 = ~1.2MB. + +Note: Need to modify FSP source code to remove 'MDEPKG_NDEBUG' as +compilation flag for release build and generate FSP binary with non-NULL +FSP debug wrapper module injected (to allow FSP event handler to execute +even with FSP non-serial image) in the final FSP.fd. + + +### security/tpm: Add vendor-specific tis functions to read/write TPM regs + +In order to abstract bus-specific logic from TPM logic, the prototype +for two vendor-specific tis functions are added in this +patch. tis_vendor_read() can be used to read directly from TPM +registers, and tis_vendor_write() can be used to write directly to TPM +registers. + + +### arch/x86: Add support for catching null dereferences through debug regs + +This commit adds support for catching null dereferences and execution +through x86's debug registers. This is particularly useful when running +32-bit coreboot as paging is not enabled to catch these through page +faults. This commit adds three new configs to support this feature: +DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and +DEBUG_NULL_DEREF_HALT. + + +### drivers/i2c/generic: Add support for i2c device detection + +Add 'detect' flag which can be attached to devices which may or may not +be present at runtime, and for which coreboot should probe the i2c bus +to confirm device presence prior to adding an entry for it in the SSDT. + +This is useful for boards which may utilize touchpads/touchscreens from +multiple vendors, so that only the device(s) present are added to the +SSDT. This relieves the burden from the OS to detect/probe if a device +is actually present and allows the OS to trust the ACPI _STA value. + + +### util/cbmem: Add FlameGraph-compatible timestamps output + +Flame graphs are used to visualize hierarchical data, like call stacks. +Timestamps collected by coreboot can be processed to resemble +profiler-like output, and thus can be feed to flame graph generation +tools. + +Generating flame graph using https://github.com/brendangregg/FlameGraph: +``` + cbmem -S > trace.txt + FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg +``` + + +### src/console/Kconfig: Add option to disable loglevel prefix + +This patch adds an option to disable loglevel prefixes. This patch helps +to achieve clear messages when low loglevel is used and very few +messages are displayed on a terminal. This option also allows to +maintain compatibility with log readers and continuous integration +systems that depend on fixed log content. + +If the code contains: + printk(BIOS_DEBUG, "This is a debug message!\n") +it will show as: + [DEBUG] This is a debug message! +but if the Kconfig contains: + CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n +the same message will show up as + This is a debug message! + + +### util/cbmem: add an option to append timestamp + +Add an option to the cbmem utility that can be used to append an entry +to the cbmem timestamp table from userspace. This is useful for +bookkeeping of post-coreboot timing information while still being able +to use cbmem-based tooling for processing the generated data. + + +`-a | --add-timestamp ID: append timestamp with ID\n` + + +Additional changes +------------------ + +The following are changes across a number of patches, or changes worth +noting, but not needing a full description. + +* As always, general documentation, code cleanup, and refactoring +* Remove doxygen config files and targets +* Get clang compile working for all x86 platforms +* Work on updating checkpatch to match the current Linux version +* Timestamps: Rename timestamps to make names more consistent +* Continue updating ACPI code to ASL 2.0 +* Remove redundant or unnecessary headers from C files +* arch/x86/acpi_bert_storage.c: Use a common implementation +* Postcar stage improvements +* arch/x86/acpi: Consolidate POST code handling +* intel/common: Enable ROM caching in ramstage +* vendorcode/amd/agesa: Fix improper use of .data (const is important) +* sandybridge & gm45: Support setting PCI bars above 4G + + +Plans for Code Deprecation +-------------------------- + + +### Intel Icelake + +Intel Icelake is unmaintained. Also, the only user of this platform ever was +the CRB board. From the looks of it the code never was ready for production as +only engineering sample CPUIDs are supported. + +Thus, to reduce the maintanence overhead for the community, it is deprecated +from this release on and support for the following components will be dropped +with the release 4.19. + + * Intel Icelake SoC + * Intel Icelake RVP mainboard + + +### LEGACY_SMP_INIT + +As of release 4.18 (August 2022) we plan to deprecate LEGACY_SMP_INIT. +This also includes the codepath for SMM_ASEG. This code is used to start +APs and do some feature programming on each AP, but also set up SMM. +This has largely been superseded by PARALLEL_MP, which should be able to +cover all use cases of LEGACY_SMP_INIT, with little code changes. The +reason for deprecation is that having 2 codepaths to do the virtually +the same increases maintenance burden on the community a lot, while also +being rather confusing. + +No platforms in the tree have any hardware limitations that would block +migrating to PARALLEL_MP / a simple !CONFIG_SMP codebase. + + +Statistics +---------- + +- Total Commits: 1261 +- Average Commits per day: 13.26 +- Total lines added: 42535 +- Average lines added per commit: 33.73 +- Number of patches adding more than 100 lines: 51 +- Average lines added per small commit: 21.00 +- Total lines removed: 65961 +- Average lines removed per commit: 52.31 +- Total difference between added and removed: -23426 +- Total authors: 146 +- New authors: 17 -- To view, visit https://review.coreboot.org/c/coreboot/+/64846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9491ad9aa6ab3eb5504bee85591f3b1d9bf6cc2 Gerrit-Change-Number: 64846 Gerrit-PatchSet: 6 Gerrit-Owner: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Documentation: Update index.md and add 4.18 release notes
by Martin L Roth (Code Review) 01 Jun '22

01 Jun '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64843 ) Change subject: Documentation: Update index.md and add 4.18 release notes ...................................................................... Documentation: Update index.md and add 4.18 release notes Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I52814ebbae804ea0ff24a7cec0618054029b8b47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- A Documentation/releases/coreboot-4.18-relnotes.md M Documentation/releases/index.md 2 files changed, 58 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.18-relnotes.md b/Documentation/releases/coreboot-4.18-relnotes.md new file mode 100644 index 0000000..cfa47ed --- /dev/null +++ b/Documentation/releases/coreboot-4.18-relnotes.md @@ -0,0 +1,56 @@ +Upcoming release - coreboot 4.18 +================================ + +The 4.18 release is planned for August 2022. + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here + + + + + + + + + + + +Plans for Code Deprecation +-------------------------- + + +### Intel Icelake + +Intel Icelake code will be removed following the 4.19 release, planned +for November 2022. This consists of the Intel Icelake SOC and Intel +Icelake RVP mainboard + +Intel Icelake is unmaintained. Also, the only user of this platform ever +was the CRB board. From the looks of it the code never was ready for +production as only engineering sample CPUIDs are supported. This reduces +the maintanence overhead for the coreboot project. + + +### LEGACY_SMP_INIT + +Legacy SMP init will be removed from the coreboot master branch +immediately following this release. Anyone looking for the latest +version of the code should find it on the 4.18 branch. + +This also includes the codepath for SMM_ASEG. This code is used to start +APs and do some feature programming on each AP, but also set up SMM. +This has largely been superseded by PARALLEL_MP, which should be able to +cover all use cases of LEGACY_SMP_INIT, with little code changes. The +reason for deprecation is that having 2 codepaths to do the virtually +the same increases maintenance burden on the community a lot, while also +being rather confusing. diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 91710f1..f1326b6 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -3,7 +3,7 @@ ## Upcoming release Please add to the release notes as changes are added: -* [4.17 - May 2022](coreboot-4.17-relnotes.md) +* [4.18 - Aug 2022](coreboot-4.18-relnotes.md) The [checklist] contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -15,6 +15,7 @@ ## Previous releases +* [4.17 - May 2022](coreboot-4.17-relnotes.md) * [4.16 - Feb 2022](coreboot-4.16-relnotes.md) * [4.15 - November 2021](coreboot-4.15-relnotes.md) * [4.14 - May 2021](coreboot-4.14-relnotes.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/64843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52814ebbae804ea0ff24a7cec0618054029b8b47 Gerrit-Change-Number: 64843 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Reka Norman (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Arthur Heymans, Eric Lai, Kyösti Mälkki, Felix Held. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Do you have CB:63475 in your build? Reboot and suspend are working again a few builds later. We don't have CB:64426 yet, but CB:63475 was merged in the build that's working, so that could be it. I haven't tested it yet. Thanks for the suggestions! -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Jun 2022 00:01:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2022