coreboot-gerrit June 2022

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Change in coreboot[master]: mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax
by John Su (Code Review) 01 Jun '22

01 Jun '22

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64856 ) Change subject: mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax ...................................................................... mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax Follow thermal table from thermal team. Chang list: 1. Update TEMP_PCT of Active Policy for TSR1. Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c --- M src/mainboard/google/brya/variants/mithrax/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/64856/1 diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 3fade87..93265bd 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -99,11 +99,11 @@ .target = DPTF_TEMP_SENSOR_1, .thresholds = { TEMP_PCT(48, 76), - TEMP_PCT(45, 65), - TEMP_PCT(42, 53), - TEMP_PCT(39, 45), - TEMP_PCT(36, 39), - TEMP_PCT(33, 34), + TEMP_PCT(40, 66), + TEMP_PCT(38, 53), + TEMP_PCT(36, 43), + TEMP_PCT(34, 39), + TEMP_PCT(32, 33), } } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/64856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c Gerrit-Change-Number: 64856 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Use SoC overrides to set CPU privilege level
by Lean Sheng Tan (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Werner Zeh, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64806 ) Change subject: soc/intel/common/cpu: Use SoC overrides to set CPU privilege level ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Gerrit-Change-Number: 64806 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:19:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Use SoC overrides to set CPU privilege level
by Angel Pons (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Werner Zeh, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64806 ) Change subject: soc/intel/common/cpu: Use SoC overrides to set CPU privilege level ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/skylake/cpu.c: https://review.coreboot.org/c/coreboot/+/64806/comment/9feabe71_11378d2d PS3, Line 40: if (!CONFIG(MAINBOARD_SUPPORTS_COFFEELAKE_CPU)) : return; : : msr_t msr; : : msr = rdmsr(MSR_BIOS_DONE); : msr.lo |= ENABLE_IA_UNTRUSTED; : wrmsr(MSR_BIOS_DONE, msr); > Ack This check is because soc/intel/skylake code can be used with CFL CPUs when using AmberLakeFspBinPkg. This FSP is also used on LGA1151v2 (socket for CFL CPUs) boards with H310C, B365 and Z370 PCHs (these PCHs are actually rebranded 200 series PCHs, c.f. datasheet). There are no boards using AmberLakeFspBinPkg right now, but I remember someone was working on porting a desktop board with a H310C PCH. And I have a Z370 board I haven't tried porting yet (I'm afraid of breaking it). I agree that a runtime check would be preferable. I remember commenting about it on CB:60900 but I wasn't sure how to implement the check. I think some Amber Lake SoCs are based on CML, so there's a bunch of CPUIDs to consider. -- To view, visit https://review.coreboot.org/c/coreboot/+/64806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4584516102560e6bb2a4ae8c0d036be40ed96990 Gerrit-Change-Number: 64806 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:12:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Move SBOM Configuration to own Kconfig
by Christian Walter (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Maximilian Brune. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64815 ) Change subject: Move SBOM Configuration to own Kconfig ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: That was actually my idea - sorry if I added more confusion here. -- To view, visit https://review.coreboot.org/c/coreboot/+/64815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a25723a96ca0e2b803c32b9dd3415753fa81e0 Gerrit-Change-Number: 64815 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:01:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 7: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/63555/comment/2de30f19_bfa5e11d PS7, Line 881: 10 > What is this magic number? A large enough array. Since ARRAY_SIZE is used everywhere, I think that's fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 08:56:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges
by Angel Pons (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges ...................................................................... Patch Set 7: (1 comment) File src/cpu/x86/mtrr/mtrr.c: https://review.coreboot.org/c/coreboot/+/63555/comment/893532ce_a86e9120 PS7, Line 881: 10 What is this magic number? -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Jun 2022 08:47:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices
by Subrata Banik (Code Review) 01 Jun '22

01 Jun '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64855 ) Change subject: soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices ...................................................................... soc/intel/cmn/cse: Implement heci_init() to initialize HECI devices This patch implements heci_init() API that perform initialization of all HECI devices as per MAX_HECI_DEVICES config. BUG=none TEST=TBD Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 42 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/64855/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e01b1cf..5da3a6f 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -23,6 +23,8 @@ #include <timer.h> #include <types.h> +#define HECI_BASE_SIZE (4 * KiB) + #define MAX_HECI_MESSAGE_RETRY_COUNT 5 /* Wait up to 15 sec for HECI to get ready */ @@ -84,6 +86,24 @@ return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } +static void heci_assign_resource(pci_devfn_t dev, uintptr_t tempbar) +{ + u16 pcireg; + + /* Assign Resources */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config16(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + /* * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been @@ -93,8 +113,6 @@ { pci_devfn_t dev = PCH_DEV_CSE; - u16 pcireg; - /* Check if device enabled */ if (!is_cse_enabled()) return; @@ -107,18 +125,8 @@ if (!tempbar) tempbar = HECI1_BASE_ADDRESS; - /* Assign Resources to HECI1 */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config16(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config16(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for HECI1 */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + /* Assign HECI resource and enable the resource */ + heci_assign_resource(dev, tempbar); /* Trigger HECI Reset and make Host ready for communication with CSE */ heci_reset(); @@ -1020,6 +1028,23 @@ } } +/* Initialize the HECI devices. */ +void heci_init(void) +{ + uintptr_t tempbar = HECI1_BASE_ADDRESS; + + for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { + pci_devfn_t dev = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); + if (!is_cse_devfn_visible(dev)) + continue; + + tempbar += (i * HECI_BASE_SIZE); + heci_assign_resource(dev, tempbar); + + ensure_cse_active(dev); + } +} + void cse_control_global_reset_lock(void) { /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 28bc250..322e9f3 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -333,6 +333,9 @@ */ void cse_init(uintptr_t bar); +/* Initialize the HECI devices. */ +void heci_init(void); + /* * Send message from BIOS_HOST_ADDR to cse_addr. * Sends snd_msg of size snd_sz, and reads message into buffer pointed by -- To view, visit https://review.coreboot.org/c/coreboot/+/64855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia25e18a20cc749fc7eee39b0b591d41540fc14c9 Gerrit-Change-Number: 64855 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Rename heci_init to cse_init
by Subrata Banik (Code Review) 01 Jun '22

01 Jun '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64854 ) Change subject: soc/intel: Rename heci_init to cse_init ...................................................................... soc/intel: Rename heci_init to cse_init This patch renames heci_init() to cse_init() as HECI initialization should have a bigger scope than just initializing the CSE (a.k.a HECI1 alone). BUG=none TEST=Able to build and boot google/taeko. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c 9 files changed, 15 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/64854/1 diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3f29fc3..48d9a6f 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -133,7 +133,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* Initialize HECI interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) pre_mem_debug_init(); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 236a122..1ea91da 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -125,7 +125,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d284a9d..e01b1cf 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -85,11 +85,11 @@ } /* - * Initialize the device with provided temporary BAR. If BAR is 0 use a + * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been * assigned yet and devices are not enabled. */ -void heci_init(uintptr_t tempbar) +void cse_init(uintptr_t tempbar) { pci_devfn_t dev = PCH_DEV_CSE; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 8fd8ba0..28bc250 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -326,8 +326,12 @@ uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA]; } __packed; -/* set up device for use in early boot enviroument with temp bar */ -void heci_init(uintptr_t bar); +/* + * Initialize the CSE device. + * + * Set up CSE device for use in early boot environment with temp bar. + */ +void cse_init(uintptr_t bar); /* * Send message from BIOS_HOST_ADDR to cse_addr. diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index ecbdd97..39a5a332 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 1dc618c..8575a3f 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -114,7 +114,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index f7e6a91..3a2f8b4 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 7e891b1..30401fc 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -129,7 +129,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); ps = pmc_get_power_state(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 872cca5..3c6e634 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); -- To view, visit https://review.coreboot.org/c/coreboot/+/64854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80 Gerrit-Change-Number: 64854 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "util/crossgcc: Update gcc to 11.2"
by Mike Banon (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Branden Waldner, Idwer Vollering, Arthur Heymans, Jacob Garber, Werner Zeh, Iru Cai, Elyes Haouas, Harshit Sharma. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 ) Change subject: Revert "util/crossgcc: Update gcc to 11.2" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Would you give a try to https://review.coreboot. […] Elyes, thank you for trying, unfortunately GCC 11.3 doesn't work too. Possible outcomes when attempting to use a coreboot+SeaBIOS on AMD Lenovo G505S built with GCC 11.3 : 1) black screen, doesn't show anything - even a SeaBIOS text interface; 2) shows a SeaBIOS interface which hangs on "Press ESC" (pressing ESC doesn't do anything); 3) shows a SeaBIOS interface which works; if I didn't choose anything, then runs a default entry (a KolibriOS ramdisk, which launched successfully the times I tried); if I chose a HDD, see "4)" and "5)" 4) loads GRUB from HDD - it gets a password from keyboard but hangs while decrypting a /boot; 5) successfully decrypts /boot and shows a GRUB menu, but later hangs on "Loading initial ramdisk" ! This booting step precedes a step of entering a key and decrypting a "/" partition of a Full Disk Encryption instal of Artix Linux (user-friendly Arch without SystemD) which I did by this manual - https://wiki.artixlinux.org/Main/InstallationWithFullDiskEncryption Meanwhile, an equal coreboot+SeaBIOS build with GCC 8.3.0 and the same contents of HDD - works perfectly all the time. I haven't yet tried a mixed build of "coreboot by new GCC, SeaBIOS by old GCC" -- To view, visit https://review.coreboot.org/c/coreboot/+/59636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a789f9ccb284ac7cad32b12bbf60ecb82efb44 Gerrit-Change-Number: 59636 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 07:51:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Reka Norman, Eric Lai, Kyösti Mälkki, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > No, we don't have any logs. When we try to suspend/reboot/poweroff the kernel finishes cleanly and then it just hangs. > > We'll try to debug it as soon as possible, but could we please still revert the change in the mean time? Having reboot and S0ix broken on nissa will block a lot of testing and be very disruptive to the program. Can you provide booting logs and enable SMI debugging? -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 07:34:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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