coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-S
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63839 ) Change subject: soc/intel/alderlake/fsp_params.c: Add VccIn Aux Imon IccMax for ADL-S ...................................................................... Patch Set 5: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95404e717787edbdb67c9e584e749526b973427 Gerrit-Change-Number: 63839 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:55:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Do not pass IRQs for non-existent devices to FSP
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63837 ) Change subject: soc/intel/alderlake: Do not pass IRQs for non-existent devices to FSP ...................................................................... Patch Set 5: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I055d4bbfd04a01fa9943278b6bbc9a31b9dfc628 Gerrit-Change-Number: 63837 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:54:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/fsp_params.c: Fill PCI SSID parameters
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

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Change in coreboot[master]: mb/msi/ms7d25: Properly handle CnvDdrRfim parameter
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63835 ) Change subject: mb/msi/ms7d25: Properly handle CnvDdrRfim parameter ...................................................................... Patch Set 5: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9 Gerrit-Change-Number: 63835 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:53:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: Configure PCIe Root Ports
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63656 ) Change subject: mb/msi/ms7d25: Configure PCIe Root Ports ...................................................................... Patch Set 9: Verified-1 (57 comments) File src/mainboard/msi/ms7d25/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/2db41601_7f784b30 PS9, Line 142: _PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/beee8641_f6ed064d PS9, Line 172: _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/a5be5c04_5bc90dc9 PS9, Line 172: _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_0 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/daf7c377_34808ba8 PS9, Line 173: _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/f6bf29a3_16825731 PS9, Line 173: _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_1 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/a09b3af6_d3254468 PS9, Line 174: _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/5289ba14_e970c5c9 PS9, Line 174: _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_2 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/0187050c_f29ddb46 PS9, Line 175: _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/89fc2401_c6f312e8 PS9, Line 175: _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_3 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/caa57988_319bf318 PS9, Line 176: _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_8 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/22943b27_0612cd94 PS9, Line 176: _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_8 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/d0a265db_16ee5cfb PS9, Line 177: _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_9 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/67894693_9c9b057c PS9, Line 177: _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_9 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/d8ad8538_f01b9919 PS9, Line 178: _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_10 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/8e9a4e9f_33c00c20 PS9, Line 178: _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_10 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/b7e62a80_20d2d561 PS9, Line 179: _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_11 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/54d3f543_908ee8b7 PS9, Line 179: _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG_GPIO_NAF_VWE, 0), /* VGPIO_USB_11 */ need consistent spacing around '|' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/81961808_fb88fdc8 PS9, Line 425: // _PAD_CFG_STRUCT(VGPIO_PCIE_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/9351c93b_c48528df PS9, Line 426: // _PAD_CFG_STRUCT(VGPIO_PCIE_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/89a39e58_eba8e620 PS9, Line 427: // _PAD_CFG_STRUCT(VGPIO_PCIE_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/6a4a87f3_6c329a4a PS9, Line 428: // _PAD_CFG_STRUCT(VGPIO_PCIE_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/a2355ee6_f12d6194 PS9, Line 429: // _PAD_CFG_STRUCT(VGPIO_PCIE_4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/4f84e1c9_1c03a950 PS9, Line 430: // _PAD_CFG_STRUCT(VGPIO_PCIE_5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/addc6b93_8c3f193f PS9, Line 431: // _PAD_CFG_STRUCT(VGPIO_PCIE_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/211b07d8_4b95cfe0 PS9, Line 432: // _PAD_CFG_STRUCT(VGPIO_PCIE_7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/112ee283_91f619be PS9, Line 433: // _PAD_CFG_STRUCT(VGPIO_PCIE_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/485d62f5_58c5248c PS9, Line 434: // _PAD_CFG_STRUCT(VGPIO_PCIE_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/854f5034_fa62ab90 PS9, Line 435: // _PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/45192d85_19dc8a82 PS9, Line 436: // _PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/bcfa29e9_230228c8 PS9, Line 437: // _PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/b6388272_1488e170 PS9, Line 438: // _PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/189b3f61_0505b2a9 PS9, Line 439: // _PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/bf6f4d70_e97a9433 PS9, Line 440: // _PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/f0b78392_9f6a657c PS9, Line 441: // _PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/c1711c58_abecbae0 PS9, Line 442: // _PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/44abbf05_893302bf PS9, Line 443: // _PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/2ced38b8_be5fd056 PS9, Line 444: // _PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/98252752_3b39d204 PS9, Line 447: // _PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/9e07034e_dacad8d3 PS9, Line 448: // _PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/8d539257_f76e6e78 PS9, Line 449: // _PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/5bf235f7_6fe692fd PS9, Line 450: // _PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/f6ab407c_1730550b PS9, Line 451: // _PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/8f48fc9a_8debeba6 PS9, Line 452: // _PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/eebe3457_533b2a75 PS9, Line 453: // _PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/f1ea16e5_fe0186b2 PS9, Line 454: // _PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/ed430990_a29d0390 PS9, Line 455: // _PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/97b2d267_d639131b PS9, Line 456: // _PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/eeddb689_6fd03319 PS9, Line 457: // _PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/e54900c1_5e441e34 PS9, Line 458: // _PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/6533b78d_c1983e74 PS9, Line 459: // _PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/a59f0043_80e3b1ec PS9, Line 460: // _PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/dd320321_cc980410 PS9, Line 461: // _PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/25c9365c_5712ca0a PS9, Line 462: // _PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/b0c71da4_c3927cd7 PS9, Line 463: // _PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/49e2f5b4_e85cfbc8 PS9, Line 464: // _PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/ec8bb31f_bdefbdd1 PS9, Line 465: // _PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150204): https://review.coreboot.org/c/coreboot/+/63656/comment/0a0956f0_312e5b7a PS9, Line 466: // _PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG_GPIO_NAF_VWE, 0), line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Gerrit-Change-Number: 63656 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:52:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Maulik V Vaghela, Jeremy Soller, Michał Kopeć, Tim Wawrzynczak, Paul Menzel, Ronak Kanabar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64074 ) Change subject: soc/intel/alderlake/hsphy: Add support for HSPHY firmware loading ...................................................................... Patch Set 3: Verified-1 (11 comments) File src/soc/intel/alderlake/hsphy.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/454402c9_f129a98e PS3, Line 28: #define HSPHY_PAYLOAD_SIZE 32*KiB Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/356a70f8_b0e8a67c PS3, Line 40: #define HSPHY_MEM_VERIFIER_ERROR_STATUS (HSPHY_VERIFIER_BASE + 0x30) please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/31555825_bc9934c2 PS3, Line 67: }__packed; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/6166ea3f_70965024 PS3, Line 159: printk (BIOS_ERR, "Hash alg %d not supported, try SHA384\n", hash_alg); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/d3a56420_dd463d3f PS3, Line 186: i += sizeof (*push_model); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/4900a9a4_7dab8cdb PS3, Line 188: if ((push_model->address == 0) && (push_model->count == 0)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/1fcb18f9_77321a58 PS3, Line 194: i += sizeof (uint32_t); space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/e5aa73cf_37a1e42a PS3, Line 275: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/3ce6bc5e_2c385d8a PS3, Line 312: hsphy_ver = REGBAR32(CPU_PID_PCIE_PHYx16_0, HSPHY_FW_VERSION);; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/d099ee3b_43e39bb6 PS3, Line 317: hsphy_ver = REGBAR32(CPU_PID_PCIE_PHYx16_1, HSPHY_FW_VERSION);; Statements terminations use 1 semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150203): https://review.coreboot.org/c/coreboot/+/64074/comment/7a4d82d5_7ac16947 PS3, Line 344: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/64074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Gerrit-Change-Number: 64074 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:51:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63655 ) Change subject: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names ...................................................................... Patch Set 7: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Gerrit-Change-Number: 63655 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:51:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/smbios.h: Add PCIe Gen5 slot type definitions
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63653 ) Change subject: include/smbios.h: Add PCIe Gen5 slot type definitions ...................................................................... Patch Set 7: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624 Gerrit-Change-Number: 63653 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:50:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [HACK] Add an option to use ADL-S IOT FSP
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63578 ) Change subject: [HACK] Add an option to use ADL-S IOT FSP ...................................................................... Patch Set 9: Verified-1 (183 comments) File src/soc/intel/alderlake/include/fsp/FirmwareVersionInfoHob.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/08eb608b_3653d6d4 PS9, Line 29: UINT8 MajorVersion; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/3755fd8c_6b04d668 PS9, Line 30: UINT8 MinorVersion; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/aec9ffcb_6acd1768 PS9, Line 31: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f4f57a5b_7ad7ac34 PS9, Line 32: UINT16 BuildNumber; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6bc888c6_fafe8162 PS9, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/4cad8764_bdeb7b0c PS9, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/c0f1a1d8_89005363 PS9, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/271969f0_3f41c7a6 PS9, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/70144758_068b691f PS9, Line 41: FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5aa2d4db_03e4c318 PS9, Line 49: UINT8 Type; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bb6d8127_4b75557c PS9, Line 50: UINT8 Length; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/12eaaf10_915cbfc8 PS9, Line 51: UINT16 Handle; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9ab0609a_278d71ba PS9, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/0e09f8f0_2f023cb4 PS9, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/55053d7c_9937ec78 PS9, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/4930e5c2_79b99ca4 PS9, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8e96b595_82ae3647 PS9, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/97f7c42a_b4db22da PS9, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/baebd19e_e6225986 PS9, Line 68: #endif // _FIRMWARE_VERSION_INFO_HOB_H_ adding a line without newline at end of file File src/soc/intel/alderlake/include/fsp/MemInfoHob.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/220a28e4_37f8f1ce PS9, Line 22: #pragma pack (push, 1) space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/83691868_5d3538c5 PS9, Line 50: UINT16 HobType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/02dfe58f_f64dd85a PS9, Line 51: UINT16 HobLength; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a6a79cfd_8fda77f1 PS9, Line 52: UINT32 Reserved; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9e3c7a41_2b46adec PS9, Line 56: EFI_HOB_GENERIC_HEADER Header; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6dad4694_b0740ec7 PS9, Line 57: EFI_GUID Name; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/925eba4b_090a8848 PS9, Line 80: UINT8 Major; ///< Major version number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/75e4ab99_368424e3 PS9, Line 81: UINT8 Minor; ///< Minor version number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9963d4aa_c68aa20e PS9, Line 82: UINT8 Rev; ///< Revision number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cedcd70b_ece3543a PS9, Line 83: UINT8 Build; ///< Build number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6445078c_33a7cc12 PS9, Line 109: #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6b9df6d5_19a8b73c PS9, Line 119: #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ac834d6f_f9f5a899 PS9, Line 124: bmCold, ///< Cold boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/55d3d1cc_3b768b79 PS9, Line 125: bmWarm, ///< Warm boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/0d17bd57_5b7a0f6a PS9, Line 126: bmS3, ///< S3 resume please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bc8d787d_81bc8a56 PS9, Line 127: bmFast, ///< Fast boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cdcbbb80_b1f4049c PS9, Line 128: MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/004b5276_6533453c PS9, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/dcd2c202_7e0c06c8 PS9, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/13d0f792_b44163c0 PS9, Line 159: UINT32 tCK; ///< Memory cycle time, in femtoseconds. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a48fea9c_1d438345 PS9, Line 160: UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6b395e51_5d0e0b00 PS9, Line 161: UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f045dde9_e0c6fff2 PS9, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d4fbd377_bf2b43e3 PS9, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/713a9bc3_13303bdb PS9, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/028c73e1_eb36f004 PS9, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/30aaad43_aa0ae96d PS9, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/94e0dafe_05e04a4f PS9, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ef71b5ca_123958ee PS9, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f81a87da_e28ada13 PS9, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/25740e1d_d090cc12 PS9, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/727301b0_d4688508 PS9, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6e82c8c7_1249a6f3 PS9, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6436aa36_f7a57132 PS9, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f0135d10_6e080e43 PS9, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8895ea06_74b22ef2 PS9, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/b3c76136_8abcc93a PS9, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8e1b45fa_23a09972 PS9, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/4a1d0ee3_03349a02 PS9, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/e265d257_30410507 PS9, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/94b428c3_df856ca3 PS9, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/2abeed6e_bd2f72db PS9, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/900f7d47_e21880d3 PS9, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cbaa56e6_269e884a PS9, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/56190c51_abf9a2d2 PS9, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/143a4eec_f0def38c PS9, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/2d6f4528_5814d8d4 PS9, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/caaf7d4c_74283c8f PS9, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/90a642a0_d6a4402e PS9, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/38eeb416_3070cb03 PS9, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5786f2c4_1daabe61 PS9, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6eb89176_ee398166 PS9, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1debfeb1_c9431125 PS9, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/01413198_59daf1de PS9, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/c6e754ed_107b67c8 PS9, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a3848053_43ca6ff3 PS9, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5b646bc6_b20fc512 PS9, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/99e49a54_899852fe PS9, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/58cfea4d_63a89bd9 PS9, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d710cdf1_ccbce91d PS9, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f281af53_6345c469 PS9, Line 184: UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9b6e985e_e6b7fe1c PS9, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/157b39a1_b97c2b68 PS9, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a6cf61a3_2ab2750d PS9, Line 192: UINT8 DimmId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/c97b0411_102be26b PS9, Line 193: UINT32 DimmCapacity; ///< DIMM size in MBytes. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/da5035d7_dc196a3e PS9, Line 194: UINT16 MfgId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/22e9accb_19e71ce4 PS9, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f2798223_ba9c9469 PS9, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f5ba041a_2078f3a2 PS9, Line 196: UINT8 RankInDimm; ///< The number of ranks in this DIMM. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/3f880101_579a95d6 PS9, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6326aac4_43a1681e PS9, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ea6af88a_8d83902d PS9, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/73d27445_bd9a6def PS9, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/731684b4_8da4b3be PS9, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f35e8265_03c80069 PS9, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5c8496a3_e3933e23 PS9, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/99ac2eb7_cdd434a4 PS9, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a9889751_b278e9b1 PS9, Line 201: UINT16 Speed; ///< The maximum capable speed of the device, in MHz please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/236eb142_7f9bd049 PS9, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8d86aac2_d5c91b00 PS9, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/c8785b18_f3cdfe1d PS9, Line 206: UINT8 Status; ///< Indicates whether this channel should be used. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/7ae845ac_f15bb616 PS9, Line 207: UINT8 ChannelId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9a3903f2_f192b657 PS9, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/db5dda50_2c2c90cc PS9, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/191c8ba9_caf13e49 PS9, Line 209: MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/3e27cbb2_5218dc07 PS9, Line 210: DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/9a47a2a2_8bb1982c PS9, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ca4a0b76_5eb9c560 PS9, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1c92970a_aca3c693 PS9, Line 215: UINT16 DeviceId; ///< The PCI device id of this memory controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ea29bea6_de3c8b55 PS9, Line 216: UINT8 RevisionId; ///< The PCI revision id of this memory controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/7387be71_19febb31 PS9, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1faa7772_fcfe62d6 PS9, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bb349be0_e23aed95 PS9, Line 218: CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/28b7133d_067768eb PS9, Line 222: UINT64 BaseAddress; ///< Trace Base Address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/abe493aa_787b2207 PS9, Line 223: UINT64 TotalSize; ///< Total Trace Region of Same Cache type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/2092ca3b_45beebee PS9, Line 224: UINT8 CacheType; ///< Trace Cache Type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/31a9d65d_fe6cf175 PS9, Line 225: UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/81de2688_59a514d3 PS9, Line 226: UINT8 Rsvd[2]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5f1266b3_feef04e8 PS9, Line 231: UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/e4c28650_48ed0cac PS9, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/b5f0e671_f2e9a234 PS9, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ad329473_4d163080 PS9, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/4c94c2f4_90a45a18 PS9, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/c7cdff7d_90b2f92d PS9, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d1e5976e_19f3dad3 PS9, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/defae224_95d41d52 PS9, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/16595abb_85ba4914 PS9, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/a4f12be9_77a9c0bb PS9, Line 240: HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1fba227f_67c934fc PS9, Line 244: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/67ac4a43_f4037842 PS9, Line 245: UINT16 DataWidth; ///< Data width, in bits, of this memory device please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/7c57a32f_83944950 PS9, Line 249: UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/e4dcb4fd_160a5823 PS9, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/edbf4ce0_d7119d89 PS9, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5ca3a596_8cd8d7b0 PS9, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/0a23af80_cf0b59ca PS9, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/54b6374d_4dc09ac2 PS9, Line 255: UINT8 ErrorCorrectionType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/4ff22a10_3f962e1d PS9, Line 257: SiMrcVersion Version; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/11458a89_2ed3858a PS9, Line 258: BOOLEAN EccSupport; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5f0bb788_1b4303be PS9, Line 259: UINT8 MemoryProfile; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/71f57cd6_6ecbec09 PS9, Line 260: UINT8 IsDMBRunning; ///< Deprecated. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f53f3bc8_0393ae5e PS9, Line 261: UINT32 TotalPhysicalMemorySize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/adb7bb31_f3762369 PS9, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bdecbdea_d89f36b6 PS9, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/66f0ab28_eb1bddf7 PS9, Line 264: /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/dead2a69_4283df7c PS9, Line 271: UINT8 XmpProfileEnable; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d51ebd38_7da48975 PS9, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/35ad24f8_e39d9138 PS9, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cce20f0e_297f012f PS9, Line 273: UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/92818021_86a4d143 PS9, Line 274: UINT8 RefClk; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/59e3ef7a_4fda2e92 PS9, Line 275: UINT32 VddVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ae1fbe6c_3c72652d PS9, Line 276: UINT32 VddqVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/956099a5_c15d351d PS9, Line 277: UINT32 VppVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/ce7fdd36_2e9cac19 PS9, Line 278: CONTROLLER_INFO Controller[MAX_NODE]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bf52216e_7352ccc2 PS9, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8c9b32d3_f5cfcc6b PS9, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cdf0ad1c_ad437db1 PS9, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/53ad1063_a00f321f PS9, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1d23d731_f3db6e77 PS9, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/91251afe_1247129a PS9, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/7b3ba07c_35af2e86 PS9, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/2c17754e_99007c04 PS9, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/73d6d018_ecf8f72a PS9, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/1b137069_b72e4c20 PS9, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8a2df802_57e3bc4f PS9, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/225f095c_1c16fb72 PS9, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/cc23b531_852f933f PS9, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d1861df1_c84eceba PS9, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/f5103563_43948eb5 PS9, Line 297: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/e7f0f8e7_efbcabc5 PS9, Line 298: UINT8 Reserved[3]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/3663edb3_146363b0 PS9, Line 299: UINT32 BootMode; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/5b86ac88_f49a21ef PS9, Line 300: UINT32 TsegSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/3b3f27bc_cd53d6d7 PS9, Line 301: UINT32 TsegBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/0eb93263_1dab3aaf PS9, Line 302: UINT32 PrmrrSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/dc074a86_c907580a PS9, Line 303: UINT64 PrmrrBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6263a868_4ffa58a8 PS9, Line 304: UINT32 GttBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/6b1e24d8_ba51b3ab PS9, Line 305: UINT32 MmioSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/67d3beb6_504775b6 PS9, Line 306: UINT32 PciEBaseAddress; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/7240ae4c_7adb612e PS9, Line 307: PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/48af2c4f_e1ae8c14 PS9, Line 308: PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/8b4029e0_467d8911 PS9, Line 309: BOOLEAN MrcBasicMemoryTestPass; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/bb59db59_ad37d894 PS9, Line 313: EFI_HOB_GUID_TYPE EfiHobGuidType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/d1c12b94_80e333d1 PS9, Line 314: MEMORY_PLATFORM_DATA Data; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/247e45a4_a889d1fe PS9, Line 315: UINT8 *Buffer; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150199): https://review.coreboot.org/c/coreboot/+/63578/comment/b926b4c5_e0ddc58e PS9, Line 318: #pragma pack (pop) space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/63578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97198b1faa3e3c57f4950b0d69df1e6c43d289c3 Gerrit-Change-Number: 63578 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:50:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Revert "cpu/x86/mtrr: Make useful MTRR functions available for all bo...
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64804 ) Change subject: Revert "cpu/x86/mtrr: Make useful MTRR functions available for all boot stages" ...................................................................... Revert "cpu/x86/mtrr: Make useful MTRR functions available for all boot stages" This code is only meant to be used in early stages so move it back to earlymtrr.c. This reverts commit 3ad00d0c89c9e7a8e9ef13b6dc65bb338a191ec8. Change-Id: I9bc1ac4b863eb43d3e398e6462ee139a7751bf62 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64804 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/mtrr/Makefile.inc M src/cpu/x86/mtrr/earlymtrr.c D src/cpu/x86/mtrr/mtrrlib.c 3 files changed, 60 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 87e61b2..a78517a 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,11 +1,5 @@ ramstage-y += mtrr.c -ramstage-y += mtrrlib.c -postcar-y += mtrrlib.c -romstage-y += mtrrlib.c -bootblock-y += mtrrlib.c -verstage_x86-y += mtrrlib.c - romstage-y += earlymtrr.c bootblock-y += earlymtrr.c verstage_x86-y += earlymtrr.c diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 8ea1216..2c14a70 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -7,6 +7,66 @@ #include <commonlib/bsd/helpers.h> #include <stdint.h> +/* Get first available variable MTRR. + * Returns var# if available, else returns -1. + */ +int get_free_var_mtrr(void) +{ + msr_t maskm; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + /* Identify the first var mtrr which is not valid. */ + for (i = 0; i < vcnt; i++) { + maskm = rdmsr(MTRR_PHYS_MASK(i)); + if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) + return i; + } + + /* No free var mtrr. */ + return -1; +} + +void set_var_mtrr( + unsigned int reg, unsigned int base, unsigned int size, + unsigned int type) +{ + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + msr_t basem, maskm; + + if (!IS_POWER_OF_2(size)) + printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); + if (size < 4 * KiB) + printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); + if (base % size != 0) + printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, + size); + + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; + maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; + wrmsr(MTRR_PHYS_MASK(reg), maskm); +} + +void clear_all_var_mtrr(void) +{ + msr_t mtrr = {0, 0}; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + for (i = 0; i < vcnt; i++) { + wrmsr(MTRR_PHYS_MASK(i), mtrr); + wrmsr(MTRR_PHYS_BASE(i), mtrr); + } +} + void var_mtrr_context_init(struct var_mtrr_context *ctx) { ctx->max_var_mtrrs = get_var_mtrr_count(); diff --git a/src/cpu/x86/mtrr/mtrrlib.c b/src/cpu/x86/mtrr/mtrrlib.c deleted file mode 100644 index 71921de..0000000 --- a/src/cpu/x86/mtrr/mtrrlib.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <console/console.h> - -/* Get first available variable MTRR. - * Returns var# if available, else returns -1. - */ -int get_free_var_mtrr(void) -{ - msr_t maskm; - int vcnt; - int i; - - vcnt = get_var_mtrr_count(); - - /* Identify the first var mtrr which is not valid. */ - for (i = 0; i < vcnt; i++) { - maskm = rdmsr(MTRR_PHYS_MASK(i)); - if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) - return i; - } - - /* No free var mtrr. */ - return -1; -} - -void set_var_mtrr( - unsigned int reg, unsigned int base, unsigned int size, unsigned int type) -{ - /* Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - - if (!IS_POWER_OF_2(size)) - printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); - if (size < 4 * KiB) - printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size); - if (base % size != 0) - printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base, - size); - - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -void clear_all_var_mtrr(void) -{ - msr_t mtrr = {0, 0}; - int vcnt; - int i; - - vcnt = get_var_mtrr_count(); - - for (i = 0; i < vcnt; i++) { - wrmsr(MTRR_PHYS_MASK(i), mtrr); - wrmsr(MTRR_PHYS_BASE(i), mtrr); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/64804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bc1ac4b863eb43d3e398e6462ee139a7751bf62 Gerrit-Change-Number: 64804 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2022