coreboot-gerrit June 2022

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Change in coreboot[master]: soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Uwe Poeche. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64661 ) Change subject: soc/intel/elkhartlake: Select SOC_INTEL_RAPL_DISABLE_VIA_MCHBAR ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f Gerrit-Change-Number: 64661 Gerrit-PatchSet: 4 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:10:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: move RAPL disabling to common code
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Uwe Poeche, Werner Zeh, Andrey Petrov. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64596 ) Change subject: intel/common/block: move RAPL disabling to common code ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84 Gerrit-Change-Number: 64596 Gerrit-PatchSet: 5 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:10:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code when calling FSP
by Lean Sheng Tan (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Arthur Heymans, Andrey Petrov. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code when calling FSP ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: This fixed ADL FSP debug reboot loop. Thanks for the fix! -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:08:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code when calling FSP
by Lean Sheng Tan (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Arthur Heymans, Andrey Petrov. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code when calling FSP ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:08:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx
by Tyler Wang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: V Sowmya, Martin L Roth, Kangheui Won, Tim Wawrzynczak, Vidya Gopalakrishnan. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64632 ) Change subject: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/64632/comment/13ade325_0f4faabf PS3, Line 7: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx rails for Craask > Please limit the subject to 65 characters. Done. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/64632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Gerrit-Change-Number: 64632 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)tutanota.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)tutanota.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx
by Tyler Wang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: V Sowmya, Kangheui Won, Tim Wawrzynczak, Vidya Gopalakrishnan, Tyler Wang. Hello V Sowmya, build bot (Jenkins), Kangheui Won, Reka Norman, Tim Wawrzynczak, Vidya Gopalakrishnan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64632 to look at the new patch set (#4). Change subject: mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx ...................................................................... mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSx This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/64632/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Gerrit-Change-Number: 64632 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)tutanota.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa/var/craask: Generate SPD ID for supported memory part
by Tyler Wang (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64858 to look at the new patch set (#2). Change subject: mb/google/nissa/var/craask: Generate SPD ID for supported memory part ...................................................................... mb/google/nissa/var/craask: Generate SPD ID for supported memory part Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. K3LKBKB0BM-MGCP H9JCNNNCP3MLYR-N6E BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 --- M src/mainboard/google/brya/variants/craask/memory/Makefile.inc M src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/64858/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 Gerrit-Change-Number: 64858 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa/var/craask: Generate SPD ID for supported memory part
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64858 ) Change subject: mb/google/nissa/var/craask: Generate SPD ID for supported memory part ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150230): https://review.coreboot.org/c/coreboot/+/64858/comment/44c5f1fb_c0d1fc23 PS1, Line 9: Add supported memory parts in mem_parts_used.txt, and generate SPD id for Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/64858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 Gerrit-Change-Number: 64858 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:01:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Enable CBFS serial number and UUID as default
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64640 ) Change subject: mainboard/msi/ms7d25: Enable CBFS serial number and UUID as default ...................................................................... Patch Set 2: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8af889f12617d4ab6a27c6f336276c04f26244c Gerrit-Change-Number: 64640 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:01:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Add USB macros and port designation comments
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64295 ) Change subject: mainboard/msi/ms7d25: Add USB macros and port designation comments ...................................................................... Patch Set 5: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d Gerrit-Change-Number: 64295 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:00:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2022