coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

1 participants
1234 discussions

Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 01 Jun '22

01 Jun '22

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Change in coreboot[master]: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195
by Rex-BC Chen (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Xi Chen, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64861 ) Change subject: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Gerrit-Change-Number: 64861 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:45:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195
by Rex-BC Chen (Code Review) 01 Jun '22

01 Jun '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64861 ) Change subject: soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195 ...................................................................... soc/mediatek: Enable thermal hardware reset for MT8192 and MT8195 From CB:64676 and CB:64675, we implement the thermal hardware reset in mtk_wdt_preinit(). To enable it, we need to call this function in bootblock_soc_init(). BUG=none TEST=build pass Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d --- M src/soc/mediatek/mt8192/bootblock.c M src/soc/mediatek/mt8195/bootblock.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/64861/1 diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 3adf5c1..d819661 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -11,6 +11,7 @@ { mtk_mmu_init(); bustracker_init(); + mtk_wdt_preinit(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8195/bootblock.c b/src/soc/mediatek/mt8195/bootblock.c index 813c0c8..00fe4e4 100644 --- a/src/soc/mediatek/mt8195/bootblock.c +++ b/src/soc/mediatek/mt8195/bootblock.c @@ -12,6 +12,7 @@ { mtk_mmu_init(); bustracker_init(); + mtk_wdt_preinit(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); -- To view, visit https://review.coreboot.org/c/coreboot/+/64861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Gerrit-Change-Number: 64861 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61494 ) Change subject: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/qemu-x86/Kconfig M src/include/cpu/intel/smm_reloc.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 5 files changed, 18 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 73aadfb..868009c 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -10,7 +10,6 @@ if CPU_QEMU_X86 -# coreboot i440fx does not support SMM choice prompt "AP init" default CPU_QEMU_X86_LAPIC_INIT @@ -24,6 +23,7 @@ endchoice +# coreboot i440fx does not support SMM choice prompt "SMM support" default CPU_QEMU_X86_ASEG_SMM @@ -35,7 +35,6 @@ config CPU_QEMU_X86_ASEG_SMM bool "SMM in ASEG" - depends on CPU_QEMU_X86_LAPIC_INIT select SMM_ASEG config CPU_QEMU_X86_TSEG_SMM diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index 126aa2a..3d95efc 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -36,6 +36,7 @@ /* These helpers are for performing SMM relocation. */ void northbridge_write_smram(u8 smram); +void smm_open_aseg(void); void smm_lock(void); void smm_relocate(void); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 06aa83a..b55ace0 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -247,7 +247,7 @@ void mp_init_cpus(struct bus *cpu_bus) { - const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm; + const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm; /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, ops); diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index fb31fc5..fe3a571 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -12,7 +12,14 @@ { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + if (CONFIG(SMM_TSEG)) + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (CONFIG(SMM_ASEG)) { + smm_open_aseg(); + *perm_smbase = 0xa0000; + *perm_smsize = 0x10000; + } /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c index 7d5180e..e73e0df 100644 --- a/src/mainboard/emulation/qemu-q35/memmap.c +++ b/src/mainboard/emulation/qemu-q35/memmap.c @@ -78,6 +78,12 @@ */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); + if (CONFIG(SMM_TSEG)) + pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN); pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } + +void smm_open_aseg(void) +{ + pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN); +} 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 25 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Kyösti Mälkki (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Reka Norman, Arthur Heymans, Eric Lai, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > No, we don't have any logs. […] Do you have CB:63475 in your build? -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:22:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Angel Pons (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Igor Bagnucki, Michał Kopeć. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63463 ) Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... Patch Set 10: (5 comments) File src/mainboard/msi/ms7d25/dsdt.asl: https://review.coreboot.org/c/coreboot/+/63463/comment/a59eb0a4_8374e2e3 PS10, Line 11: /* OEM revision */ It's not the OEM revision, this is just copy-pasta. Please drop the comment. File src/mainboard/msi/ms7d25/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/63463/comment/95a6cd02_2469dc85 PS10, Line 14: .resistor = 100, Seems OK. https://review.coreboot.org/c/coreboot/+/63463/comment/24d95ef2_4184b2ae PS10, Line 17: 50, 20, 25, 25, 25 I think this should be `40, 30, 33, 33, 30`. If you have access to FSP sources, grep for `RcompTargetHDdr4`. https://review.coreboot.org/c/coreboot/+/63463/comment/528eec53_3b190bae PS10, Line 20: .ect = true, /* Early Command Training */ I think this doesn't do anything on DDR4. At least, it doesn't on SKL/KBL/CFL. https://review.coreboot.org/c/coreboot/+/63463/comment/7854c1c7_3df2488c PS10, Line 24: .LpDdrDqDqsReTraining = 1, This shouldn't be needed with DDR4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:15:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h: https://review.coreboot.org/c/coreboot/+/63467/comment/0cb55e7b_7c8483c5 PS11, Line 485: INC(GPP_D2) > INC(GPP_D20) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:13:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63499 ) Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ...................................................................... Patch Set 15: (1 comment) File src/mainboard/msi/ms7d25/devicetree.cb: https://review.coreboot.org/c/coreboot/+/63499/comment/705cd972_c72f78fe PS7, Line 12: OC_SKIP > Also we need to pass OC pins Already done -- To view, visit https://review.coreboot.org/c/coreboot/+/63499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Gerrit-Change-Number: 63499 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:12:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: correct ddi_ports_config
by Raihow Shi (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64819 to look at the new patch set (#7). Change subject: mb/google/brask/variants/moli: correct ddi_ports_config ...................................................................... mb/google/brask/variants/moli: correct ddi_ports_config 1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection 2. remove DDI_ENABLE_DDC for Port 2. BUG=b:234521799 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/64819/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/64819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e Gerrit-Change-Number: 64819 Gerrit-PatchSet: 7 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Subrata Banik. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... Patch Set 14: (1 comment) File src/soc/intel/alderlake/chipset_pch_s.cb: https://review.coreboot.org/c/coreboot/+/63493/comment/f2ba5325_fe3629bb PS8, Line 84: 2.10 > This is hex, should be 2. […] Already done -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:11:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2022