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Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S
......................................................................
Patch Set 15: Verified+1
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Change subject: soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63500/comment/f9ebe34a_a32625a5
PS2, Line 101: select SOC_INTEL_COMMON_BLOCK_TCSS if !SOC_INTEL_ALDERLAKE_PCH_S
: select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
: select SOC_INTEL_COMMON_BLOCK_USB4 if !SOC_INTEL_ALDERLAKE_PCH_S
: select SOC_INTEL_COMMON_BLOCK_USB4_PCIE if !SOC_INTEL_ALDERLAKE_PCH_S
: select SOC_INTEL_COMMON_BLOCK_USB4_XHCI if !SOC_INTEL_ALDERLAKE_PCH_S
> Should we make a new Kconfig for these like […]
Makes sense, done
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Change subject: mb/msi/ms7d25: Enable displays
......................................................................
Patch Set 14:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63507/comment/03d4f341_2a589209
PS2, Line 9: Add VBT from vendor firmware and configure display ports in
: devicetree.
> Sorry, incorrect paste. The sentence fits in 72 characters. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/63507/comment/43e4c432_2f775f47
PS5, Line 13: Display Port
> DisplayPort
Done
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Michał Kopeć has uploaded a new patch set (#15) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/63507 )
Change subject: mb/msi/ms7d25: Enable displays
......................................................................
mb/msi/ms7d25: Enable displays
Add VBT from vendor firmware v5.24 and configure display outputs in
devicetree.
TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the
connected dispaly via HDMI or DisplayPort on rear panel.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/msi/ms7d25/Kconfig
A src/mainboard/msi/ms7d25/data.vbt
M src/mainboard/msi/ms7d25/devicetree.cb
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63507/15
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Michał Kopeć has uploaded a new patch set (#10) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/63500 )
Change subject: soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
......................................................................
soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1
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---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
2 files changed, 10 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63500/10
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Change subject: mb/msi/ms7d25: add GPIO configuration
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/msi/ms7d25/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/63490/comment/b372508d_8510c063
PS8, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */
> Put the file directly into mainboard directory
Already done
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Hello Keith Hui, build bot (Jenkins), Branden Waldner, Angel Pons, Keith Hui, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59693
to look at the new patch set (#10).
Change subject: nb/intel/i440bx: Use PARALLEL_MP
......................................................................
nb/intel/i440bx: Use PARALLEL_MP
The ramstage size is decreased by roughly 5K, but the compressed size
increased by ~1K.
Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/i440bx/Kconfig
M src/northbridge/intel/i440bx/northbridge.c
2 files changed, 15 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59693/10
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59693 )
Change subject: nb/intel/i440bx: Use PARALLEL_MP
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59693/comment/278693dd_8811b5f6
PS4, Line 10: always
> asus/p2b/variants/p2b-d/overridetree.cb
>
> config MAX_CPUS
> int
> default 2 if BASE_ASUS_P2B_D
The code does alloc_find_dev so that should actually be ok.
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Change subject: cpu/intel/model_fxx: Select SSE2
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/intel/model_f2x/Kconfig:
https://review.coreboot.org/c/coreboot/+/64666/comment/309795ae_4a48f2ae
PS1, Line 7: select SSE2
> Hmm.. the SSE2 default below is no longer honoured, but I think we can just remove it. My aopen/dxplplusu is the only that could break. And the comment may actually originate from romcc romstage times from around 2011.
>
> if CPU_INTEL_SOCKET_MPGA604
> select CPU_INTEL_MODEL_F2X
> ,,,
> select SSE
>
> # mPGA604 are usually Intel Netburst CPUs which should have SSE2
> # but the ramtest.c code on the Dell S1850 seems to choke on
> # enabling it, so disable it for now.
> config SSE2
> bool
> default n
Let's keep it then. The pre-SSE2 mfence should also work.
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