coreboot-gerrit June 2022

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Change in coreboot[master]: mb/google/brask/var/kuldax: Update gpio table
by David Wu (Code Review) 01 Jun '22

01 Jun '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64862 ) Change subject: mb/google/brask/var/kuldax: Update gpio table ...................................................................... mb/google/brask/var/kuldax: Update gpio table Based on latest schematic to update the gpio table. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309 --- A src/mainboard/google/brya/variants/kuldax/Makefile.inc A src/mainboard/google/brya/variants/kuldax/gpio.c 2 files changed, 134 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/64862/1 diff --git a/src/mainboard/google/brya/variants/kuldax/Makefile.inc b/src/mainboard/google/brya/variants/kuldax/Makefile.inc new file mode 100644 index 0000000..d38141c --- /dev/null +++ b/src/mainboard/google/brya/variants/kuldax/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/kuldax/gpio.c b/src/mainboard/google/brya/variants/kuldax/gpio.c new file mode 100644 index 0000000..5282298 --- /dev/null +++ b/src/mainboard/google/brya/variants/kuldax/gpio.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + + /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/64862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309 Gerrit-Change-Number: 64862 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Use struct region to check overlapping sections
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63602 ) Change subject: cpu/x86/smm: Use struct region to check overlapping sections ...................................................................... Patch Set 20: (2 comments) File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/63602/comment/db510582_1e0bf30d PS19, Line 376: static unsigned int region_counter = 0; > A bit of asymmetry here, counter is in .bss while the list is on stack. […] Done https://review.coreboot.org/c/coreboot/+/63602/comment/61303c45_9097e653 PS19, Line 428: struct region region_list[SMM_REGIONS_ARRAY_SIZE] = {}; > If this blows the stack requirements for APs too, maybe put this in .bss instead? Done. Also added a comment to move it back to the stack once AP stacks are not a continuous region with BSP stack (CPU_INFO_V2 allows for that). -- To view, visit https://review.coreboot.org/c/coreboot/+/63602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Gerrit-Change-Number: 63602 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 11:00:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63655 ) Change subject: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names ...................................................................... Patch Set 8: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Gerrit-Change-Number: 63655 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 11:00:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/model_fxx: Select SSE2
by Kyösti Mälkki (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64666 ) Change subject: cpu/intel/model_fxx: Select SSE2 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/cpu/intel/model_f2x/Kconfig: https://review.coreboot.org/c/coreboot/+/64666/comment/af324529_9318b0ee PS1, Line 7: select SSE2 > > Hmm.. the SSE2 default below is no longer honoured, but I think we can just remove it. […] I'll do a followup that addresses mPGA604/Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/64666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Gerrit-Change-Number: 64666 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Jun 2022 11:00:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/smbios.h: Add PCIe Gen5 slot type definitions
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63653 ) Change subject: include/smbios.h: Add PCIe Gen5 slot type definitions ...................................................................... Patch Set 8: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624 Gerrit-Change-Number: 63653 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:59:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [VERY WIP]tests/cpu/x86/smm: Add unit tests
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63560 ) Change subject: [VERY WIP]tests/cpu/x86/smm: Add unit tests ...................................................................... Patch Set 20: Code-Review-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7462fa6155b8f8085256a027692cbead0ca3f08e Gerrit-Change-Number: 63560 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:59:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Use struct region to check overlapping sections
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Arthur Heymans, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63602 to look at the new patch set (#20). Change subject: cpu/x86/smm: Use struct region to check overlapping sections ...................................................................... cpu/x86/smm: Use struct region to check overlapping sections This allows for some runtime checks on all SMM elements and removes the need for manual checks. We can drop completely separate codepaths on SMM_TSEG & SMM_ASEG as the only difference is where permanent handler gets placed. TESTED on prodrive/hermes and qemu with SSM_ASEG with 4 cores & SMM_TSEG with 128 cores. This code figured out quite some problems with overlapping regions so I think this is the right approach. Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 122 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63602/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/63602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Gerrit-Change-Number: 63602 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [HACK] Add an option to use ADL-S IOT FSP
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63578 ) Change subject: [HACK] Add an option to use ADL-S IOT FSP ...................................................................... Patch Set 10: Verified-1 (183 comments) File src/soc/intel/alderlake/include/fsp/FirmwareVersionInfoHob.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b532fd23_5f1987b1 PS10, Line 29: UINT8 MajorVersion; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/eddef06c_f5c6627c PS10, Line 30: UINT8 MinorVersion; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/689d1030_22908ef7 PS10, Line 31: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a0e38e02_e139117e PS10, Line 32: UINT16 BuildNumber; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a48cb306_c0db7796 PS10, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/39edad9d_38cf8b71 PS10, Line 39: UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a42cdbfb_4fff38fe PS10, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b8b805f4_6922ef43 PS10, Line 40: UINT8 VersionStringIndex; ///< Offset 1 Index of Version String please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2bbfc723_dbbd9293 PS10, Line 41: FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/0b4b69e5_f7cd09d7 PS10, Line 49: UINT8 Type; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/59734345_dcedcf20 PS10, Line 50: UINT8 Length; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/75b32394_4aaa5623 PS10, Line 51: UINT16 Handle; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d9081fb5_6ccde207 PS10, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ce58b517_62c5b74e PS10, Line 59: EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/378e13c5_653681ee PS10, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/5a43e911_cf83c2aa PS10, Line 60: SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/51a017bf_3583dd8d PS10, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/10466ded_8f432463 PS10, Line 61: UINT8 Count; ///< Offset 28 Number of FVI elements included. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/88bc8d8d_291fe00c PS10, Line 68: #endif // _FIRMWARE_VERSION_INFO_HOB_H_ adding a line without newline at end of file File src/soc/intel/alderlake/include/fsp/MemInfoHob.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ba386b04_c350c6d0 PS10, Line 22: #pragma pack (push, 1) space prohibited between function name and open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c8dd7868_fa0542b9 PS10, Line 50: UINT16 HobType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b5ec8926_aae711ef PS10, Line 51: UINT16 HobLength; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/78a34c04_c4128911 PS10, Line 52: UINT32 Reserved; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b172b6bc_a54b42f5 PS10, Line 56: EFI_HOB_GENERIC_HEADER Header; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/041b036f_b2f238d9 PS10, Line 57: EFI_GUID Name; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f1858af0_7a39595e PS10, Line 80: UINT8 Major; ///< Major version number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/47e6db69_7ddc1911 PS10, Line 81: UINT8 Minor; ///< Minor version number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d69528be_439ca608 PS10, Line 82: UINT8 Rev; ///< Revision number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/85804641_ac1ee039 PS10, Line 83: UINT8 Build; ///< Build number please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4cc3e3f7_70d26fbb PS10, Line 109: #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7b77c833_4963784a PS10, Line 119: #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7f2f79b1_dfb5f8a7 PS10, Line 124: bmCold, ///< Cold boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2070f9a5_e2272b7b PS10, Line 125: bmWarm, ///< Warm boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/86db86f2_cc7409e3 PS10, Line 126: bmS3, ///< S3 resume please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/000d346c_21b5e8ef PS10, Line 127: bmFast, ///< Fast boot please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6d777046_fcdd4004 PS10, Line 128: MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7188e115_5d35a6c7 PS10, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d692ce27_c7a72aa2 PS10, Line 129: MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/1db9d11d_65c05f47 PS10, Line 159: UINT32 tCK; ///< Memory cycle time, in femtoseconds. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/65470a98_113d6c03 PS10, Line 160: UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/bbb37273_3c8278e3 PS10, Line 161: UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b5fac1ff_927c8ad5 PS10, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6ed1b679_f8090f2e PS10, Line 162: UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a92565f4_bebf5261 PS10, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/636374da_ecb3e7f0 PS10, Line 163: UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c54560c1_0f7074bd PS10, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/14c068d5_0047d08c PS10, Line 164: UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/562a3bc7_d64d96fa PS10, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f03b36d6_c20b25ab PS10, Line 165: UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/07954669_fdf9c0ee PS10, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4f45a33e_f4f546bd PS10, Line 166: UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/35907dc0_d08c5fb6 PS10, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d61b22ce_e9ae2476 PS10, Line 167: UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/81b3a21b_52854541 PS10, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f779f0bb_730b455d PS10, Line 168: UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6ffb5873_6b1c2711 PS10, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6b265455_4c63a5cc PS10, Line 169: UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/44b6830b_f3986001 PS10, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/61b4691b_55cc5cd8 PS10, Line 170: UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/26e6645c_f3f06f4d PS10, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/1f8805b5_aa90288f PS10, Line 171: UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a07da471_ad02e81a PS10, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f9be315d_a39a002a PS10, Line 172: UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/1b121032_6ce6481a PS10, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/55437215_5a8bbc30 PS10, Line 173: UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e8e20649_369ac590 PS10, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6eaa2e6b_d3cad06f PS10, Line 174: UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/63331282_97127155 PS10, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ad9fe489_80f6ae3f PS10, Line 175: UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/28d87997_728838a6 PS10, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/dd00a2c5_6478d8a4 PS10, Line 176: UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b7799f93_0f30d2cc PS10, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4a9591f3_3c9ed4db PS10, Line 177: UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/bc9144c5_d21f905f PS10, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f46f10c8_b06bd174 PS10, Line 178: UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b1d4fbbe_8de307e6 PS10, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/0b1cb0d6_259a68dd PS10, Line 179: UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c55f9240_49c504fd PS10, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/34223e70_08a036b2 PS10, Line 180: UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/52757b52_02964ee5 PS10, Line 184: UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/78b96182_547b29c8 PS10, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/bbcdce42_f5927354 PS10, Line 191: UINT8 Status; ///< See MrcDimmStatus for the definition of this field. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/eeccefcc_da9afd6f PS10, Line 192: UINT8 DimmId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/8a5c384f_b22a2ecf PS10, Line 193: UINT32 DimmCapacity; ///< DIMM size in MBytes. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b9aa6bf9_7c509a18 PS10, Line 194: UINT16 MfgId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/dbd93168_c6ba4565 PS10, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7141bec8_848702f4 PS10, Line 195: UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f4a34731_1240e0e4 PS10, Line 196: UINT8 RankInDimm; ///< The number of ranks in this DIMM. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/970855d0_b7419f9a PS10, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/baa989f5_220ce28c PS10, Line 197: UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/43cbe4b3_d8ee4605 PS10, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2724943e_82028695 PS10, Line 198: UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f20f10c4_4602f5d9 PS10, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4b44a1c1_324f7f49 PS10, Line 199: UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/59a30147_a1c4a8b0 PS10, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/273cd5f5_9af6e257 PS10, Line 200: UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/3d487bda_128f0cda PS10, Line 201: UINT16 Speed; ///< The maximum capable speed of the device, in MHz please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ef2acac4_88508041 PS10, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/cec3e5b4_705b3803 PS10, Line 202: UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c66d2954_42f95b81 PS10, Line 206: UINT8 Status; ///< Indicates whether this channel should be used. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2f9b0289_6eaa3067 PS10, Line 207: UINT8 ChannelId; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f745af8b_54722a5f PS10, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ed870e06_c6de17af PS10, Line 208: UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/34c04cb6_af8fa2b6 PS10, Line 209: MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/978038a2_63e0c4e6 PS10, Line 210: DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f9246415_4aa1f5c4 PS10, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/87b0b6ea_7ecbe2c3 PS10, Line 214: UINT8 Status; ///< Indicates whether this controller should be used. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ce88991d_e862271d PS10, Line 215: UINT16 DeviceId; ///< The PCI device id of this memory controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/014cc1d2_8593f120 PS10, Line 216: UINT8 RevisionId; ///< The PCI revision id of this memory controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/21fb96ef_4021de79 PS10, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/75e759e2_a8f0cffb PS10, Line 217: UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7e5ddb7c_e3f19125 PS10, Line 218: CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f68468ea_22b06dae PS10, Line 222: UINT64 BaseAddress; ///< Trace Base Address please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/870b2f1f_d4ee939c PS10, Line 223: UINT64 TotalSize; ///< Total Trace Region of Same Cache type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/caa2a01b_6a2baa11 PS10, Line 224: UINT8 CacheType; ///< Trace Cache Type please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e293e14e_d6eddf6c PS10, Line 225: UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7224a842_8c705b20 PS10, Line 226: UINT8 Rsvd[2]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/8eb01d32_5601f7f2 PS10, Line 231: UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d3e138be_e44a0116 PS10, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e2c25750_7cab0ede PS10, Line 232: MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/27886118_33d79d88 PS10, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/81e2f057_92f944bb PS10, Line 233: MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4a051aba_785d8bf9 PS10, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/0dbe5617_bdfb4bf6 PS10, Line 238: UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/675b2a8f_41730aaa PS10, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/40378e3c_91ee49d5 PS10, Line 239: UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/10de98ef_178d6fc9 PS10, Line 240: HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/736bf992_d081dcee PS10, Line 244: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c95dd693_9638065d PS10, Line 245: UINT16 DataWidth; ///< Data width, in bits, of this memory device please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2d1dc8ca_8ead2ec7 PS10, Line 249: UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/1b005150_02dc3233 PS10, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b13fb000_f28dc072 PS10, Line 250: UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/db41c3e5_827caaca PS10, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/de2132b2_81b007f9 PS10, Line 251: UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/18ae6337_b840b913 PS10, Line 255: UINT8 ErrorCorrectionType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/92dcb7e4_0584489a PS10, Line 257: SiMrcVersion Version; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/fd4a5428_22455943 PS10, Line 258: BOOLEAN EccSupport; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2d12c94d_90e79f59 PS10, Line 259: UINT8 MemoryProfile; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6099f51f_dca4cc43 PS10, Line 260: UINT8 IsDMBRunning; ///< Deprecated. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e9bf877b_f7d5e225 PS10, Line 261: UINT32 TotalPhysicalMemorySize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e370fa29_16db7273 PS10, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/69268dc2_b0794c8f PS10, Line 262: UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f9646af2_e7a93593 PS10, Line 264: /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/aaa72e5a_d4e1cb37 PS10, Line 271: UINT8 XmpProfileEnable; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6f532a90_9126c4a8 PS10, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2d1bd526_792fc4c6 PS10, Line 272: UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/54972f23_f81ece4d PS10, Line 273: UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e25829b8_2496b593 PS10, Line 274: UINT8 RefClk; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/bdf58fa6_813f0a79 PS10, Line 275: UINT32 VddVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/f3ee5795_0b0ddaa1 PS10, Line 276: UINT32 VddqVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/775a5507_76a17201 PS10, Line 277: UINT32 VppVoltage[MAX_PROFILE_NUM]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/3051f9a5_25f28af6 PS10, Line 278: CONTROLLER_INFO Controller[MAX_NODE]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2ce751b0_2c83a167 PS10, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/0bdc70cc_49900635 PS10, Line 279: UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/03733549_cd529732 PS10, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/79fb7770_fb61247c PS10, Line 280: UINT32 NumPopulatedChannels; ///< Total number of memory channels populated please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/c472dc32_2c5d4b88 PS10, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d81dcd0d_62823b18 PS10, Line 281: HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/541222b5_2a627493 PS10, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d56d3c9c_1ce9763f PS10, Line 282: UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/61afca43_71f71849 PS10, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/7c4f9047_2164ae97 PS10, Line 283: BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/07d017ba_d11bcf9f PS10, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/50de211d_62ba3684 PS10, Line 284: BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e0a49463_00221986 PS10, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/2611b8c7_9514149f PS10, Line 285: BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a65e58df_cb679c70 PS10, Line 297: UINT8 Revision; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/4db67764_9063529f PS10, Line 298: UINT8 Reserved[3]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/bfdf34be_832b1716 PS10, Line 299: UINT32 BootMode; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/9d8d1451_2197762c PS10, Line 300: UINT32 TsegSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/58240d4e_8358a315 PS10, Line 301: UINT32 TsegBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6b108fd6_fb267717 PS10, Line 302: UINT32 PrmrrSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/078cc887_f72e89be PS10, Line 303: UINT64 PrmrrBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/affe48d7_aee89133 PS10, Line 304: UINT32 GttBase; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/d045fee3_c6678025 PS10, Line 305: UINT32 MmioSize; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/ead67c49_1989fafd PS10, Line 306: UINT32 PciEBaseAddress; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/b5a74ea2_62a2ea24 PS10, Line 307: PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/cb732039_a75ce463 PS10, Line 308: PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/266b2af5_e6e3f6f9 PS10, Line 309: BOOLEAN MrcBasicMemoryTestPass; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/a35d9e69_34b52834 PS10, Line 313: EFI_HOB_GUID_TYPE EfiHobGuidType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/1180ba6c_5296283f PS10, Line 314: MEMORY_PLATFORM_DATA Data; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/e6252401_e3051f6c PS10, Line 315: UINT8 *Buffer; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150245): https://review.coreboot.org/c/coreboot/+/63578/comment/6979d400_ddca1454 PS10, Line 318: #pragma pack (pop) space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/63578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97198b1faa3e3c57f4950b0d69df1e6c43d289c3 Gerrit-Change-Number: 63578 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:59:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

1 0

Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63499 ) Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree ...................................................................... Patch Set 16: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Gerrit-Change-Number: 63499 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 10:57:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2022