coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/fast_spi: Use smarter mtrr code in ramstage
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63550 ) Change subject: soc/intel/fast_spi: Use smarter mtrr code in ramstage ...................................................................... soc/intel/fast_spi: Use smarter mtrr code in ramstage mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It will compute a new optimal solution with the temp ranges included while also taking care of the cleanup before loading the payload/s3 resume. Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index c07b565..ed61c10 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -223,6 +223,11 @@ static void fast_spi_enable_cache_range(unsigned int base, unsigned int size) { + if (ENV_RAMSTAGE) { + mtrr_use_temp_range(base, size, MTRR_TYPE_WRPROT); + return; + } + const int type = MTRR_TYPE_WRPROT; int mtrr = get_free_var_mtrr(); if (mtrr == -1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Gerrit-Change-Number: 63550 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "cpu/x86: Add function to set `put_back_original_solution` var...
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64803 ) Change subject: Revert "cpu/x86: Add function to set `put_back_original_solution` variable" ...................................................................... Revert "cpu/x86: Add function to set `put_back_original_solution` variable" Now that mtrr_use_temp_range() can deal with multiple ranges there is no need to expose this to restore the MTRR solution. This reverts commit 00aaffaf470adfbaa0fbfa0ec3cc67311763810b. Change-Id: Ib77a0f52228cd2f19f3227824f704ac690be4aba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64803 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/mtrr/mtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 1 insertion(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d1098d9..6d4aa57 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -861,11 +861,6 @@ static bool put_back_original_solution; -void need_restore_mtrr(void) -{ - put_back_original_solution = true; -} - void mtrr_use_temp_range(uintptr_t begin, size_t size, int type) { const struct range_entry *r; @@ -935,7 +930,7 @@ (long long)begin, (long long)begin + size - 1, (long long)size, type); else - need_restore_mtrr(); + put_back_original_solution = true; memranges_teardown(&addr_space); } diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 5397d3394..b2bc2c8 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -96,7 +96,6 @@ /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); -void need_restore_mtrr(void); /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/64803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib77a0f52228cd2f19f3227824f704ac690be4aba Gerrit-Change-Number: 64803 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63555 ) Change subject: cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges ...................................................................... cpu/x86/mtrr: Allow for multiple TEMP MTRR ranges Temporary MTRR setup usually covers the memory mapped flash. On recent Intel hardware the mapping is not coherent. It uses an external window for parts of the BIOS region that exceed 16M. This now allows up to 10 temporary memory ranges. TESTED: Qemu with multiple MTRR temporary MTRR ranges sets up a valid and optimized temporary MTRR solution. Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63555 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/cpu/x86/mtrr/mtrr.c 1 file changed, 28 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d8903b8..d1098d9 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -9,6 +9,7 @@ */ #include <stddef.h> +#include <stdint.h> #include <string.h> #include <bootstate.h> #include <commonlib/helpers.h> @@ -873,6 +874,28 @@ struct memranges addr_space; const int above4gb = 1; /* Cover above 4GiB by default. */ int address_bits; + static struct temp_range { + uintptr_t begin; + size_t size; + int type; + } temp_ranges[10]; + + if (size == 0) + return; + + int i; + for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) { + if (temp_ranges[i].size == 0) { + temp_ranges[i].begin = begin; + temp_ranges[i].size = size; + temp_ranges[i].type = type; + break; + } + } + if (i == ARRAY_SIZE(temp_ranges)) { + printk(BIOS_ERR, "Out of temporary ranges for MTRR use\n"); + return; + } /* Make a copy of the original address space and tweak it with the * provided range. */ @@ -891,7 +914,11 @@ } /* Place new range into the address space. */ - memranges_insert(&addr_space, begin, size, type); + for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) { + if (temp_ranges[i].size != 0) + memranges_insert(&addr_space, temp_ranges[i].begin, + temp_ranges[i].size, temp_ranges[i].type); + } print_physical_address_space(&addr_space, "TEMPORARY"); -- To view, visit https://review.coreboot.org/c/coreboot/+/63555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Gerrit-Change-Number: 63555 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63502 ) Change subject: soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S ...................................................................... Patch Set 12: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Gerrit-Change-Number: 63502 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:48:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add basic FSP configuration in devicetree
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... Patch Set 14: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:47:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add GPIO configuration
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d25: add GPIO configuration ...................................................................... Patch Set 16: Verified+1 (15 comments) File src/mainboard/msi/ms7d25/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/05bad0e4_9e987009 PS16, Line 136: _PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/cdadcbca_e6afa204 PS16, Line 137: _PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/c19b0177_77874f18 PS16, Line 138: _PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0), /* GPIO */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/f6650b26_9c122ff3 PS16, Line 143: _PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_10 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/9a2af67e_ae0754a3 PS16, Line 146: _PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_13 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/c877633a_50c45918 PS16, Line 151: _PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_22 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/4dfe40b7_304a517f PS16, Line 154: _PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_25 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/ac74ca02_fc6be8c5 PS16, Line 165: _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* VGPIO_USB_0 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/97a65a63_6ef53a4a PS16, Line 166: _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* VGPIO_USB_1 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/56f986cd_c41734d6 PS16, Line 167: _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* VGPIO_USB_2 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/3bc0913d_faf13838 PS16, Line 168: _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), /* VGPIO_USB_3 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/ebb9ddb9_c2c42aee PS16, Line 169: _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_USB_8 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/b221c4b8_9df8ae6e PS16, Line 170: _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_USB_9 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/4f15d26f_72ccc19d PS16, Line 171: _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_USB_10 */ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-150190): https://review.coreboot.org/c/coreboot/+/63490/comment/8d514c1b_a261135f PS16, Line 172: _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* VGPIO_USB_11 */ line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:46:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "cpu/x86/smm: Remove heap"
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Nico Huber, Reka Norman, Eric Lai, Kyösti Mälkki, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64853 ) Change subject: Revert "cpu/x86/smm: Remove heap" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I tested ADL and the SMI handler works on all APs. Can maybe using a newer coreboot revision works for you? Notice that I needed https://review.coreboot.org/c/coreboot/+/64426 to be able to boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/64853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd782159b43091fff66fe075b77a3dc20d5e6e32 Gerrit-Change-Number: 64853 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:46:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by build bot (Jenkins) (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... Patch Set 14: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 14 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:46:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Igor Bagnucki, Michał Kopeć, Angel Pons. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63463 ) Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... Patch Set 9: (2 comments) File src/mainboard/msi/ms7d25/Kconfig: https://review.coreboot.org/c/coreboot/+/63463/comment/46119ac3_5fbca787 PS8, Line 9: select SUPERIO_NUVOTON_NCT6776 > SUPERIO_NUVOTON_NCT6687D of course This is fixed already https://review.coreboot.org/c/coreboot/+/63463/comment/619e662d_ad834e96 PS8, Line 30: config DEVICETREE : default "devicetree.cb" > Shouldn't be needed Removed -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:45:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2022