coreboot-gerrit June 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code when calling FSP
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Arthur Heymans, Andrey Petrov. Hello build bot (Jenkins), Raul Rangel, Michał Kopeć, Mario Scheithauer, Angel Pons, Lean Sheng Tan, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64426 to look at the new patch set (#4). Change subject: driver/intel/fsp2_0: Disable NULL deref code when calling FSP ...................................................................... driver/intel/fsp2_0: Disable NULL deref code when calling FSP FSP needs interrupts disable so also disable generating exceptions around debug registers. Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/null_breakpoint.h M src/arch/x86/null_breakpoint.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 5 files changed, 31 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/64426/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/msi/ms7d25: Fill board-specific SMBIOS data
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski. Michał Kopeć has uploaded a new patch set (#7) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/64050 ) Change subject: mainboard/msi/ms7d25: Fill board-specific SMBIOS data ...................................................................... mainboard/msi/ms7d25: Fill board-specific SMBIOS data Add board connectors and headers descriptions to SMBIOS. Specify type 1 and type 2 fields as in vendor firmware. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 --- M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7d25/mainboard.c 2 files changed, 382 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/64050/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/64050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 Gerrit-Change-Number: 64050 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Michał Kopeć (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Michał Żygowski, Igor Bagnucki, Michał Kopeć. Michał Kopeć has uploaded a new patch set (#10) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/63463 ) Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A configs/config.msi_ms7d25 A src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/Kconfig.name A src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/board_info.txt A src/mainboard/msi/ms7d25/bootblock.c A src/mainboard/msi/ms7d25/devicetree.cb A src/mainboard/msi/ms7d25/dsdt.asl A src/mainboard/msi/ms7d25/hda_verb.c A src/mainboard/msi/ms7d25/mainboard.c A src/mainboard/msi/ms7d25/romstage_fsp_params.c 11 files changed, 283 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code on some FSP
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Arthur Heymans, Andrey Petrov. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code on some FSP ...................................................................... Patch Set 3: (3 comments) Patchset: PS3: Let's just do it for all FSP. The spec says to disable interrupts. Debug registers are not interrupts but exceptions... However this problem seems to be so common that it makes sense to generally disable this feature when entering FSP. File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/64426/comment/14a7a79f_3ba9a063 PS2, Line 388: acces > access Done File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/64426/comment/d2fec047_638575b7 PS2, Line 297: if (CONFIG(FSP_ACCESSES_NULL_WORKAROUND)) : null_breakpoint_disable(); : post_code(POST_FSP_MEMORY_INIT); : timestamp_add_now(TS_FSP_MEMORY_INIT_START); : if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) : status = protected_mode_call_2arg(fsp_raminit, : (uintptr_t)&fspm_upd, : (uintptr_t)fsp_get_hob_list_ptr()); : else : status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); : if (CONFIG(FSP_ACCESSES_NULL_WORKAROUND)) : null_breakpoint_init(); : > Can you please implement this for silicon init (silicon_init.c) as well? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:44:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code on some FSP
by Lean Sheng Tan (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Mario Scheithauer, Arthur Heymans, Andrey Petrov. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code on some FSP ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/64426/comment/a545d77c_78682a45 PS2, Line 297: if (CONFIG(FSP_ACCESSES_NULL_WORKAROUND)) : null_breakpoint_disable(); : post_code(POST_FSP_MEMORY_INIT); : timestamp_add_now(TS_FSP_MEMORY_INIT_START); : if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) : status = protected_mode_call_2arg(fsp_raminit, : (uintptr_t)&fspm_upd, : (uintptr_t)fsp_get_hob_list_ptr()); : else : status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); : if (CONFIG(FSP_ACCESSES_NULL_WORKAROUND)) : null_breakpoint_init(); : > Can you please implement this for silicon init (silicon_init.c) as well? […] Hi Mario, I also saw the same issue on ADL, with the latest patch the issue should fix now. Could you try? -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:44:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code on some FSP
by Arthur Heymans (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Arthur Heymans, Andrey Petrov. Hello build bot (Jenkins), Raul Rangel, Michał Kopeć, Mario Scheithauer, Angel Pons, Lean Sheng Tan, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64426 to look at the new patch set (#3). Change subject: driver/intel/fsp2_0: Disable NULL deref code on some FSP ...................................................................... driver/intel/fsp2_0: Disable NULL deref code on some FSP FSP needs interrupts disable so also disable generating exceptions around debug registers. Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/null_breakpoint.h M src/arch/x86/null_breakpoint.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 5 files changed, 31 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/64426/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/intel/fsp2_0: Disable NULL deref code on some FSP
by Lean Sheng Tan (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Arthur Heymans, Andrey Petrov. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64426 ) Change subject: driver/intel/fsp2_0: Disable NULL deref code on some FSP ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/64426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia49dde68d45b71e231aaf32a0e6fd847f0e06146 Gerrit-Change-Number: 64426 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:38:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intelblocks/gpio.c: Handle NULL return values from child functions
by Maulik V Vaghela (Code Review) 01 Jun '22

01 Jun '22

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64857 ) Change subject: intelblocks/gpio.c: Handle NULL return values from child functions ...................................................................... intelblocks/gpio.c: Handle NULL return values from child functions gpio_configure_pad function gets called for most of the GPIO configuration for all the boards. This function is not handling NULL pointers properly which can cause exception in CPU. This patch fixes the handling and function is able to return early in case the NULL pointer is passed or any subsequent child function calls return NULL. BUG=None BRANCH=None TEST=Compilation works fine for all Alder Lake boards. Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/64857/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d12281f..baf0e16 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -331,11 +331,23 @@ static void gpio_configure_pad(const struct pad_config *cfg) { - const struct pad_community *comm = gpio_get_community(cfg->pad); + const struct pad_community *comm; uint16_t config_offset; uint32_t pad_conf, soc_pad_conf; int i, pin, group; + if (!cfg) { + printk(BIOS_ERR, "%s: cfg value is NULL\n", __func__); + return; + } + + comm = gpio_get_community(cfg->pad); + if (!comm) { + printk(BIOS_ERR, "%s: Could not find community for pad: 0x%x\n", + __func__, cfg->pad); + return; + } + config_offset = pad_config_offset(comm, cfg->pad); pin = relative_pad_in_comm(comm, cfg->pad); group = gpio_group_index(comm, pin); -- To view, visit https://review.coreboot.org/c/coreboot/+/64857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388 Gerrit-Change-Number: 64857 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax
by John Su (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64856 to look at the new patch set (#2). Change subject: mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax ...................................................................... mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax Follow thermal table from thermal team. Chang list: 1. Update TEMP_PCT of Active Policy for TSR1. BUG=b:230829301 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c --- M src/mainboard/google/brya/variants/mithrax/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/64856/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c Gerrit-Change-Number: 64856 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Update coreboot 4.17 release notes
by Sean Rhodes (Code Review) 01 Jun '22

01 Jun '22

Attention is currently required from: Felix Singer, Martin L Roth, Nicholas Chin. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64846 ) Change subject: Documentation: Update coreboot 4.17 release notes ...................................................................... Patch Set 3: (1 comment) File Documentation/releases/coreboot-4.17-relnotes.md: https://review.coreboot.org/c/coreboot/+/64846/comment/d364d492_1cd567b3 PS3, Line 30: Star Labs Star Labs Ideally: sed 's/Star Labs Star Labs/Star/' Are these generated? -- To view, visit https://review.coreboot.org/c/coreboot/+/64846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9491ad9aa6ab3eb5504bee85591f3b1d9bf6cc2 Gerrit-Change-Number: 64846 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin L Roth <gaumless(a)tutanota.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Jun 2022 09:25:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2022